EPIC: Hardware-engineer course track -- 10 new 9x3 courses and fixes to the 4 existing ones #1476

Goal

Turn t27.ai/#/course into a full hardware-engineer track: every course 9 modules x 3 lessons = 27 lessons, every lesson a widget plus a .t27 spec that runs in the reader's browser, English by default with an RU contract, black-and-white share cards, SEO pages, and a blog post (EN + RU) per course PR.

This epic is planning only: each child issue is a full decomposition (27 lessons, the spec each lesson opens, a widget idea, and the specs still to be written). Nothing is implemented here.

State on 2026-10-07

Note: t27.ai has not deployed since 2026-10-04; see #1475.

Key findings from the review

1. Hardware specs do not run in the browser. Every hardware spec tried typechecks and lowers to HIR. Their tests still fail in the runner on locals, calls and struct fields. constsOf also crashes on 100_000_000, 0x03, 0b..., unary and identifier constants. Examples: clock_domain (12 failures), fifo (18), axi4 (16), tri27_machine (93). Two ai-numbers lesson specs fail too. Hardware lessons fall back to recorded casts. Course infra: browser test runner must run hardware specs (calls, locals, struct fields, hex/binary/underscore literals) #1477 blocks every course below.
2. Course 1 repeats Course 0. It reteaches hello, tests, compiler stages and seven backends. 11 of its lessons open a spec that does not match the lesson topic, including generic specs/tutorial/* files on hardware lessons (Course 1 (FPGA): remove overlap with Course 0 and give every lesson a hardware spec #1478).
3. GoldenFloat is a width table. 17 of its 27 lessons are one per width. It has no hardware cost per format and no cross-links (Course 3 (GoldenFloat): teach concepts, not one lesson per width; add hardware cost per format #1479).
4. The repo already holds most of the material. About 35 fpga/ specs, 30 testbenches, 18 ISA specs, 64 ternary specs and 60+ tri fpga-* / x7-* tool specs. Most new courses below are grounded in existing specs, not invented.

Child issues

Infrastructure (do first)

• Course infra: browser test runner must run hardware specs (calls, locals, struct fields, hex/binary/underscore literals) #1477 Browser test runner: calls, locals, struct fields, literal forms
• Hardware track: course map, prerequisites, capstone receipts and a shared lesson-quality checklist #1481 Hardware track: course map, prerequisites, capstone receipts, duplicate-lesson check

Fixes to existing courses

• Course 1 (FPGA): remove overlap with Course 0 and give every lesson a hardware spec #1478 Course 1 (FPGA): remove overlap with Course 0, hardware spec per lesson
• Course 2 (AI numbers): make lessons runnable instead of recorded, and hand datapath topics to the accelerator course #1480 Course 2 (AI numbers): runnable lessons, hand datapath to the accelerator course
• Course 3 (GoldenFloat): teach concepts, not one lesson per width; add hardware cost per format #1479 Course 3 (GoldenFloat): concepts not widths, hardware cost per format

New hardware courses (9x3 each, decomposed)

Ship order:

1. Course infra: browser test runner must run hardware specs (calls, locals, struct fields, hex/binary/underscore literals) #1477, Course 1 (FPGA): remove overlap with Course 0 and give every lesson a hardware spec #1478
2. verify-hardware + clocks-and-cdc (most existing specs, highest demand)
3. buses-and-peripherals + open-toolchain
4. ternary-computer + ai-accelerator
5. arithmetic-circuits, which supplies CORDIC for DSP
6. power-and-test
7. dsp-and-radio
8. fpga-to-silicon

Golden Ruler (arXiv:2606.09686) stays on the roadmap as a formats course. Its conformance vectors are used as a test corpus by #1483 and #1479.

Rules for every child

• Spec first in gHashTag/t27, then copied here (t27-spec-first); only t27 for new code.
• Numbers only from real tool output named in DATA_SOURCES; board named on every page.
• Hardware results are on the Artix-7 FPGA prototype; no silicon claims anywhere (TTSKY26a/b were withdrawn, no die exists).