Parent epic: #1476
Course id: verify-hardware
Audience: hardware engineers (RTL / FPGA / ASIC).
Prerequisites: Course 0 (t27 basics) module tests-and-functions; Course 1 module program.
Why this course
Verification is more than half of real hardware work, and it is where t27's claim (the spec IS the test) is strongest. The repo has 30 *_tb testbenches, VCD tracing and comparison, a formal spec, cosimulation and mutation tooling (tri x7-mutate). None of it is taught. Verification engineers are a large audience that the current courses ignore.
What already exists in the repo (grounding)
fpga/testbench.t27, 30 files under fpga/testbench/*_tb.t27, fpga/simulator.t27
fpga/vcd_trace.t27, fpga/vcd_conformance_compare.t27
fpga/formal.t27 + formal_tb, fpga/verification/build_verify.t27
conformance/e2e_scenarios.t27, numeric/formats_catalog.t27 (bit-exact vectors)
tools/trios/tri/x7-mutate.t27, fpga-batch-cosim.t27, fpga-selftest.t27
Decomposition: 9 modules x 3 lessons
Module 1 -- why-verify: the spec is the golden model
| # |
Lesson id |
What the reader learns |
Spec |
Widget idea |
| 1 |
bugs-that-compile |
classes of bugs that pass synthesis |
fpga/testbench/uart_tb.t27 |
bug gallery, each with the test that catches it |
| 2 |
golden-model |
spec tests as a reference model for RTL |
fpga/testbench.t27 |
spec vs RTL side by side |
| 3 |
plan-before-code |
a verification plan: features x checks |
fpga/verification/build_verify.t27 |
plan table from the spec |
Module 2 -- testbenches: stimulus, check, report
| # |
Lesson id |
What the reader learns |
Spec |
Widget idea |
| 4 |
anatomy-of-a-tb |
what every *_tb spec has in common |
fpga/testbench/fifo_tb.t27 |
tb anatomy annotator |
| 5 |
self-checking |
assertions instead of eyeballing waves |
fpga/testbench/spi_tb.t27 |
pass/fail matrix of the tb |
| 6 |
directed-vs-random |
directed cases vs constrained random |
fpga/testbench/uart_tb.t27 |
random stimulus generator with seed |
Module 3 -- waveforms: reading what happened
| # |
Lesson id |
What the reader learns |
Spec |
Widget idea |
| 7 |
vcd-format |
the VCD format line by line |
fpga/vcd_trace.t27 |
vcd-wrapped |
| 8 |
debug-with-waves |
finding a bug in a trace |
fpga/vcd_trace.t27 |
test-waves with a planted bug |
| 9 |
compare-traces |
conformance by trace comparison |
fpga/vcd_conformance_compare.t27 |
diff of two VCDs |
Module 4 -- conformance-vectors: bit-exact or nothing
| # |
Lesson id |
What the reader learns |
Spec |
Widget idea |
| 10 |
what-a-vector-is |
input, expected output, bit-exact |
numeric/formats_catalog.t27 |
vector browser |
| 11 |
golden-ruler-vectors |
the Golden Ruler catalog as a test corpus (arXiv:2606.09686) |
numeric/formats_catalog.t27 |
format -> vectors -> pass count |
| 12 |
end-to-end-scenarios |
scenario tests across the whole pipeline |
conformance/e2e_scenarios.t27 |
scenario timeline |
Module 5 -- cosimulation: spec, RTL and board must agree
| # |
Lesson id |
What the reader learns |
Spec |
Widget idea |
| 13 |
three-way-agreement |
spec vs simulator vs board |
tools/trios/tri/fpga-batch-cosim.t27 |
three-column agreement table |
| 14 |
simulator-internals |
event-driven vs cycle-based simulation |
fpga/simulator.t27 |
event queue stepper |
| 15 |
when-they-disagree |
triage a cosim mismatch |
tools/trios/tri/fpga-batch-cosim.t27 |
mismatch walkthrough from a real run |
Module 6 -- coverage: what you did not test
| # |
Lesson id |
What the reader learns |
Spec |
Widget idea |
| 16 |
line-and-toggle |
line and toggle coverage |
NEW fpga/coverage.t27 |
coverage heatmap over the spec |
| 17 |
fsm-coverage |
state and transition coverage |
NEW fpga/coverage.t27 |
fsm-sketch with visited edges |
| 18 |
coverage-lies |
100% coverage with a broken design |
fpga/testbench/fifo_tb.t27 |
counter-example |
Module 7 -- formal: proof instead of samples
| # |
Lesson id |
What the reader learns |
Spec |
Widget idea |
| 19 |
assertions |
immediate vs temporal assertions |
fpga/formal.t27 |
assertion editor with verdict |
| 20 |
bounded-model-checking |
BMC: depth, counterexamples |
fpga/formal.t27 |
counterexample trace |
| 21 |
induction |
k-induction and why BMC is not a proof |
fpga/testbench/formal_tb.t27 |
induction step visual |
Module 8 -- mutation: testing the tests
| # |
Lesson id |
What the reader learns |
Spec |
Widget idea |
| 22 |
kill-the-mutant |
mutation testing: change the design, a test must fail |
tools/trios/tri/x7-mutate.t27 |
mutant scoreboard |
| 23 |
surviving-mutants |
what a surviving mutant tells you |
tools/trios/tri/x7-mutate.t27 |
survivor list from a real run |
| 24 |
test-strength |
mutation score vs coverage |
tools/trios/tri/x7-mutate.t27 |
two-axis plot |
Module 9 -- sign-off: done means proven
| # |
Lesson id |
What the reader learns |
Spec |
Widget idea |
| 25 |
build-verify |
the sign-off checklist as a spec |
fpga/verification/build_verify.t27 |
checklist with live verdicts |
| 26 |
board-selftest |
self-test on the board |
tools/trios/tri/fpga-selftest.t27 |
self-test log replay |
| 27 |
capstone |
verify a peripheral: tb + formal + mutation + board |
fpga/uart.t27 |
sign-off receipt |
Specs that do not exist yet (write in gHashTag/t27 first)
Honesty notes and traps
- The browser runner cannot run most
*_tb specs today (calls, locals, struct fields). This course is the strongest reason to land that issue first.
- Avoid repeating Course 1 lesson
tests-are-the-spec; link to it.
Acceptance criteria
Blocked by: #1477 (browser test runner) for every lesson whose spec uses calls, locals or struct fields in tests.
Parent epic: #1476
Course id:
verify-hardwareAudience: hardware engineers (RTL / FPGA / ASIC).
Prerequisites: Course 0 (t27 basics) module
tests-and-functions; Course 1 moduleprogram.Why this course
Verification is more than half of real hardware work, and it is where t27's claim (the spec IS the test) is strongest. The repo has 30
*_tbtestbenches, VCD tracing and comparison, a formal spec, cosimulation and mutation tooling (tri x7-mutate). None of it is taught. Verification engineers are a large audience that the current courses ignore.What already exists in the repo (grounding)
fpga/testbench.t27, 30 files underfpga/testbench/*_tb.t27,fpga/simulator.t27fpga/vcd_trace.t27,fpga/vcd_conformance_compare.t27fpga/formal.t27+formal_tb,fpga/verification/build_verify.t27conformance/e2e_scenarios.t27,numeric/formats_catalog.t27(bit-exact vectors)tools/trios/tri/x7-mutate.t27,fpga-batch-cosim.t27,fpga-selftest.t27Decomposition: 9 modules x 3 lessons
Module 1 --
why-verify: the spec is the golden modelbugs-that-compilefpga/testbench/uart_tb.t27golden-modelfpga/testbench.t27plan-before-codefpga/verification/build_verify.t27Module 2 --
testbenches: stimulus, check, reportanatomy-of-a-tb*_tbspec has in commonfpga/testbench/fifo_tb.t27self-checkingfpga/testbench/spi_tb.t27directed-vs-randomfpga/testbench/uart_tb.t27Module 3 --
waveforms: reading what happenedvcd-formatfpga/vcd_trace.t27debug-with-wavesfpga/vcd_trace.t27compare-tracesfpga/vcd_conformance_compare.t27Module 4 --
conformance-vectors: bit-exact or nothingwhat-a-vector-isnumeric/formats_catalog.t27golden-ruler-vectorsnumeric/formats_catalog.t27end-to-end-scenariosconformance/e2e_scenarios.t27Module 5 --
cosimulation: spec, RTL and board must agreethree-way-agreementtools/trios/tri/fpga-batch-cosim.t27simulator-internalsfpga/simulator.t27when-they-disagreetools/trios/tri/fpga-batch-cosim.t27Module 6 --
coverage: what you did not testline-and-togglefpga/coverage.t27fsm-coveragefpga/coverage.t27coverage-liesfpga/testbench/fifo_tb.t27Module 7 --
formal: proof instead of samplesassertionsfpga/formal.t27bounded-model-checkingfpga/formal.t27inductionfpga/testbench/formal_tb.t27Module 8 --
mutation: testing the testskill-the-mutanttools/trios/tri/x7-mutate.t27surviving-mutantstools/trios/tri/x7-mutate.t27test-strengthtools/trios/tri/x7-mutate.t27Module 9 --
sign-off: done means provenbuild-verifyfpga/verification/build_verify.t27board-selftesttools/trios/tri/fpga-selftest.t27capstonefpga/uart.t27Specs that do not exist yet (write in
gHashTag/t27first)fpga/coverage.t27-- line, toggle and FSM coverage modelHonesty notes and traps
*_tbspecs today (calls, locals, struct fields). This course is the strongest reason to land that issue first.tests-are-the-spec; link to it.Acceptance criteria
specs/course/<id>.t27+<id>-ru.t27exist, registered inspecs/course/courses.t27, built bycourse-from-spec.mjs(recipe:specs/course_recipe/course-27.t27).testblocks pass in the reader's browser (blocked by the browser-runner issue), or the lesson says plainly that it is a recordedtricast and links the recording.DATA_SOURCES(yosys / nextpnr / board run / spec test). No invented figures.xc7a200tfgg676vs AX7203xc7a200tfbg484vs Arty A7 / XC7A100T).body+ RUruBody.gHashTag/t27, then copied here).Blocked by: #1477 (browser test runner) for every lesson whose spec uses calls, locals or struct fields in tests.