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Course: Power, testability and bring-up -- where watts go and how chips are tested (9x3, hardware track) #1489
Description
Parent epic: #1476
Course id: power-and-test
Audience: hardware engineers (RTL / FPGA / ASIC).
Prerequisites: Course 1 (FPGA); Course verify-hardware module waveforms.
Why this course
Power and design-for-test are sign-off topics every ASIC and serious FPGA team owns, and almost no online course covers them hands-on. The repo has power, power_analysis and dft specs with testbenches, JTAG tooling, and board self-test and loop-check tools.
What already exists in the repo (grounding)
fpga/power.t27,fpga/power_analysis.t27,fpga/dft.t27+power_tb,power_analysis_tb,dft_tbfpga/vcd_trace.t27(switching activity source)tools/trios/tri/fpga-jtag.t27,fpga-selftest.t27,fpga-loopcheck.t27,fpga-tristate.t27
Decomposition: 9 modules x 3 lessons
Module 1 -- where-power-goes: the power equation
| # | Lesson id | What the reader learns | Spec | Widget idea |
|---|---|---|---|---|
| 1 | dynamic-and-static |
P = aCV^2*f + leakage | fpga/power.t27 |
power equation slider |
| 2 | activity-factor |
toggle rate from a real trace | fpga/power_analysis.t27 |
activity heatmap from VCD |
| 3 | clocks-cost-most |
why the clock tree dominates | fpga/power.t27 |
pie from the estimator |
Module 2 -- estimation: numbers before silicon
| # | Lesson id | What the reader learns | Spec | Widget idea |
|---|---|---|---|---|
| 4 | vectorless-vs-vcd |
vectorless vs simulation-based estimates | fpga/power_analysis.t27 |
two estimates side by side |
| 5 | estimator-limits |
what an estimator cannot know | fpga/power_analysis.t27 |
error bars |
| 6 | measure-on-board |
measuring board current | fpga/power.t27 |
measured vs estimated (when measured) |
Module 3 -- saving-power: design techniques
| # | Lesson id | What the reader learns | Spec | Widget idea |
|---|---|---|---|---|
| 7 | clock-enables |
clock enables instead of gated clocks | fpga/power.t27 |
toggle saved |
| 8 | operand-isolation |
stop idle datapaths from toggling | fpga/power.t27 |
before/after activity |
| 9 | ternary-and-power |
does ternary save switching? the honest answer | ternary/packed_trit.t27 |
measured toggles binary vs packed trits |
Module 4 -- thermal: heat
| # | Lesson id | What the reader learns | Spec | Widget idea |
|---|---|---|---|---|
| 10 | junction-temperature |
theta-JA, junction temperature limits | fpga/power.t27 |
thermal calculator |
| 11 | throttling |
designing for the thermal budget | fpga/power.t27 |
budget chart |
| 12 | power-and-timing |
temperature changes timing | fpga/timing.t27 |
slack vs temperature corners |
Module 5 -- scan: design for test
| # | Lesson id | What the reader learns | Spec | Widget idea |
|---|---|---|---|---|
| 13 | why-dft |
defects, fault models, stuck-at | fpga/dft.t27 |
fault injector |
| 14 | scan-chains |
muxed scan flops and chains | fpga/dft.t27 |
scan shift animation |
| 15 | atpg |
automatic test pattern generation basics | fpga/testbench/dft_tb.t27 |
pattern coverage |
Module 6 -- bist: the chip tests itself
| # | Lesson id | What the reader learns | Spec | Widget idea |
|---|---|---|---|---|
| 16 | lfsr |
LFSR pattern generators | fpga/dft.t27 |
LFSR stepper |
| 17 | misr |
signature compaction with a MISR | fpga/dft.t27 |
signature diff |
| 18 | memory-bist |
March tests for RAM | fpga/dft.t27 |
March algorithm stepper |
Module 7 -- boundary-scan: testing the board
| # | Lesson id | What the reader learns | Spec | Widget idea |
|---|---|---|---|---|
| 19 | tap-controller |
the JTAG TAP state machine | tools/trios/tri/fpga-jtag.t27 |
TAP walker |
| 20 | boundary-scan-cells |
EXTEST: driving pins without logic | tools/trios/tri/fpga-tristate.t27 |
pin driver |
| 21 | idcode-and-bypass |
IDCODE and BYPASS on a real chain | tools/trios/tri/fpga-jtag.t27 |
idcode |
Module 8 -- bring-up: first power-on
| # | Lesson id | What the reader learns | Spec | Widget idea |
|---|---|---|---|---|
| 22 | bring-up-plan |
what to check in which order | tools/trios/tri/fpga-selftest.t27 |
bring-up checklist |
| 23 | loopback |
loopback tests for IO | tools/trios/tri/fpga-loopcheck.t27 |
loopback log |
| 24 | when-it-is-dead |
triage a board that does not answer | tools/trios/tri/fpga-jtag.t27 |
decision tree |
Module 9 -- economics: why test costs money
| # | Lesson id | What the reader learns | Spec | Widget idea |
|---|---|---|---|---|
| 25 | test-time |
test time and tester cost | fpga/dft.t27 |
cost model |
| 26 | coverage-vs-cost |
fault coverage vs pattern count | fpga/testbench/dft_tb.t27 |
coverage curve |
| 27 | capstone |
add scan + BIST to a design, report power and coverage | fpga/dft.t27 |
sign-off receipt |
Honesty notes and traps
- No measured board power exists yet in the repo as far as found; until a measurement lands, every power figure is an estimate and the page says so.
Acceptance criteria
-
specs/course/<id>.t27+<id>-ru.t27exist, registered inspecs/course/courses.t27, built bycourse-from-spec.mjs(recipe:specs/course_recipe/course-27.t27). - Exactly 9 modules x 3 lessons = 27 lessons; every lesson names one widget and one spec.
- Every lesson spec compiles AND its
testblocks pass in the reader's browser (blocked by the browser-runner issue), or the lesson says plainly that it is a recordedtricast and links the recording. - Every number on a page comes from real tool output named in the widget's
DATA_SOURCES(yosys / nextpnr / board run / spec test). No invented figures. - Board named on every hardware page (Wukong
xc7a200tfgg676vs AX7203xc7a200tfbg484vs Arty A7 / XC7A100T). - Black-and-white share cards and SEO pages generated for all 27 lessons (EN + RU).
- The course PR carries a blog post: EN
body+ RUruBody. - Lessons that need a spec that does not exist yet are listed as sub-tasks (spec first in
gHashTag/t27, then copied here).
Blocked by: #1477 (browser test runner) for every lesson whose spec uses calls, locals or struct fields in tests.
Activity