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Course: The TRI-27 ternary computer -- trits to a CPU on an FPGA (9x3, hardware track) #1486

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Description

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Parent epic: #1476

Course id: ternary-computer
Audience: hardware engineers (RTL / FPGA / ASIC).
Prerequisites: Course 0 (t27 basics); Course 1 module numbers.

Why this course

Planned in the course roadmap (ternary-computer) and the most original material the project owns: 18 ISA specs and 64 ternary specs describe a complete balanced-ternary machine. Building a CPU is the classic capstone of computer-architecture education; building a ternary one is unique.

What already exists in the repo (grounding)

  • isa/ (18): ternary_encoding, ternary_gates, ternary_bitwise, ternary_arithmetic, ternary_shift, registers, ternary_memory, tri27_machine (93 test failures in the browser runner today), tri27_bytecode, ternary_control_flow, data-structure specs
  • ternary/: packed_trit, ternary_xor, ternary_full_adder, ternary_ripple_adder, hybrid_arithmetic, clocked_counter
  • fpga/ternary_isa.t27, fpga/assembler.t27, fpga/linker.t27, fpga/bootrom.t27, fpga/simulator.t27, fpga/ternary_link.t27 + testbenches

Decomposition: 9 modules x 3 lessons

Module 1 -- trits: a digit with three values

# Lesson id What the reader learns Spec Widget idea
1 balanced-ternary -1, 0, +1 and why negation is free isa/ternary_encoding.t27 trit counter
2 encoding-trits-in-bits 2 bits per trit and the wasted state ternary/packed_trit.t27 packing density chart
3 radix-economy radix economy: why 3 is close to e isa/ternary_encoding.t27 cost curve

Module 2 -- gates: ternary logic

# Lesson id What the reader learns Spec Widget idea
4 min-max-not ternary AND/OR/NOT as min/max/negate isa/ternary_gates.t27 truth-table explorer
5 ternary-xor sum mod 3 ternary/ternary_xor.t27 truth table
6 gates-in-luts what a ternary gate costs in LUT6 isa/ternary_gates.t27 LUT count from a yosys run

Module 3 -- arithmetic: adding without a sign bit

# Lesson id What the reader learns Spec Widget idea
7 full-adder the ternary full adder ternary/ternary_full_adder.t27 adder stepper
8 ripple-adder ripple carry over trits ternary/ternary_ripple_adder.t27 carry ripple animation
9 shift-and-multiply shift by a trit = multiply by 3 isa/ternary_shift.t27 shift visual

Module 4 -- state: registers and memory

# Lesson id What the reader learns Spec Widget idea
10 register-file the TRI-27 register file isa/registers.t27 register viewer
11 ternary-memory addressing in trits isa/ternary_memory.t27 memory map
12 clocked-counter the first clocked ternary circuit ternary/clocked_counter.t27 counter waves

Module 5 -- the-isa: an instruction set

# Lesson id What the reader learns Spec Widget idea
13 instruction-formats opcodes and operand fields isa/tri27_machine.t27 instruction decoder
14 the-machine fetch, decode, execute isa/tri27_machine.t27 CPU stepper
15 isa-on-fpga the ISA mapped to hardware fpga/ternary_isa.t27 datapath diagram

Module 6 -- toolchain: from text to code

# Lesson id What the reader learns Spec Widget idea
16 bytecode the bytecode format isa/tri27_bytecode.t27 byte inspector
17 assembler two-pass assembler, labels fpga/assembler.t27 assembler playground
18 linker sections, relocation fpga/linker.t27 link map

Module 7 -- programs: making it do something

# Lesson id What the reader learns Spec Widget idea
19 control-flow branches and loops in trits isa/ternary_control_flow.t27 program trace
20 boot-rom how the machine starts fpga/bootrom.t27 boot sequence
21 simulator the reference simulator fpga/simulator.t27 simulator trace

Module 8 -- algorithms: ternary data structures

# Lesson id What the reader learns Spec Widget idea
22 sorting sorting on a ternary machine isa/ternary_sorting.t27 sort race
23 search-and-hash search and hashing in trits isa/ternary_hash.t27 hash spread
24 trees ternary trees isa/ternary_tree.t27 tree view

Module 9 -- on-the-chip: the computer on real hardware

# Lesson id What the reader learns Spec Widget idea
25 hybrid-arithmetic binary/ternary hybrid datapaths ternary/hybrid_arithmetic.t27 cost comparison
26 ternary-link talking to the host fpga/ternary_link.t27 link trace
27 capstone run a program on TRI-27 on the board isa/tri27_machine.t27 board run receipt

Honesty notes and traps

  • Honest framing: ternary on a binary FPGA is emulated with 2-bit trits; the course must show the cost, not claim an efficiency win the data does not support.
  • tri27_machine.t27 cannot run in the browser yet (93 failures); blocked by the runner issue.

Acceptance criteria

  • specs/course/<id>.t27 + <id>-ru.t27 exist, registered in specs/course/courses.t27, built by course-from-spec.mjs (recipe: specs/course_recipe/course-27.t27).
  • Exactly 9 modules x 3 lessons = 27 lessons; every lesson names one widget and one spec.
  • Every lesson spec compiles AND its test blocks pass in the reader's browser (blocked by the browser-runner issue), or the lesson says plainly that it is a recorded tri cast and links the recording.
  • Every number on a page comes from real tool output named in the widget's DATA_SOURCES (yosys / nextpnr / board run / spec test). No invented figures.
  • Board named on every hardware page (Wukong xc7a200tfgg676 vs AX7203 xc7a200tfbg484 vs Arty A7 / XC7A100T).
  • Black-and-white share cards and SEO pages generated for all 27 lessons (EN + RU).
  • The course PR carries a blog post: EN body + RU ruBody.
  • Lessons that need a spec that does not exist yet are listed as sub-tasks (spec first in gHashTag/t27, then copied here).

Blocked by: #1477 (browser test runner) for every lesson whose spec uses calls, locals or struct fields in tests.

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