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Hold host-orchestration phase state per pipeline slot - #2204
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📝 WalkthroughWalkthroughThe change stores host-phase records and clock-correlation data per pipeline slot. It threads the slot through preparation, collector startup, teardown, callbacks, and artifact writing. Host-orchestrated runs can now use prepared overlap, with stress tests verifying overlap and per-run artifacts. ChangesPer-slot host-phase pipeline
Priority: ➖ Normal Estimated code review effort: 4 (Complex) | ~45 minutes Change: Bug fix · Severity of issue fixed: Medium Sequence Diagram(s)sequenceDiagram
participant Preparation
participant DeviceRunnerBase
participant Collector
participant ArtifactWriter
Preparation->>DeviceRunnerBase: begin_host_phase_run(pipeline_slot, dfx)
Preparation->>DeviceRunnerBase: arm host-phase pool and capture anchors
DeviceRunnerBase->>Collector: publish_host_phase_run_to_collector(pipeline_slot)
DeviceRunnerBase->>Collector: start and finish slot-specific collection
DeviceRunnerBase->>ArtifactWriter: write slot-specific host-phase artifact
Merge Risk: 🟡 Moderate · up to Host-orchestrated overlapping runs can produce incomplete swimlane and clock-correlation artifacts. Correct the collector publication order and session ownership before merging. 🚥 Pre-merge checks | ✅ 4 | ❌ 1❌ Failed checks (1 warning)
✅ Passed checks (4 passed)
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In `@src/a2a3/platform/onboard/host/device_runner.cpp`:
- Line 1078: In the host-phase run flow, move
publish_host_phase_run_to_collector() to execute after finalize_collectors() and
before collector initialization at all three sites:
src/a2a3/platform/onboard/host/device_runner.cpp:1078-1078,
src/a2a3/platform/sim/host/device_runner.cpp:783-783, and
src/a5/platform/sim/host/device_runner.cpp:781-781. Preserve the existing
publication arguments and initialization behavior.
In `@src/a5/platform/onboard/host/device_runner.cpp`:
- Around line 969-971: Move the publish_host_phase_run_to_collector call to
after stale collector finalization completes and immediately before
init_chip_swimlane, so finalize_collectors cannot clear the published
host-orchestration and clock-correlation state before initialization reads it.
In `@src/common/platform/onboard/host/device_runner_base.cpp`:
- Around line 1375-1377: Track the pipeline slot that owns the active
clock-correlation session associated with chip_swimlane_collector_. In the
cleanup path around host_phase_runs_ and clock_correlation, finish the collector
session only when pipeline_slot matches the recorded active-session slot; for a
different slot, release only that slot’s provider without altering the active
session. Update the active-slot state when starting or completing sessions while
preserving the existing provider handling.
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📒 Files selected for processing (19)
src/a2a3/platform/onboard/host/device_runner.cppsrc/a2a3/platform/onboard/host/device_runner.hsrc/a2a3/platform/sim/host/device_runner.cppsrc/a5/platform/onboard/host/device_runner.cppsrc/a5/platform/sim/host/device_runner.cppsrc/common/hierarchical/scheduler.cppsrc/common/platform/include/common/host_api.hsrc/common/platform/include/host/dfx_run_config.hsrc/common/platform/include/host/host_phase_run_state.hsrc/common/platform/onboard/host/c_api_shared.cppsrc/common/platform/onboard/host/device_runner_base.cppsrc/common/platform/onboard/host/device_runner_base.hsrc/common/platform/sim/host/c_api_shared.cppsrc/common/platform/sim/host/device_runner_base.cppsrc/common/platform/sim/host/device_runner_base.hsrc/common/task_interface/call_config.hsrc/common/worker/chip_run_lane.cppsrc/common/worker/chip_worker.cpptests/st/a2a3/host_build_graph/concurrent_prepare_stress/test_concurrent_prepare_stress.py
💤 Files with no reviewable changes (3)
- src/common/task_interface/call_config.h
- src/common/hierarchical/scheduler.cpp
- src/common/platform/include/host/dfx_run_config.h
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The host-phase record store and the clock-correlation provider were one per runner, but their lifetime is one per run: armed during a host-orchestrating bind, read at that run's teardown. A bind is preparation, and a prepared successor prepares while its predecessor is still executing — so the successor's bind reset the store its predecessor had finished and was waiting to publish, and released the provider whose session that predecessor was still running under. Unlike the collector pools, this could not simply move under the execution claim the way hw-native-sys#2163 and hw-native-sys#2200 moved theirs. The records describe the bind, and the `HostOrchestrationBegin` anchor means the instant host orchestration began; deferring either to launch would record something else. hw-native-sys#2201 therefore excluded the affected configurations from pipeline overlap rather than fixing them, which is what this removes. The state is now `std::array<HostPhaseRunState, PTO_PIPELINE_MAX_DEPTH>`, and what reaches the resident swimlane collector is split from what is sampled: - `begin_host_phase_run()` stamps the run's own level and prefix into its slot before its bind, because the runner's members describe whichever run last held the claim - `host_phase_pool_arm()` and `capture_clock_correlation_begin()` write only that slot — no collector writes at all during bind - `publish_host_phase_run_to_collector()` hands the session, the anchors and `set_host_orchestrated` to the collector from the launch arming, under the claim — after the stale-shape `finalize_collectors()`, which resets both, and before the `initialize()` that reads `host_orchestrated_` when it decides whether to size a device orch phase pool The two `HostApiOps` host-phase hooks take a `uint32_t pipeline_slot`, matching the five sibling hooks that already do. No new plumbing was needed to supply it: `HostApi` is already constructed per run and already carries `pipeline_slot_`, and the teardown readers have it on `PreparedExecution`. `HostPhaseRecordStore` deletes copy and move on purpose — `pool_` holds raw pointers into `buffers_` — so the array holds it in place rather than moving it onto `PreparedExecution`. The providers are per slot but the collector's clock-correlation session is not, so the runner records which slot opened it and only that slot may end it. A prepared successor that fails while its predecessor is executing reaches `finish_clock_correlation_session` for its own slot; without the owner check it would end the predecessor's session, costing that run its `DeviceExecutionComplete` anchor and exporting a correlation with no closing edge. With that, the exclusion and everything that supported it goes: the `captures_host_orchestration_phases()` predicate, its four gate sites, the weak `host_phase_records_enabled()` read, and the static_assert pinning the level literal. Any diagnostics configuration now overlaps its predecessor. The scene test's level-4 arm was written for this and flips from requiring `did not overlap` to requiring the overlap. Overlap alone would not have detected a regression, though — collapsing the state back to one store still overlaps, it just loses a run's records — so the arm now also gives each iteration its own output directory and requires every one of them to carry `orchestrator_source: host` in its swimlane artifact. That marker is written only when a run's own host-phase records reached the collector. Verified on a2a3 onboard. The negative control indexes the array at 0 instead of the run's slot: the overlap assertion alone stays green, and the artifact assertion fails with `run 0: its host-orchestration phase records never reached the collector`. The whole a2a3 onboard host_build_graph suite is green in the per-PR CI shape. Also green: 12 DFX channel runs over both sim platforms, full sim sweeps (39 and 35 cases), pyut 2242 passed / 7 skipped, and cpput 140/140 from a cleared build dir.
This was referenced Sep 12, 2026
ChaoWao
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Sep 12, 2026
A run that fails is the run whose swimlane, dumped tensors and dependency
graph someone actually wants to read, and on sim it was the one run that
exported none of them. `drain_execution`'s `runtime_rc != 0` return closed the
clock-correlation session and left immediately, skipping the whole collector
teardown: no swimlane JSON, no dump manifest, no PMU or scope_stats
reconcile, no deps.json. The AICPU threads are joined before that check, so
every collector's producer had already stopped and its records were as
complete as the run had made them — the data was there and simply never
written.
Both sim runners now run the same `teardown_shared_collectors_after_run` the
success path runs, with `device_execution_complete=false`. That argument
withholds exactly one thing, the `DeviceExecutionComplete` clock anchor, which
a failed run never reached. It also subsumes the `finish_clock_correlation_
session` call it replaces, since the teardown opens with it.
Onboard already had that teardown on its error path, for the reason its own
comment gives: emergency shutdown flushes the device's diagnostic buffers
before the timeout rc comes back, so the records survive, and without the
export the dumped tensors reach .bin with no manifest. dep_gen sat outside
that reasoning for no reason — it was inline after the error return, so the
graph of a run that deadlocked was discarded. All four runners now call it
from both paths, extracted as `emit_device_dep_gen_graph` so the two paths
cannot drift.
Emitting it on a failure path is safe because its own reconcile is a
completeness gate: an un-flushed device buffer, a dropped record or a count
mismatch makes `reconcile_counters()` false and nothing is written, so a run
that failed mid-flight yields a whole graph or none, never a partial one. And
its `quiesce()` adds no new exposure on a poisoned card — that error path
already quiesces the four other collectors through the shared teardown.
Two header comments said `cleanup_execution` releases the run's collectors;
both files' own bodies say the opposite ("not per-run: they are released in
finalize()"). The a2a3 one also still justified itself with the
diagnostics-based overlap exclusion that #2204 removed. Corrected to match the
code.
`test_failed_run_exports_its_diagnostics` drives the `scope_deadlock` case
with scope_stats, dep_gen and chip_swimlane on, and requires the artifacts
after the run raises. scope_stats is the witness for the teardown: it writes
whenever its collector initialized, so it has no record-count precondition,
and it is written last in the sequence. deps.json needs its own assertion
because the dep_gen emit follows the teardown and has its own gate. swimlane
is enabled but not asserted — this case fatals in the orchestrator before any
task completes, so the collector is empty and its artifact cannot witness
anything.
Negative control, with the runner change reverted and rebuilt, separates the
two halves: on a2a3sim the output directory is empty and the test fails on the
scope_stats assertion with `holds []`, while on a2a3 onboard it fails on
deps.json with `holds ['scope_stats', 'scope_stats/scope_stats.jsonl']` —
exactly the gap each platform had. Both pass with the change; a5sim passes
too.
The four `emit_device_dep_gen_graph` bodies are near-duplicates, as the four
inline blocks they replace were: `dep_gen_collector_` is a member of each
runner and the two runner bases are unrelated types, so there is nowhere
shared to put it until #2162.
Also green: full sim sweeps (a2a3sim 40 cases, a5sim 36), all 15 sim DFX
channel runs in the `include_dfx_smokes` shape, pyut 2242 passed / 7 skipped,
cpput 140/140 from a cleared build dir, and the a2a3 onboard scene-test suite
in the per-PR CI shape (67 cases). The new test runs in that onboard sweep too.
This was referenced Sep 13, 2026
This was referenced Sep 14, 2026
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Summary
The host-phase record store and the clock-correlation provider were one per runner, but their lifetime is one per run: armed during a host-orchestrating bind, read at that run's teardown. A bind is preparation, and a prepared successor prepares while its predecessor is still executing — so the successor's bind reset the store its predecessor had finished and was waiting to publish, and released the provider whose session that predecessor was still running under.
Closes #2203. Removes the exclusion #2201 put in place instead of fixing it.
Why this could not follow #2163 / #2200
Those moved collector state under the execution claim. This cannot: the records describe the bind, and the
HostOrchestrationBeginanchor means the instant host orchestration began. Deferring either to launch would record something else.So the state is held per slot, and what reaches the resident collector is split from what is sampled:
begin_host_phase_run()host_phase_pool_arm(),capture_clock_correlation_begin()publish_host_phase_run_to_collector()set_host_orchestratedto the collector from the launch arming, ahead of the collectorinitialize()that reads the last of themThe plumbing was already there
The two
HostApiOpshost-phase hooks take auint32_t pipeline_slot, matching the five sibling hooks that already do. Nothing new was needed to supply it:HostApiis already constructed per run and already carriespipeline_slot_, and the teardown readers have it onPreparedExecution.HostPhaseRecordStoredeletes copy and move on purpose —pool_holds raw pointers intobuffers_— so the array holds it in place rather than moving it ontoPreparedExecution.With that, the exclusion and its scaffolding go:
captures_host_orchestration_phases(), its four gate sites, the weakhost_phase_records_enabled()read, and thestatic_assertpinning the level literal. Any diagnostics configuration now overlaps its predecessor.The test needed more than the flip
The scene test's level-4 arm was written for this moment and flips from requiring
did not overlapto requiring the overlap.That alone would not have detected a regression. I checked: collapsing the state back to one store still overlaps — it just loses a run's records, and the overlap assertion is about span timing. So the arm now also gives each iteration its own output directory and requires every one to carry
orchestrator_source: hostin its swimlane artifact. That marker is written only when a run's own host-phase records reached the collector.Testing
Negative control on a2a3 onboard, indexing the array at
0instead of the run's slot:run 0: its host-orchestration phase records never reached the collectorThe whole a2a3 onboard
host_build_graphsuite is green in the per-PR CI shape.Also green: 12 DFX channel runs over both sim platforms; full sim sweeps (39 and 35 cases); pyut 2242 passed / 7 skipped; cpput 140/140 from a cleared build dir.
Related: #2078, #2201, #2203, #2162