Skip to content

Docs: say why sim never stages a prepared successor - #2235

Merged
ChaoWao merged 1 commit into
hw-native-sys:mainfrom
ChaoWao:explain-sim-prepare-opt-out
Sep 15, 2026
Merged

ChaoWao merged 1 commit into
hw-native-sys:mainfrom
ChaoWao:explain-sim-prepare-opt-out

Conversation

@ChaoWao

@ChaoWao ChaoWao commented Sep 15, 2026

Copy link
Copy Markdown
Collaborator

Summary

supports_concurrent_native_prepare_ctx returned a bare 0 on sim with nothing saying why — and it is the switch that makes every overlap-dependent path in the shared runner base dead code on that platform. Two comments, no code.

Why sim opts out — established, not assumed

It is not a policy choice. Sim prepares under the exclusive execution claim:

where the claim is taken
onboard simpler_launch_run (c_api_shared.cpp:930)
sim simpler_prepare_run (c_api_shared.cpp:762)

Sim's simpler_prepare_run calls try_acquire_native_run before it binds and rejects a second run with "another native run is active on this device context". And this base has no try_reserve_native_run for a successor to hold — reservation exists only on the onboard base (device_runner_base.h:122).

So depth-2 pipelining is unreachable here, not switched off. That distinction is the thing a reader needs and could not previously get from the return 0.

A stale justification I introduced in #2204

The per-slot host_phase_runs_ array in the sim base carried the onboard reasoning verbatim:

// One per pipeline slot: a bind is preparation, and a prepared successor
// binds while its predecessor still owns the collectors.

True onboard, false on sim — sim has no prepared successor, which is exactly what the return 0 above reports. I copied it across in #2204 without noticing.

The array is still the right shape: it keeps the storage identical to the onboard base so the shared host-phase code can index by the descriptor's slot with no per-platform branch. The comment now says that.

Testing

Comment-only; no behavior change.

  • a2a3sim and a5sim compile
  • clang-format, cpplint

I deliberately did not run the local scene-test gate: there is no behavior to exercise, the build is the proof, and CI runs the full matrix on any src/ change regardless. Flagging that explicitly rather than implying a gate I skipped.

@coderabbitai

coderabbitai Bot commented Sep 15, 2026 •

Copy link
Copy Markdown

Review Change StackReview Change Stack

No actionable comments were generated in the recent review. 🎉

ℹ️ Recent review info
⚙️ Run configuration

Configuration used: Organization UI

Review profile: CHILL

Plan: Advanced

Run ID: 9da16352-a710-4d26-acf8-b8d7c3f7277d

📥 Commits

Reviewing files that changed from the base of the PR and between a02d96c and a61429e.

📒 Files selected for processing (2)
  • src/common/platform/sim/host/c_api_shared.cpp
  • src/common/platform/sim/host/device_runner_base.h

Included review availability: Your plan provides up to 1 included review per hour; 0 remain after this review.


📝 Walkthrough

Walkthrough

The pull request updates comments in the sim host runner. The comments document exclusive execution, unreachable depth-2 pipelining, dead overlap paths, and the storage shape of host_phase_runs_. No functional or signature changes occur.

Changes

Sim runner clarification

Layer / File(s) Summary
Execution and storage comments
src/common/platform/sim/host/c_api_shared.cpp, src/common/platform/sim/host/device_runner_base.h
The comments explain sim’s exclusive execution claim, the absence of try_reserve_native_run, unreachable depth-2 pipelining, and the single-live-slot storage shape used by shared host-phase code.

Priority: ⬇️ Low

Estimated code review effort: 1 (Trivial) | ~3 minutes

Change: Other

Merge Risk: ⚪ Minimal · up to a6142

This PR clarifies existing sim behavior and storage layout without changing runtime behavior, so it is ready to merge.

🚥 Pre-merge checks | ✅ 4 | ❌ 1

❌ Failed checks (1 warning)

Check name Status Explanation Resolution
Docstring Coverage ⚠️ Warning Docstring coverage is 50.00% which is insufficient. The required threshold is 80.00%. Docstring coverage is scoped to functions touched by this diff. Analyzed 4 functions across 2 files. Write docstrings for the functions missing them to satisfy the coverage threshold.
✅ Passed checks (4 passed)
Check name Status Explanation
Title check ✅ Passed The title clearly and concisely describes the main documentation change: explaining why sim does not stage a prepared successor.
Description check ✅ Passed The description directly explains both comment updates, the sim execution behavior, and the absence of functional changes.
Linked Issues check ✅ Passed Check skipped because no linked issues were found for this pull request.
Out of Scope Changes check ✅ Passed Check skipped because no linked issues were found for this pull request.
  • Fix all pre-merge checks with AI

Thanks for using CodeRabbit! It's free for OSS, and your support helps us grow. If you like it, consider giving us a shout-out.

❤️ Share

A rabbit reads the runner’s note
Exclusive claims keep slots afloat
No staged successor waits in line
Shared paths index storage fine
Seven lines now explain the flow
With no behavior changed below

Comment @coderabbitai help to get the list of available commands.

`supports_concurrent_native_prepare_ctx` returns a bare `0` on sim with nothing
saying why, and it is the switch that makes every overlap-dependent path in the
shared runner base dead code on that platform.

The reason is not a policy choice: `simpler_prepare_run` takes
`try_acquire_native_run` before it binds and rejects a second run with "another
native run is active on this device context", and this base has no
`try_reserve_native_run` for a successor to hold — reservation exists only
onboard. Depth-2 pipelining is unreachable here, not switched off.

The per-slot `host_phase_runs_` array carried the onboard justification, which
does not hold on this side: it said a prepared successor binds while its
predecessor owns the collectors, and sim has no prepared successor. The array
is still the right shape — it keeps the storage identical to the onboard base
so the shared host-phase code can index by the descriptor's slot without a
per-platform branch — so the comment now says that instead.

Comment-only; no behavior change. Both sim platforms compile, clang-format and
cpplint are clean.
@ChaoWao
ChaoWao merged commit 17f6bf5 into hw-native-sys:main Sep 15, 2026
20 checks passed
@ChaoWao
ChaoWao deleted the explain-sim-prepare-opt-out branch September 15, 2026 08:25
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

1 participant