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Fix: preserve device profiling across captures and repeated runs - #2225
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Capturing level-4 clock anchors incorrectly marked device orchestration as host orchestration. The swimlane exporter then rejected the mixed clock domains and omitted the profiling JSON despite successful execution. Preserve the orchestration source in onboard and simulator runners. Use the clock provider name to detect an attempted capture when publishing the correlation session, including unavailable-provider sessions. Add a regression that checks numerical results, AICPU orchestration records, and clock anchors in the exported capture.
📝 WalkthroughWalkthroughThe host runners now start clock correlation when capture records a provider name. Device-orchestrated runs no longer set the host-orchestrated flag. A new scene test validates device orchestration clock-anchor output. ChangesClock correlation capture
Priority: ⬇️ Low Estimated code review effort: 2 (Simple) | ~10 minutes Change: Bug fix Merge Risk: 🔵 Low · up to The new test can pass even if device-orchestrated correlation exports no usable clock anchors, leaving this regression insufficiently protected. Add a non-empty valid-anchor assertion before merge. 🚥 Pre-merge checks | ✅ 4 | ❌ 1❌ Failed checks (1 warning)
✅ Passed checks (4 passed)
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Inline comments:
In
`@tests/st/a2a3/tensormap_and_ringbuffer/dfx/chip_swimlane/test_chip_swimlane.py`:
- Around line 136-143: Strengthen the clock capture assertion in the test around
_clock_capture_path so metadata["clock_anchors"] is a non-empty collection
containing at least one valid anchor, rather than only checking key presence.
Preserve the existing orchestration and non-host source checks.
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📒 Files selected for processing (3)
src/common/platform/onboard/host/device_runner_base.cppsrc/common/platform/sim/host/device_runner_base.cpptests/st/a2a3/tensormap_and_ringbuffer/dfx/chip_swimlane/test_chip_swimlane.py
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Little-oil
changed the title
A disabled run skips profiling initialization, so a reused AICPU module can retain the preceding run's level and phase writers. Orchestration then waits on old profiling queues and triggers scheduler starvation. Invalidate the cached level, phase header, thread index, and phase pool and buffer pointers when each launch publishes its profiling enable bit. This happens before the onboard affinity barrier or sim thread startup, and covers enabled and disabled runs without depending on prior teardown. Extend the clock-capture regression to alternate profiling on and off twice on the same worker, preserving numerical and valid-anchor checks.
Review — merge-base
|
| 桶 | 文件 | +/− | 合计 |
|---|---|---|---|
| Core | 4 | +24 / −18 | 42 |
| Test/Ex | 1 | +38 / −0 | 38 |
| TOTAL | 5 | +62 / −18 | 80 |
规模健康。
机制说明
缺陷 1 的成因链。 collector 有两个独立标志：host_orchestrated_（决定 initialize() 是否给设备侧 orch phase pool 分配 buffer，chip_swimlane_collector.cpp:441）和 host_phase_records_present_（决定导出 orchestrator_source: "host"）。导出前有一道闸：chip_swimlane_collector.cpp:1065，has_aicpu_orch_phases && host_orchestrated_ 就拒绝导出。
时序上，publish_host_phase_run_to_collector() 在 arm_collectors_for_run() 里先跑一次（此时 tmr 路径 host_orchestrated=false，pool 正确分配），随后 start_shared_collectors_for_run() → begin_clock_correlation_session_if_needed() 把它改成 true 并二次 publish。于是：pool 按"设备编排"分配、AICPU 真的写了 orch phase，标志却说"host 编排" → 1065 行的闸触发 → 整个文件不导出。这个 = true 唯一的作用是让当时的早退条件 if (!run.host_orchestrated) return; 放行，属于借标志位当门票。本 PR 把门票换成"这次是否真的尝试过 clock capture"（clock_provider_name 非空 —— capture_clock_correlation_begin() 即使 provider 不可用也会写 "unavailable"），标志位回归本义。
顺带一提：host_phase_run_state.h:58 的注释一直写着 "Only a host-orchestrating bind sets it"，#2204 之后这句话是假的，本 PR 把它变回真的。
缺陷 2 的成因链。 AICPU 的 .so 常驻，静态量跨 launch 存活。旧代码把 s_phase_initialized = false 放在 chip_swimlane_aicpu_init() 里 —— 而这个函数只在启用 profiling 的 launch 上跑。所以 enabled→disabled 序列下：g_chip_swimlane_level 仍是 ORCH_PHASES，aicpu_executor.cpp:681 的 get_chip_swimlane_level() >= ORCH_PHASES 放行 → chip_swimlane_aicpu_set_orch_thread_idx() 被调用 → s_orch_thread_idx >= 0 且 s_phase_initialized 还是上一轮的 true → record_orch_phase 走进上一轮已释放的 s_orch_phase_pools[] → wait_for_free_queue_entry 死等。旧注释声称自己修的正是这个场景，但放错了位置，所以从来没生效。
新位置的并发安全性核对过，成立：onboard 上 set_chip_swimlane_enabled() 在 simpler_aicpu_exec 入口被每个 launch 线程调用（含随后会被 affinity gate 淘汰的超发线程），而 platform_aicpu_affinity_gate_filter() 里有一道真正的屏障（platform_aicpu_affinity.cpp:86-88：release 累加 + 自旋等 total_launched），所有线程的清零都发生在任何线程越过屏障之前，chip_swimlane_aicpu_init() 在屏障之后。屏障状态每次 launch 由最后一个线程复位（:163-169），所以每轮都有效。sim 上该函数在起 sim 线程之前由 host 线程调用，同样安全。多线程写同值/同 nullptr 与该文件既有的 set_platform_chip_swimlane_base 等属同一形态。
目标—手段可追溯性
| 声明目标 | 设计选择 | 代码位置 | 评价 |
|---|---|---|---|
| 设备编排的 clock capture 不再被错标为 host | 删除 host_orchestrated = true，门票改为 clock_provider_name |
onboard/host/device_runner_base.cpp:1464,1486；sim/…:831,850 |
✅ |
| 采集尝试过就发布 correlation（含 provider 不可用的诊断） | 复用 capture_clock_correlation_begin() 的 "unavailable"/"unknown" 落值 |
onboard/…:1452-1453 |
✅ |
| 重复运行时重置 AICPU profiling 状态 | 把失效点搬到每次 launch 都会经过的 set_chip_swimlane_enabled() |
shared/aicpu/chip_swimlane_collector_aicpu.cpp:119-133 |
✅ |
| 回归测试覆盖 4→0→4→0 + 两种 AICPU 线程数 | 新增 TestDeviceOrchestrationClockCapture |
test_chip_swimlane.py:118-150 |
类型化审查：Bugfix ×2
- 触发条件都很窄，既有用例都不做这两件事，CI 之前绿是合理的：(1) 需要
capture_clock_anchors为真，而 L2 默认不开、只有_read_config_from_mailbox的 rank 分支才会置位，所以只有分布式采集撞得到；(2) 需要同一 worker 上 profiling 开→关→开。 - 回归测试：有，且是先失败后通过的形态 —— 修复前迭代 1 会因为文件缺失而 assert 失败，迭代 3 会挂死。符合
discipline.md§3。 - 覆盖面：新用例继承父类
CASES（manual: ["a2a3sim"]），所以 a2a3 onboard 常规 sweep 会跑（2 case × 4 launch），a2a3sim 在_st-sim-a2a3.yml的 chip_swimlane DFX smoke 步骤用--manual include也会跑 —— sim 侧的同款修改因此确实有 CI 覆盖。a5 走同一份src/common代码，未单独加用例，可接受。 - CI：
ad10dae7全绿（19 项）。
pto-isa Pin Check
ℹ️ advisory：pto_isa.pin 当前钉在 03e45c4bda48a6909feb239f0acc45f04176c2a1。本 PR 没有增删或迁移任何 pto-isa 头文件引用，无需 bump。
发现的问题
Must fix
无。两处修复的正确性逐条核到了调用链、时序与屏障，站得住。
Should fix
1. 断言可能被上一轮的产物"喂饱"（test_chip_swimlane.py:133-135,143）
_build_config 只在 config.output_prefix 为空时才造唯一目录。在 DFX smoke lane（--enable-chip-swimlane --enable-dep-gen）里 output_prefix 非空，由 run_class_cases 每次调用 build_output_prefix(case_label) 生成 —— 而它的时间戳是秒级，label 四次迭代完全相同（build_output_prefix 的 docstring 自己写了"同名 case 同一秒内运行不在设计考虑内"，这个用例恰好把它变成常态）。只要迭代 1 和迭代 3 落在同一秒，两者共用一个目录，迭代 3 即使一个字节都没导出，path.is_file() 也会被迭代 1 的文件满足 —— 回归假绿。
父类正是为同一个坑准备了 since=run_marker 判据（见 _swimlane_validate.py 的 docstring）。建议二选一：每次 run 前 path.unlink(missing_ok=True)，或记录 st_mtime 并要求它推进。
2. 断言挂在 compare_outputs 上，--skip-golden 会让整个回归测试静默失效（test_chip_swimlane.py:138）
_run_and_validate_l2 里 compare_outputs 被 if not skip_golden 包着（scene_test.py:2073,2076）。--skip-golden 目前不在任何 workflow 里，所以现在不出事；但父类把它的产物校验放在 test_run 里正是为了避开这个耦合。建议对齐父类：在 test_run 的循环体内、SceneTestCase.test_run(...) 之后做断言。
3. orchestrator_source 那条断言恒为真（test_chip_swimlane.py:146）
原始 chip_swimlane_records.json 里这个 key 只有 host 编排时才会被写出（chip_swimlane_collector.cpp:1111 是唯一写入点，且值恒为 "host"）。AICPU 路径下 key 根本不存在，.get(...) 返回 None，None != "host" 永真 —— 它既不会失败，也无法区分"正确的设备编排"和"metadata 被截断"。建议改成 assert "orchestrator_source" not in records["metadata"]，语义才落到实处。
Consider
4. chip_swimlane_aicpu_init() 现在隐式依赖 set_chip_swimlane_enabled() 先跑过。 这个耦合写在头文件的 doc 里了，但 init 现场没有任何痕迹 —— 而删掉的那段旧注释恰好是唯一提到这个 hazard（以及 #936 同形先例）的地方。在 init 里补一句现在时的事实（例如"phase-writer 状态在 enable 发布点失效，本函数不再重置"）能让下一个读者不必反推。符合 comments.md：陈述当下不变式，而非改动史。
5. 关闭 profiling 的那两次迭代也会 mkdir 一个空的 outputs/… 目录（build_output_prefix 内部 mkdir）。每跑一次留 4 个空目录（onboard 常规 lane）。config.output_prefix 只在 self._swimlane_level 为真时才需要设。
6. set_chip_swimlane_enabled 现在做的事已经超出名字（它是"每次 launch 的 profiling 状态失效点"）。头文件注释已补，不必改名，仅记一笔。
7. 硬件开销：新类在每个 PR 的 a2a3 onboard sweep 上多跑 2 case × 4 launch。考虑到 s_sched_phase_pools[] / s_orch_phase_pools[] 是按线程索引的，覆盖两种 aicpu_thread_num 有实质价值，这笔开销划算 —— 只是提醒这是有意为之，别在后续精简时误删。
8. 子类通过 MRO 复用父类缓存的 type(self)._st_l2_handle（scene_test.py:2015）。这里因为 CALLABLE 完全继承、且 L2 worker 是 session 级共享，所以是对的；但如果将来有人继承 SceneTestCase 又改了 CALLABLE，会静默复用父类的 handle。属框架层面的坑，非本 PR 引入，仅记录。
结论
Approve（建议合入前处理 Should-fix 1–3）。
两处修复都定位准确，改在了正确的层次：缺陷 1 是把被借用作门票的语义标志还原，而不是给闸再加一个例外；缺陷 2 是把失效点从"只有启用时才经过的路径"搬到"每次 launch 都经过的路径"，并且新位置的并发安全性有 affinity 屏障兜底 —— 这两个选择都比更省事的替代方案（比如在 1065 行的闸上加特判、或在 disabled 分支里补一次 init）更耐得住后续修改。
Should-fix 三条全在测试侧，不影响修复本身的正确性，但会削弱这个回归测试未来的把关能力 —— 其中第 1 条尤其值得处理：一个能被上一轮产物喂饱的回归测试，回归时的表现是绿色，正是最难被发现的那种失效。
Remove a previous profiling JSON before each enabled run so repeated case directories cannot hide a missing export. Check all case artifacts after each profiling iteration, independently of golden comparison. Require device captures to omit orchestrator_source, matching the raw JSON schema and rejecting unexpected values such as null.
|
@ChaoWao 已在 c326f370 中处理了这条 review 的 Should-fix 1–3：
验证了三组故障注入：导出缺失但保留旧 JSON、 正常测试在 A2/A3 模拟器和硬件上均通过：默认模式、 |
…2746) Updates the bundled runtime from `39ce891d` to `097735888e6dd2a5dd71b3e82312af99bad95576` and adapts Graph scalar forwarding and N-D transpose scratch allocation to the updated runtime and PTO-ISA. Graph boundary scalars retain the runtime's `InheritableScalar` wrapper when forwarded to tasks, so replay uses the current invocation's scalar values. The compilation test checks generated orchestration against the pinned runtime headers. English and Chinese documentation explain that implicit integer conversion is rejected and explicit `to<T>()` extraction loses the parameter origin. `LowerNdTranspose` reserves each scratch page using the ISA's padded row stride and staging requirements, then advances page offsets by that full capacity. Logical scratch views retain the source shape required by `pto.ttrans`. For the failing FP32 `[4, 24, 8]` transpose, each page grows from 768 to 1024 bytes, preventing the fourth page from overwriting the output buffer. Eight regression cases cover FP32, FP16 (including two full-height staging strips), and INT8, and the pass documentation is updated in both languages. Named constants describe the ISA requirements. Positive dimensions and supported element widths are checked; ceiling division avoids numerator overflow, and checked multiplication validates page capacity, pool dimensions, and total pool bytes before batch expansion. Nine additional regression cases cover invalid dimensions, unsupported widths, and arithmetic overflow. Repeated comments are shortened. The runtime update includes hw-native-sys/simpler#2225: clock capture preserves the actual orchestration source, restoring device profiling JSON output, and per-launch profiling state cleanup prevents stale state across enabled/disabled runs. Its regression coverage checks fresh artifacts on repeated runs, including when golden comparison is disabled. Validation: - Reproduced the original A2/A3 `test_nd3d_transpose` failure locally: 24/768 incorrect output elements. The same onboard test passes after the scratch fix. - Latest revision: local PyPTO build and 197 focused flattening, Graph codegen, and Graph boundary tests passed, including all nine new bounds checks. The original scratch regression cases detect six failures with the old lowering. - Full local unit suite after the scratch fix, before the bounds follow-up: 12,832 passed, 10 skipped, 1 xfailed. Torch backend autoload and the editable import hook were disabled for this run to avoid local subprocess/import interference. - Local PyPTO build and A2/A3 onboard, A2/A3 simulator, and A5 simulator runtime builds passed. - Local per-rank DFX/swimlane tests on A2/A3 simulator: 2 passed, 1 skipped (four ranks require four devices). - Changed-file clang-tidy and pre-commit checks passed. CI validation of the final revision is pending. --------- Co-authored-by: Youhezhen <youhezhen@huawei.com>
3 participants
Summary
Level-4 device orchestration with clock-anchor capture incorrectly marked its records as host-produced. The swimlane exporter then refused mixed clock domains and omitted
chip_swimlane_records.json, causing the distributed profiling failure in hw-native-sys/pypto#2746. Preserve the actual orchestration source in onboard and simulator runners, and publish clock correlation whenever capture has been attempted, including unavailable-provider diagnostics. This fixes the regression introduced by 0cc51ad (#2204).Reusing a worker for a subsequent run with profiling disabled also retained the prior AICPU profiling level and phase writers. The orchestrator could block waiting on old profiling queues and report
S5:orchestrator-starvation. Reset the cached level, phase header, thread index, and phase pool/buffer pointers at each launch's enable-state publication, before the onboard affinity barrier or simulator thread startup. Existing profiling buffers remain reusable.The regression alternates profiling levels
4 → 0 → 4 → 0on one worker, covers both AICPU-count configurations, and checks numerical results, AICPU orchestration records, and non-empty valid clock anchors. Before each enabled run it removes any previous profiling JSON at that path. Capture assertions run for every case after each iteration, independently of golden comparison, and require raw device metadata to omitorchestrator_source.Validation
Reproduced the original missing-JSON failure on two A2/A3 devices; the fix passed the PyPTO per-rank DFX tests (2 passed, 1 skipped; the skipped case requires four devices).
The profiling-transition regression reproduced the same
S5timeout before the cleanup fix. A local debugger showed profiling disabled while the cached level remainedORCH_PHASES, with the orchestrator blocked inwait_for_free_queue_entry.The transition regression passes after the fix, including with CLI profiling and dependency generation enabled.
A2/A3 and A5 simulator profiling checks cover both runtime flavors.
A2/A3 simulator sweep: 40 resource jobs passed; L2
host_build_graph: 12 passed, 7 skipped; L2tensormap_and_ringbuffer: 30 passed, 1 skipped.Applicable pre-commit checks passed with CI's
clang-tidy-18.A2/A3 hardware L2 suites, with a separate process per runtime and xdist loadfile scheduling: 41 passed, 1 skipped for
host_build_graph; 60 passed fortensormap_and_ringbuffer. This includes the repeated profiling transition and both previously failing BGEMM and paged-attention ring-buffer cases.CI on
c326f370passed in full, including A2/A3 and A5 hardware scene tests and DFX smokes, Linux and macOS simulator suites, the profiling flag matrix, unit tests, packaging, DeepSeek, and network hardware tests.Capture-validation fault injection: retaining an old JSON when export is suppressed, suppressing export with
--skip-golden, and addingorchestrator_source: nullall escaped the previous test and are rejected by the strengthened assertions. The probes target the first case, confirming that validation covers both case configurations.Updated scene-test file on A2/A3 simulator and hardware: 2 passed per platform in default mode and 2 passed per platform with
--enable-chip-swimlane 4 --enable-dep-gen --skip-golden. Applicable pre-commit checks passed.A local exploratory invocation mixing runtime flavors in one pytest process failed and later segfaulted. Its cause is unverified and recorded in the local
KNOWN_ISSUES.md; the separate-process invocation above completed without those failures.