qwen4exp: add hc ops

[am17an]

Overview

Qwen4Exp uses hyperconnection ops like DSV4 but in 2 slightly different ways:

1. a per element gate in hc_pre
2. a NULL comb in hc_comb

This PR adds both of them without changing ggml ops. On a DGX spark

CPU	Model	Test	t/s qwen4exp-hc-normfix	t/s qwen4exp-hc-fuse-wip	Speedup
CPU	qwen4exp A3B IQ1_S - 1.5625 bpw	pp2048	964.36	1096.91	1.14
CPU	qwen4exp A3B IQ1_S - 1.5625 bpw	tg32	37.17	37.85	1.02

Additional information

Requirements

• I have read and agree with the contributing guidelines
• AI usage disclosure: YES

[pwilkin]

/bot review

[ggml-gh-bot]

Automated code review

Review: qwen4exp: add hc ops (gated hc_pre, identity-comb hc_post)

Scope: extends the existing GGML_OP_DSV4_HC_PRE / GGML_OP_DSV4_HC_POST semantics (per-element sigmoid gate + scale in PRE, comb == NULL identity in POST), CPU + CUDA implementations, correct rejection in Metal/SYCL/Vulkan, and a qwen4exp graph fast path plus test-backend-ops cases. No new ops, no public API signature changes.

Blocking

None found. I verified the math: the fused gated PRE (scale * sum_h x[i,h,t]*sigmoid(gate[i,h,t]), scale = 1/hc) and the identity POST (x[i,t]*post[dst,t] + residual[i,dst,t]) are element-for-element equivalent to the reference paths they replace in src/models/qwen4exp.cpp (same reshape layout [n_embd, hc, nt] from [hc*n_embd, nt], so the stream pairing matches the old elementwise mul). Op-param layout (f32 at 0, i32 at 1) does not overlap, op params are always set by the single _impl constructor, and RPC serializes op_params with the tensor, so remote CPU execution is correct. Backend gating is consistent: CUDA implements both variants and claims them; SYCL/Vulkan/Metal reject the variants their kernels cannot run (and the previous NULL-src[3] deref in supports_op for Metal/SYCL would have crashed on the identity POST - the added null guards fix that). The per-model resolve_fused_ops probe means the shared cparams.fused_dsv4_hc_pre/post flags are resolved against the current model's graph, so unsupported backends fall back to the reference path automatically.

Will slow the review

(point 1) Latent scale trap on SYCL/Vulkan/Metal PRE. Their kernels do not apply the new scale op param, and their supports_op checks reject only the gated variant (ggml_get_op_params_i32(op, 1) != 0). Today this is safe only because ggml_dsv4_hc_pre() hardcodes scale = 1.0f; nothing enforces the invariant "non-gated implies scale == 1". A future non-gated caller passing scale != 1 would silently compute wrong results on those three backends. Cheapest fix: also reject in supports_op when ggml_get_op_params_f32(op, 0) != 1.0f, or apply the scale in those kernels.

(point 2) docs/ops.md / docs/ops/*.csv have no entries for the DSV4_HC ops at all (pre-existing from the PR that introduced them), so the extended semantics are also undocumented. Not this PR's obligation, but worth a follow-up since the ops now have two distinct shapes/modes.

Nits

(point 3) tests/test-backend-ops.cpp: the identity POST is only exercised at (31,17) and (4096,21); the comb variant also has the (1,1) degenerate-size case. Consider adding test_dsv4_hc_post(1, 1, true) for symmetry.

(point 4) ggml/include/ggml.h around the new declaration: the trailing lone // line after the result[i, t] = ... comment - the adjacent hc_post block uses the same pattern, so it blends in, just noting it.

Otherwise the diff is clean: no unicode, concise comments, existing style followed (_impl wrapper pattern, GGML_TENSOR_LOCALS, template kernels selected via function pointer with the existing ggml_cuda_kernel_launch helper), and test cases for both new variants are included per the two-backend convention.

This review was generated automatically by pi coding agent using zai-org/GLM-5.3. It may contain mistakes. Maintainers make the final call.

[pwilkin]

Before:

model	size	params	backend	ngl	test	t/s
qwen4exp A3B Q4_K - Medium	103.68 GiB	176.94 B	ROCm,Vulkan	-1	pp512	334.85 ± 43.96
qwen4exp A3B Q4_K - Medium	103.68 GiB	176.94 B	ROCm,Vulkan	-1	tg128	20.96 ± 0.61
qwen4exp A3B Q4_K - Medium	103.68 GiB	176.94 B	ROCm,Vulkan	-1	pp512 @ d30000	232.26 ± 10.62
qwen4exp A3B Q4_K - Medium	103.68 GiB	176.94 B	ROCm,Vulkan	-1	tg128 @ d30000	16.85 ± 0.92

After:

model	size	params	backend	ngl	test	t/s
qwen4exp A3B Q4_K - Medium	103.68 GiB	176.94 B	ROCm,Vulkan	-1	pp512	360.32 ± 23.06
qwen4exp A3B Q4_K - Medium	103.68 GiB	176.94 B	ROCm,Vulkan	-1	tg128	22.11 ± 0.06
qwen4exp A3B Q4_K - Medium	103.68 GiB	176.94 B	ROCm,Vulkan	-1	pp512 @ d30000	228.14 ± 24.20
qwen4exp A3B Q4_K - Medium	103.68 GiB	176.94 B	ROCm,Vulkan	-1	tg128 @ d30000	16.81 ± 1.17

Tested mixed mmproj+text input, everything looks fine.