t27b ledger steward: the rules and the job card, so spec PRs stop editing the ledger (Closes #8654) by gHashTag · Pull Request #8656 · gHashTag/t27

gHashTag · 2026-10-10T14:45:53Z

Why

Spec PRs land without a row in docs/reports/t27b_expectations.json. Master's t27b-native-ratchet then goes red (UNLISTED) on every PR, and parallel lanes conflict on the file. It was fixed by hand three times in two days: see #8289, #8548 and #8646. This is item 1 of the efficiency plan (see #8637) and option 3 of #8321.

The rules: `specs/tri/t27b/ledger_steward.t27`

The rules use steward.t27's codes and functions: is_pass, bless_reason, cap_rise_is_new, and entry_code in an invariant.

finding on a master run	steward
UNLISTED, t27b pass / pass_vacuous	add the row as the run states it
UNLISTED, blocked / frontend / codegen	add it, reason `unimplemented`
UNEXPECTED PASS	set the row to the run's pass
STALE	drop the row
VACUITY MEASURED, UNJUDGED	keep the row (information)
cap rise <= new non-pass rows	`max_not_pass` = the recounted non-pass
UNEXPECTED FAILURE, MOVED, BAD REASON, OVER CAP	refuse
UNLISTED where t27b fails / mismatches / crashes / times out	refuse (a defect is never `unimplemented`)
a cap rise larger than the new rows, or more than 16 STALE rows	refuse

One refused finding refuses the whole run: the run gets one issue and no PR. A run that is not a master run, did not count asserts, or was compared against a ledger master no longer has is skipped.

The tests use the hand batches as vectors:

t27b ledger: rows for 9 specs merged without one (Closes #8287) #8289 (7 pass + 2 blocked, cap 18 -> 20) is applied;
t27b ledger: rows for 9 more specs that landed without one (Closes #8645) #8646 (8 pass + 1 codegen, cap 25 -> 26) is applied;
t27b ledger: master's native run at c9d36f314, row by row (Closes #8322) #8548 is refused for its 2 UNEXPECTED FAILUREs, and its cap rise to 27 does not fit either. Without the failures, its 56 row changes are applied with cap 23 -> 25.

The job card: `specs/jobs/t27b_ledger_steward.t27`

The card has the shape of release_t27c.t27 and follows jobs.t27:

0 CHECK steward-run
1 EFFECT steward-refusals-issue
2 CHECK steward-appliable
3 EFFECT steward-ledger-issue
4 EFFECT steward-compose
5 EFFECT steward-pull-request
6 EFFECT steward-auto-merge
7 WAIT steward-merged

The trigger is a master run of t27b-lab (latest.json) whose ratchet is red. Master's native ratchet is the second trigger once t27b-native.yml uploads its run.json and ratchet.json. Every effect goes through the effects journal, keyed by the run's commit.

Runtime

The Queen's job runner (gHashTag/trios queen-jobs.ts, branch queen-runners) runs only the release card. Its loader, trigger, executors, journal kinds (issue, auto-merge) and credential are missing; the details are in gHashTag/trios#1751. Until it runs, spec PRs keep adding their own rows. The t27b-loop skill says so.

Measured on the t27c lab

t27c test-report: 10 of 10 tests, 0 vacuous (ledger_steward); 2 of 2, 0 vacuous (card).
t27b corpus --blockers --reference <t27c> --json, under qemu-aarch64: both specs pass on both sides, with 108 and 26 runtime asserts and 0 reference disagreements. All 117 files under specs/tri/t27b still pass the reference.
Both specs are sealed with t27c seal --save, and each has its ledger row (pass). max_not_pass is unchanged.

Only .t27, .json and .md files change.

🤖 Generated with Claude Code

…ting the ledger (Closes #8654) specs/tri/t27b/ledger_steward.t27 decides which ratchet findings on a master run the steward applies (UNLISTED, UNEXPECTED PASS, STALE, a cap rise covered by new rows) and which it refuses and reports in one issue per run (UNEXPECTED FAILURE, MOVED, BAD REASON, OVER CAP, a defect, a larger cap rise, a STALE flood). The hand batches #8289, #8548 and #8646 are its test vectors. specs/jobs/t27b_ledger_steward.t27 is the jobs.t27 card: CHECK the run, EFFECT the refusal issue, CHECK appliable, EFFECT ledger issue, compose, PR, auto-merge, WAIT merged. The Queen runtime gaps are in gHashTag/trios#1751. Both specs pass t27c test-report and t27b corpus --reference on the t27c lab with runtime asserts; seals and ledger rows included. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

github-actions · 2026-10-10T14:46:14Z

PR Dashboard

Generated at: 2026-10-10 14:46:06 UTC

t27b ledger steward: the rules and the job card, so spec PRs stop editing the ledger (Closes #8654) #8656 t27b ledger steward: the rules and the job card, so spec PRs stop editing the ledger (Closes #8654) | Created: 2026-10-10 | Updated: 2026-10-10 | 29 failing / 30 total
t27b: an empty typed array literal is an empty list; drop the stale reference-defect refusal (Closes #8633) #8647 t27b: an empty typed array literal is an empty list; drop the stale reference-defect refusal (Closes #8633) | Created: 2026-10-10 | Updated: 2026-10-10 | 5 failing / 39 total
Port gHashTag/trinity:src/tri/railway.zig (Zig, 4 functions) to specs/port/trinity/src/tri/railway.t27 #8555 Port gHashTag/trinity:src/tri/railway.zig (Zig, 4 functions) to specs/port/trinity/src/tri/railway.t27 | Created: 2026-10-10 | Updated: 2026-10-10 | 6 failing / 29 total
docs(fpga): HARDWARE_SSOT records the TRI-NET node answering jobs over UDP #8538 docs(fpga): HARDWARE_SSOT records the TRI-NET node answering jobs over UDP | Created: 2026-10-10 | Updated: 2026-10-10 | 2 failing / 24 total
fix(fpga): eth_reply.t27 sends one frame per receipt, to the sender, with a real checksum #8532 fix(fpga): eth_reply.t27 sends one frame per receipt, to the sender, with a real checksum | Created: 2026-10-10 | Updated: 2026-10-10 | 5 failing / 39 total
gf16.t27 (L6 ceiling): gf16_extract_exponent returns 0 for every input; 3 invariants false under execution #8531 gf16.t27 (L6 ceiling): gf16_extract_exponent returns 0 for every input; 3 invariants false under execution | Created: 2026-10-10 | Updated: 2026-10-10 | 8 failing / 30 total
Wave 683: one mistake in two copies, and a withdrawn explanation #8509 Wave 683: one mistake in two copies, and a withdrawn explanation | Created: 2026-10-10 | Updated: 2026-10-10 | 3 failing / 24 total
Port gHashTag/trinity:fpga/openxc7-synth/uart_bridge_fixed.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synt #8506 Port gHashTag/trinity:fpga/openxc7-synth/uart_bridge_fixed.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synt | Created: 2026-10-10 | Updated: 2026-10-10 | 6 failing / 29 total
Port gHashTag/trinity:src/tri_lang/content_registry.zig (Zig, 7 functions) to specs/port/trinity/src/tri_lang/content_re #8483 Port gHashTag/trinity:src/tri_lang/content_registry.zig (Zig, 7 functions) to specs/port/trinity/src/tri_lang/content_re | Created: 2026-10-10 | Updated: 2026-10-10 | 4 failing / 29 total
Port gHashTag/trinity:src/tri/gen_splay_tree.zig (Zig, 5 functions) to specs/port/trinity/src/tri/gen_splay_tree.t27 #8470 Port gHashTag/trinity:src/tri/gen_splay_tree.zig (Zig, 5 functions) to specs/port/trinity/src/tri/gen_splay_tree.t27 | Created: 2026-10-10 | Updated: 2026-10-10 | 4 failing / 29 total
Port gHashTag/trios:crates/trios-ipc/src/validate.rs (Rust, 3 functions) to specs/port/trios/crates/trios-ipc/src/valida #8459 Port gHashTag/trios:crates/trios-ipc/src/validate.rs (Rust, 3 functions) to specs/port/trios/crates/trios-ipc/src/valida | Created: 2026-10-10 | Updated: 2026-10-10 | 4 failing / 29 total
Port scripts/gen_w680.py (Python, 3 functions) to specs/port/scripts/gen_w680.t27 #8458 Port scripts/gen_w680.py (Python, 3 functions) to specs/port/scripts/gen_w680.t27 | Created: 2026-10-10 | Updated: 2026-10-10 | 5 failing / 29 total
Port gHashTag/trinity:src/tri/tri_hardware_deploy.zig (Zig, 5 functions) to specs/port/trinity/src/tri/tri_hardware_depl #8457 Port gHashTag/trinity:src/tri/tri_hardware_deploy.zig (Zig, 5 functions) to specs/port/trinity/src/tri/tri_hardware_depl | Created: 2026-10-10 | Updated: 2026-10-10 | 4 failing / 29 total
Port gHashTag/trios:crates/trios-mcp/rings/SR-00/src/screenshot.rs (Rust, 5 functions) to specs/port/trios/crates/trios- #8456 Port gHashTag/trios:crates/trios-mcp/rings/SR-00/src/screenshot.rs (Rust, 5 functions) to specs/port/trios/crates/trios- | Created: 2026-10-10 | Updated: 2026-10-10 | 4 failing / 29 total
Port gHashTag/trios:crates/trios-chat/rings/CR-CHAT-04/src/padding_class_downgrade_guard.rs (Rust, 2 functions) to specs #8455 Port gHashTag/trios:crates/trios-chat/rings/CR-CHAT-04/src/padding_class_downgrade_guard.rs (Rust, 2 functions) to specs | Created: 2026-10-10 | Updated: 2026-10-10 | 8 failing / 29 total
Port gHashTag/trinity:fpga/openxc7-synth/ternary_matvec.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/t #8453 Port gHashTag/trinity:fpga/openxc7-synth/ternary_matvec.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/t | Created: 2026-10-10 | Updated: 2026-10-10 | 4 failing / 29 total
spec automation/ci-bridge v3: the verdict as the app's own PR comment #8452 spec automation/ci-bridge v3: the verdict as the app's own PR comment | Created: 2026-10-10 | Updated: 2026-10-10 | 4 failing / 37 total
Port gHashTag/trinity:fpga/openxc7-synth/quantum_bridge.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/q #8451 Port gHashTag/trinity:fpga/openxc7-synth/quantum_bridge.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/q | Created: 2026-10-10 | Updated: 2026-10-10 | 5 failing / 29 total
Port gHashTag/trios:crates/trios-phd/src/bin/migrate_rag.rs (Rust, 1 function) to specs/port/trios/crates/trios-phd/src/ #8450 Port gHashTag/trios:crates/trios-phd/src/bin/migrate_rag.rs (Rust, 1 function) to specs/port/trios/crates/trios-phd/src/ | Created: 2026-10-10 | Updated: 2026-10-10 | 4 failing / 29 total
Port gHashTag/trios:crates/trios-hdc/src/lib.rs (Rust, 2 functions) to specs/port/trios/crates/trios-hdc/src/lib.t27 #8449 Port gHashTag/trios:crates/trios-hdc/src/lib.rs (Rust, 2 functions) to specs/port/trios/crates/trios-hdc/src/lib.t27 | Created: 2026-10-10 | Updated: 2026-10-10 | 4 failing / 29 total
Port scripts/gen_w660.py (Python, 3 functions) to specs/port/scripts/gen_w660.t27 #8448 Port scripts/gen_w660.py (Python, 3 functions) to specs/port/scripts/gen_w660.t27 | Created: 2026-10-10 | Updated: 2026-10-10 | 5 failing / 29 total
Port gHashTag/trinity:src/phi-engine/vibeec_original/bogatyrs_yaml_syntax.zig (Zig, 1 function) to specs/port/trinity/sr #8447 Port gHashTag/trinity:src/phi-engine/vibeec_original/bogatyrs_yaml_syntax.zig (Zig, 1 function) to specs/port/trinity/sr | Created: 2026-10-10 | Updated: 2026-10-10 | 4 failing / 29 total
Port scripts/gen_w670.py (Python, 3 functions) to specs/port/scripts/gen_w670.t27 #8444 Port scripts/gen_w670.py (Python, 3 functions) to specs/port/scripts/gen_w670.t27 | Created: 2026-10-10 | Updated: 2026-10-10 | 5 failing / 29 total
Port bootstrap/src/compiler.rs lines 28604-28703 (Rust, 10 functions) to specs/port/bootstrap/src/compiler/HirMemory_new #8443 Port bootstrap/src/compiler.rs lines 28604-28703 (Rust, 10 functions) to specs/port/bootstrap/src/compiler/HirMemory_new | Created: 2026-10-10 | Updated: 2026-10-10 | 5 failing / 29 total
Port scripts/gen_w672.py (Python, 3 functions) to specs/port/scripts/gen_w672.t27 #8442 Port scripts/gen_w672.py (Python, 3 functions) to specs/port/scripts/gen_w672.t27 | Created: 2026-10-10 | Updated: 2026-10-10 | 5 failing / 29 total
spec(automation): blog-share v6 -- autopost: new articles at once, the backlog on a schedule, Telegram a network (Closes #8318) #8319 spec(automation): blog-share v6 -- autopost: new articles at once, the backlog on a schedule, Telegram a network (Closes #8318) | Created: 2026-10-09 | Updated: 2026-10-09 | 5 failing / 31 total
course-outreach v3: daily and weekly send cap per network #8308 course-outreach v3: daily and weekly send cap per network | Created: 2026-10-09 | Updated: 2026-10-09 | 1 failing / 29 total
t27b: ledger rows carry the host-free verdict key; bless rewrites only rows that moved (Closes #8186) #8218 t27b: ledger rows carry the host-free verdict key; bless rewrites only rows that moved (Closes #8186) | Created: 2026-10-09 | Updated: 2026-10-10 | 4 failing / 39 total
policy: list the t27b bless test as an own-language exception (Closes #8214) #8216 policy: list the t27b bless test as an own-language exception (Closes #8214) | Created: 2026-10-09 | Updated: 2026-10-09 | 2 failing / 24 total
tri-mcp: tri_test runs the spec's tests through report.t27 (Closes #8140) #8149 tri-mcp: tri_test runs the spec's tests through report.t27 (Closes #8140) | Created: 2026-10-09 | Updated: 2026-10-09 | 5 failing / 62 total
Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/api/services/mcp/mcp-server.ts (TypeScript, 1 function) to sp #8108 Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/api/services/mcp/mcp-server.ts (TypeScript, 1 function) to sp | Created: 2026-10-09 | Updated: 2026-10-09 | 3 failing / 29 total
specs/functions: broadcast-message-send -- one step per batch of 25 #8021 specs/functions: broadcast-message-send -- one step per batch of 25 | Created: 2026-10-09 | Updated: 2026-10-09 | 1 failing / 29 total
Port scripts/tri_loop/gate_sweep.py (Python, 1 function) to specs/port/scripts/tri_loop/gate_sweep.t27 #7993 Port scripts/tri_loop/gate_sweep.py (Python, 1 function) to specs/port/scripts/tri_loop/gate_sweep.t27 | Created: 2026-10-09 | Updated: 2026-10-09 | 2 failing / 29 total
Port gHashTag/trios:crates/trios-igla-race/src/status.rs (Rust, 2 functions) to specs/port/trios/crates/trios-igla-race/ #7986 Port gHashTag/trios:crates/trios-igla-race/src/status.rs (Rust, 2 functions) to specs/port/trios/crates/trios-igla-race/ | Created: 2026-10-09 | Updated: 2026-10-09 | 2 failing / 29 total
Port gHashTag/trios:crates/trios-chat/rings/CR-CHAT-05/src/store_compaction_integrity_guard.rs (Rust, 1 function) to spe #7920 Port gHashTag/trios:crates/trios-chat/rings/CR-CHAT-05/src/store_compaction_integrity_guard.rs (Rust, 1 function) to spe | Created: 2026-10-08 | Updated: 2026-10-09 | 2 failing / 29 total
gen-ts: lower the bodies of pure functions #7872 gen-ts: lower the bodies of pure functions | Created: 2026-10-08 | Updated: 2026-10-08 | 4 failing / 42 total
Port bootstrap/src/compiler.rs lines 23970-24090 (Rust, 8 functions) to specs/port/bootstrap/src/compiler/return_unsized #7797 Port bootstrap/src/compiler.rs lines 23970-24090 (Rust, 8 functions) to specs/port/bootstrap/src/compiler/return_unsized | Created: 2026-10-08 | Updated: 2026-10-08 | 1 failing / 29 total
Port gHashTag/trios:crates/trios-cli/src/cmd/issue.rs (Rust, 2 functions) to specs/port/trios/crates/trios-cli/src/cmd/i #7795 Port gHashTag/trios:crates/trios-cli/src/cmd/issue.rs (Rust, 2 functions) to specs/port/trios/crates/trios-cli/src/cmd/i | Created: 2026-10-08 | Updated: 2026-10-08 | 2 failing / 29 total
Port gHashTag/trinity:fpga/gf16-pipelined/gf16_dot4_p.v (Verilog, 1 module) to specs/port/trinity/fpga/gf16-pipelined/gf #7734 Port gHashTag/trinity:fpga/gf16-pipelined/gf16_dot4_p.v (Verilog, 1 module) to specs/port/trinity/fpga/gf16-pipelined/gf | Created: 2026-10-08 | Updated: 2026-10-08 | 1 failing / 29 total
fpga: systolic wavefront array spec -- matrix multiply as a schedule (for the ai-accelerator course) (Closes #10536) #7719 fpga: systolic wavefront array spec -- matrix multiply as a schedule (for the ai-accelerator course) | Created: 2026-10-08 | Updated: 2026-10-08 | 5 failing / 37 total
Port scripts/gen_w328.py (Python, 1 function) to specs/port/scripts/gen_w328.t27 #7709 Port scripts/gen_w328.py (Python, 1 function) to specs/port/scripts/gen_w328.t27 | Created: 2026-10-08 | Updated: 2026-10-08 | 3 failing / 29 total
Port fpga/verilog/gft_sadd_jtag.v (Verilog, 1 module) to specs/port/fpga/verilog/gft_sadd_jtag.t27 #7708 Port fpga/verilog/gft_sadd_jtag.v (Verilog, 1 module) to specs/port/fpga/verilog/gft_sadd_jtag.t27 | Created: 2026-10-08 | Updated: 2026-10-08 | 2 failing / 29 total
Port gHashTag/trinity:fpga/openxc7-synth/quantum_bridge_zero.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-sy #7707 Port gHashTag/trinity:fpga/openxc7-synth/quantum_bridge_zero.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-sy | Created: 2026-10-08 | Updated: 2026-10-08 | 3 failing / 29 total
Port gHashTag/trinity:src/tri/author_attribution_guard.zig (Zig, 2 functions) to specs/port/trinity/src/tri/author_attri #7689 Port gHashTag/trinity:src/tri/author_attribution_guard.zig (Zig, 2 functions) to specs/port/trinity/src/tri/author_attri | Created: 2026-10-08 | Updated: 2026-10-08 | 2 failing / 29 total
Port gHashTag/trinity:src/vibeec/bogatyrs_spec_structure.zig (Zig, 1 function) to specs/port/trinity/src/vibeec/bogatyrs #7644 Port gHashTag/trinity:src/vibeec/bogatyrs_spec_structure.zig (Zig, 1 function) to specs/port/trinity/src/vibeec/bogatyrs | Created: 2026-10-08 | Updated: 2026-10-08 | 3 failing / 29 total
Port gHashTag/trios:crates/trios-mcp/rings/SR-01/src/audits_new.rs (Rust, 4 functions) to specs/port/trios/crates/trios- #7643 Port gHashTag/trios:crates/trios-mcp/rings/SR-01/src/audits_new.rs (Rust, 4 functions) to specs/port/trios/crates/trios- | Created: 2026-10-08 | Updated: 2026-10-08 | 3 failing / 29 total
Port gHashTag/trinity:src/phi-engine/vibeec_original/bogatyrs_spec_structure.zig (Zig, 1 function) to specs/port/trinity #7624 Port gHashTag/trinity:src/phi-engine/vibeec_original/bogatyrs_spec_structure.zig (Zig, 1 function) to specs/port/trinity | Created: 2026-10-07 | Updated: 2026-10-07 | 2 failing / 31 total
Port gHashTag/trios:crates/trios-chat/rings/CR-CHAT-05/src/envelope_size_distribution_uniformity.rs (Rust, 1 function) t #7623 Port gHashTag/trios:crates/trios-chat/rings/CR-CHAT-05/src/envelope_size_distribution_uniformity.rs (Rust, 1 function) t | Created: 2026-10-07 | Updated: 2026-10-07 | 2 failing / 31 total
Implement the 1 empty function body in specs/test_framework/graph_drift_detection.t27 #7613 Implement the 1 empty function body in specs/test_framework/graph_drift_detection.t27 | Created: 2026-10-07 | Updated: 2026-10-07 | 4 failing / 29 total
Port fpga/verilog/gft_dup_jtag.v (Verilog, 1 module) to specs/port/fpga/verilog/gft_dup_jtag.t27 #7612 Port fpga/verilog/gft_dup_jtag.v (Verilog, 1 module) to specs/port/fpga/verilog/gft_dup_jtag.t27 | Created: 2026-10-07 | Updated: 2026-10-07 | 3 failing / 29 total

Summary

Status	Count
Total Open PRs	50
PRs with Failing Checks	49
PRs with All Checks Green	1
READY	0
FAILING	49
PENDING	0
NO CHECKS YET	0

These columns do not partition: 0 + 49 + 0 + 0 = 49, and there are 50 open PRs. A PR is being counted twice or not at all.

Seal Status

⚠️ STALE -- sha256(compiler.rs)=998387bced4a != manifest seal=87e5cbd3ad94.
The committed NMSE numbers were certified against an older compiler.rs.
Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

…10364) Closes #10363 Merged by the rules (required checks green; every other red inherited): - Corpus ratchet (expected-failure ledger): ['+ Ring NEW conflict'] subset of master's ['+ Ring NEW conflict'] at 2c02386 - t27b-native-ratchet: rows 6 = master's or UNLISTED own new specs (t27b pass/blocked = steward applies, #8656) - claw-sarif: infra (TRI CLAW app lacks security_events:write) Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

…bin/reset_queue.t27 (Closes #9743) (#10056) Closes #9743 Merged by the rules (required checks green; every other red inherited): - Corpus ratchet (expected-failure ledger): ['+ Ring NEW conflict'] subset of master's ['+ Ring NEW conflict'] at 2c02386 - t27b-native-ratchet: rows 5 = master's or UNLISTED own new specs (t27b pass/blocked = steward applies, #8656) Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

#10579; Refs #8883, #8884) (#10175) Closes #10579 Merged by the rules (required checks green; every other red inherited): - Verilog widths (absurd-width ledger): ['specs/t27f/deps_card.t27', 'specs/t27f/why_card.t27'] subset of master's ['specs/t27f/deps_card.t27', 'specs/t27f/why_card.t27'] at b94c869 - t27b-native-ratchet: rows 4 = master's or UNLISTED own new specs (t27b pass/blocked = steward applies, #8656) Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

…h no hand Verilog or XDC (Closes #8889) (#8890) Closes #8875 Closes #8889 Merged by the rules (required checks green; every other red inherited): - Verilog widths (absurd-width ledger): ['specs/t27f/deps_card.t27', 'specs/t27f/why_card.t27'] subset of master's ['specs/t27f/deps_card.t27', 'specs/t27f/why_card.t27'] at b94c869 - t27b-native-ratchet: rows 4 = master's or UNLISTED own new specs (t27b pass/blocked = steward applies, #8656) Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

…bin/smoke_agent.t27 (Closes #9714) (#10022) Closes #9714 Merged by the rules (required checks green; every other red inherited): - Verilog widths (absurd-width ledger): ['specs/t27f/deps_card.t27', 'specs/t27f/why_card.t27'] subset of master's ['specs/t27f/deps_card.t27', 'specs/t27f/why_card.t27'] at b94c869 - t27b-native-ratchet: rows 5 = master's or UNLISTED own new specs (t27b pass/blocked = steward applies, #8656) Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

…bin/debug_queue.t27 (Closes #9704) (#10015) Closes #9704 Merged by the rules (required checks green; every other red inherited): - Verilog widths (absurd-width ledger): ['specs/t27f/deps_card.t27', 'specs/t27f/why_card.t27'] subset of master's ['specs/t27f/deps_card.t27', 'specs/t27f/why_card.t27'] at b94c869 - t27b-native-ratchet: rows 5 = master's or UNLISTED own new specs (t27b pass/blocked = steward applies, #8656) Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

Closes #8762 Merged by the rules (required checks green; every other red inherited): - Verilog widths (absurd-width ledger): ['specs/t27f/deps_card.t27', 'specs/t27f/why_card.t27'] subset of master's ['specs/t27f/deps_card.t27', 'specs/t27f/why_card.t27'] at b94c869 - t27b-native-ratchet: rows 4 = master's or UNLISTED own new specs (t27b pass/blocked = steward applies, #8656) Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

…Closes #5744) (#8843) Closes #1 Closes #5744 Merged by the rules (required checks green; every other red inherited): - Verilog widths (absurd-width ledger): ['specs/t27f/deps_card.t27', 'specs/t27f/why_card.t27'] subset of master's ['specs/t27f/deps_card.t27', 'specs/t27f/why_card.t27'] at b94c869 - t27b-native-ratchet: rows 4 = master's or UNLISTED own new specs (t27b pass/blocked = steward applies, #8656) Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

Merged by the rules (required checks green; every other red inherited): - Verilog widths (absurd-width ledger): ['specs/t27f/deps_card.t27', 'specs/t27f/why_card.t27'] subset of master's ['specs/t27f/deps_card.t27', 'specs/t27f/why_card.t27'] at 797bd09 - fpga-lint (read_verilog + hierarchy): [0] subset of master's [0] at b94c869 - t27b-native-ratchet: 4 UNLISTED rows are master specs already listed in the merged tree's ledger (ledger lag): ['specs/skills/t27-deps-card.t27', 'specs/skills/t27-why-card.t27', 'specs/t27f/deps_card.t27', 'specs/t27f/why_card.t27'] - t27b-native-ratchet: rows 5 = master's or UNLISTED own new specs (t27b pass/blocked = steward applies, #8656) - fpga-conformance: ['systolic'] subset of master's ['systolic'] at b94c869 - L1: trusted bot, exempt by the repo's own gates (#1031) Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

…bles, JTAG status) (Closes #8770) (#8772) Closes #8770 Merged by the rules (required checks green; every other red inherited): - Verilog widths (absurd-width ledger): ['specs/t27f/deps_card.t27', 'specs/t27f/why_card.t27'] subset of master's ['specs/t27f/deps_card.t27', 'specs/t27f/why_card.t27'] at 797bd09 - fpga-lint (read_verilog + hierarchy): [0] subset of master's [0] at b94c869 - t27b-native-ratchet: 4 UNLISTED rows are master specs already listed in the merged tree's ledger (ledger lag): ['specs/skills/t27-deps-card.t27', 'specs/skills/t27-why-card.t27', 'specs/t27f/deps_card.t27', 'specs/t27f/why_card.t27'] - t27b-native-ratchet: rows 4 = master's or UNLISTED own new specs (t27b pass/blocked = steward applies, #8656) - fpga-conformance: ['systolic'] subset of master's ['systolic'] at b94c869 Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

Merged by the rules (required checks green; every other red inherited): - Verilog widths (absurd-width ledger): ['specs/t27f/deps_card.t27', 'specs/t27f/why_card.t27'] subset of master's ['specs/t27f/deps_card.t27', 'specs/t27f/why_card.t27'] at 797bd09 - fpga-lint (read_verilog + hierarchy): [0] subset of master's [0] at b94c869 - t27b-native-ratchet: 4 UNLISTED rows are master specs already listed in the merged tree's ledger (ledger lag): ['specs/skills/t27-deps-card.t27', 'specs/skills/t27-why-card.t27', 'specs/t27f/deps_card.t27', 'specs/t27f/why_card.t27'] - t27b-native-ratchet: rows 5 = master's or UNLISTED own new specs (t27b pass/blocked = steward applies, #8656) - fpga-conformance: ['systolic'] subset of master's ['systolic'] at b94c869 - L1: trusted bot, exempt by the repo's own gates (#1031) Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

…rustc (Closes #8891) (#9135) Closes #8891 Merged by the rules (required checks green; every other red inherited): - Verilog widths (absurd-width ledger): ['specs/t27f/deps_card.t27', 'specs/t27f/why_card.t27'] subset of master's ['specs/t27f/deps_card.t27', 'specs/t27f/why_card.t27'] at 797bd09 - fpga-lint (read_verilog + hierarchy): [0] subset of master's [0] at b94c869 - t27b-native-ratchet: 4 UNLISTED rows are master specs already listed in the merged tree's ledger (ledger lag): ['specs/skills/t27-deps-card.t27', 'specs/skills/t27-why-card.t27', 'specs/t27f/deps_card.t27', 'specs/t27f/why_card.t27'] - t27b-native-ratchet: rows 5 = master's or UNLISTED own new specs (t27b pass/blocked = steward applies, #8656) - fpga-conformance: ['systolic'] subset of master's ['systolic'] at b94c869 Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

#10841; Refs #8883, #8884) (#10795) Closes #10841 Merged by the rules (required checks green; every other red inherited): - coverage: stale seals ['ml_train_hslm.json'] subset of master's ['ml_train_hslm.json'] at 22cdc61 (same seal as spec-guards: gen_hash_rust drift reproduced with master's t27c) - spec-guards: stale seals ['ml_train_hslm.json'] subset of master's ['ml_train_hslm.json'] at 22cdc61 (reproduced locally: t27c seal --verify) - scan: stale seals ['.claude/skills/self-cleanup/SKILL.md'] subset of master's ['.claude/skills/self-cleanup/SKILL.md'] at ae19b93 (reproduced locally: tools/check_devhome_paths.py; fix is #10852) - t27b-native-ratchet: 3 UNLISTED rows are master specs already listed in the merged tree's ledger (ledger lag): ['specs/fpga/analog_cell_ax7203.t27', 'specs/port/trios-railway/crates/trios-igla-race/src/bin/debug_queue.t27', 'specs/port/trios-railway/crates/trios-igla-race/src/bin/smoke_agent.t27'] - t27b-native-ratchet: rows 11 = master's or UNLISTED own new specs (t27b pass/blocked = steward applies, #8656) Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

…a void body's last call stays a statement (Closes #5649, Closes #5650, Closes #5651) (#8844) Closes #5649 Closes #5650 Closes #5651 Merged by the rules (required checks green; every other red inherited): - duplicate-bodies: ['a body written under dec_len is now copied [N] time(s) and was in no ledger', 'a body written under hex_val is now copied [N] time(s) and was in no ledger', 'a body written under imports_anchor is now copied [N] time(s) and was in no ledger', 'a body written under is_indented is now copied [N] time(s) and was in no ledger', 'a body written under is_word is now copied [N] time(s) and was in no ledger', 'a body written under jn_same is now copied [N] time(s) and was in no ledger', 'a body written under match_in is now copied [N] time(s) and was in no ledger', 'a body written under nn_text is now copied [N] time(s) and was in no ledger', 'a body written under nullish is now copied [N] time(s) and was in no ledger', 'a body written under put_all is now copied [N] time(s) and was in no ledger', 'a body written under skip_digits is now copied [N] time(s) and was in no ledger', 'a body written under skip_ws is now copied [N] time(s) and was in no ledger', 'a body written under trim_span is now copied [N] time(s) and was in no ledger', 'bytes_eq was copied [N] and is now copied [N]', 'ws_len_at was copied [N] and is now copied [N]'] subset of master's ['a body written under dec_len is now copied [N] time(s) and was in no ledger', 'a body written under hex_val is now copied [N] time(s) and was in no ledger', 'a body written under imports_anchor is now copied [N] time(s) and was in no ledger', 'a body written under is_indented is now copied [N] time(s) and was in no ledger', 'a body written under is_word is now copied [N] time(s) and was in no ledger', 'a body written under jn_same is now copied [N] time(s) and was in no ledger', 'a body written under match_in is now copied [N] time(s) and was in no ledger', 'a body written under nn_text is now copied [N] time(s) and was in no ledger', 'a body written under nullish is now copied [N] time(s) and was in no ledger', 'a body written under put_all is now copied [N] time(s) and was in no ledger', 'a body written under skip_digits is now copied [N] time(s) and was in no ledger', 'a body written under skip_ws is now copied [N] time(s) and was in no ledger', 'a body written under trim_span is now copied [N] time(s) and was in no ledger', 'bytes_eq was copied [N] and is now copied [N]', 'ws_len_at was copied [N] and is now copied [N]'] at 80cd57a - fpga-lint (read_verilog + hierarchy): [0] subset of master's [0] at 621a67c - t27b-native-ratchet: rows 15 = master's or UNLISTED own new specs (t27b pass/blocked = steward applies, #8656) - fpga-conformance: ['systolic'] subset of master's ['systolic'] at 621a67c Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

Merged by the rules (required checks green; every other red inherited): - compile-proofs: ['13 of 13 Coq files did not compile'] subset of master's ['13 of 13 Coq files did not compile'] at 4db9acc - fpga-lint (read_verilog + hierarchy): ["1/60 modules failed read_verilog or hierarchy. Defects inside uncalled function bodies are out of this job's reach -- see fpga-conformance and #2326."] subset of master's ["1/60 modules failed read_verilog or hierarchy. Defects inside uncalled function bodies are out of this job's reach -- see fpga-conformance and #2326."] at 7ad0615 - t27b-native-ratchet: 14 UNLISTED rows are master specs already listed in the merged tree's ledger (ledger lag): ['specs/claw/merge_judge.t27', 'specs/compiler/use_splice.t27', 'specs/widgets/bit_autopsy_logic.t27', 'specs/widgets/bit_diff_logic.t27', 'specs/widgets/build_receipt.t27', 'specs/widgets/fsm_sketch_logic.t27', 'specs/widgets/js_num.t27', 'specs/widgets/js_val.t27', 'specs/widgets/pin_map_logic.t27', 'specs/widgets/synth_smells_logic.t27', 'specs/widgets/t27_cell.t27', 'specs/widgets/t27_vs_nvfp4.t27', 'specs/widgets/test_touch.t27', 'specs/widgets/uart_bucket.t27'] - t27b-native-ratchet: rows 15 = master's or UNLISTED own new specs (t27b pass/blocked = steward applies, #8656) - fpga-conformance: ['systolic'] subset of master's ['systolic'] at 7ad0615 - L1: trusted bot, exempt by the repo's own gates (#1031) Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

Merged by the rules (required checks green; every other red inherited): - compile-proofs: ['13 of 13 Coq files did not compile'] subset of master's ['13 of 13 Coq files did not compile'] at 4db9acc - fpga-lint (read_verilog + hierarchy): ["1/60 modules failed read_verilog or hierarchy. Defects inside uncalled function bodies are out of this job's reach -- see fpga-conformance and #2326."] subset of master's ["1/60 modules failed read_verilog or hierarchy. Defects inside uncalled function bodies are out of this job's reach -- see fpga-conformance and #2326."] at 0ffd09c - t27b-native-ratchet: 14 UNLISTED rows are master specs already listed in the merged tree's ledger (ledger lag): ['specs/claw/merge_judge.t27', 'specs/compiler/use_splice.t27', 'specs/widgets/bit_autopsy_logic.t27', 'specs/widgets/bit_diff_logic.t27', 'specs/widgets/build_receipt.t27', 'specs/widgets/fsm_sketch_logic.t27', 'specs/widgets/js_num.t27', 'specs/widgets/js_val.t27', 'specs/widgets/pin_map_logic.t27', 'specs/widgets/synth_smells_logic.t27', 'specs/widgets/t27_cell.t27', 'specs/widgets/t27_vs_nvfp4.t27', 'specs/widgets/test_touch.t27', 'specs/widgets/uart_bucket.t27'] - t27b-native-ratchet: rows 15 = master's or UNLISTED own new specs (t27b pass/blocked = steward applies, #8656) - fpga-conformance: ['systolic'] subset of master's ['systolic'] at fcb3bc5 - L1: trusted bot, exempt by the repo's own gates (#1031) Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

Merged by the rules (required checks green; every other red inherited): - coverage: master red too at 65525cc -- CHECK SUBSET BY HAND - t27b-native-ratchet: rows 20 = master's or UNLISTED own new specs (t27b pass/blocked = steward applies, #8656) - fpga-conformance: ['systolic'] subset of master's ['systolic'] at ed2faab - L1: trusted bot, exempt by the repo's own gates (#1031) Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com>

…68.t27 (#11085) Closes #11052 Merged by the rules (required checks green; every other red inherited): - Verilog widths (absurd-width ledger): ['specs/widgets/bit_diff.t27', 'specs/widgets/lut_treemap.t27'] subset of master's ['specs/widgets/bit_diff.t27', 'specs/widgets/lut_treemap.t27'] at 2e2ca5f - t27b-native-ratchet: rows 41 = master's or UNLISTED own new specs (t27b pass/blocked = steward applies, #8656) Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com>

gHashTag enabled auto-merge (squash) October 10, 2026 14:45

gHashTag merged commit f21cbbb into master Oct 10, 2026
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gHashTag mentioned this pull request Oct 18, 2026

analog: sar_cdac.t27 -- the SAR ADC split capacitive DAC with its 1-unit bridge, charge redistribution against ngspice (Closes #10540) #10575

Merged

gHashTag mentioned this pull request Oct 19, 2026

analog: mos_psp103.t27 -- IHP SG13G2 PSP103 tables for five corners from ngspice, run by M3a's solver, inverter against ngspice (Closes #10516) #10778

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t27b ledger steward: the rules and the job card, so spec PRs stop editing the ledger (Closes #8654) - #8656

t27b ledger steward: the rules and the job card, so spec PRs stop editing the ledger (Closes #8654)#8656
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gHashTag commented Oct 10, 2026

Why

The rules: specs/tri/t27b/ledger_steward.t27

The job card: specs/jobs/t27b_ledger_steward.t27

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The rules: `specs/tri/t27b/ledger_steward.t27`

The job card: `specs/jobs/t27b_ledger_steward.t27`