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[https://nvbugs/6556429][fix] Fix host tier budget on integrated GPUs - #18926
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Included review availability: Your plan provides up to 12 included reviews per hour; 10 remain after this review. WalkthroughAutomatic host-tier sizing now detects integrated GPUs, charges device quota against shared memory, and returns zero when no host-tier headroom remains. Tests cover both shared-memory accounting and exhausted-memory behavior. ChangesHost-tier sizing
Priority: ⬇️ Low Estimated code review effort: 3 (Moderate) | ~20 minutes Suggested reviewers: Merge Risk: 🟡 Moderate · up to Integrated-GPU host-tier sizing now avoids duplicating the device quota when no headroom remains, but multi-rank integrated deployments may still allocate cache tiers beyond the shared physical-memory budget. This should be resolved before merge. 🚥 Pre-merge checks | ✅ 4 | ❌ 1❌ Failed checks (1 warning)
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Inline comments:
In `@tensorrt_llm/_torch/pyexecutor/kv_cache_manager_v2.py`:
- Line 276: Update the memory-budget calculation around mem_available so it
subtracts quota * local_ranks before dividing the remaining shared-memory budget
into per-rank host quota. Add an integrated-GPU test with local_ranks greater
than one that asserts local_ranks * (quota + host_quota) is no greater than
mem_available.
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tensorrt_llm/_torch/pyexecutor/kv_cache_manager_v2.pytests/unittest/_torch/executor/test_kvv2_host_tier_sizing.py
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Dev Engineer Review
KVCacheManagerV2now subtracts the device quota from the shared memory budget on integrated GPUs. With no remaining headroom, it returns zero and skips host-tier allocation. Discrete-GPU behavior, explicithost_cache_size, and public APIs remain unchanged.QA Engineer Review
Modified
tests/unittest/_torch/executor/kv_cache/test_kvv2_host_tier_sizing.py. Added coverage for integrated-GPU budget charging and zero host-tier provisioning without headroom. Existing discrete-GPU, memlock, fallback, and rank-synchronization coverage remains. The suite is listed in the CItest-db/lists for H100, A10, CPU, and B200. Coverage is sufficient.Per-File QA Perspective
tensorrt_llm/_torch/pyexecutor/kv_cache/kv_cache_manager_v2.py: Verify shared-memory accounting, zero-tier behavior, host-tier omission, and the diagnosablehost_cache_sizeerror path on integrated GPUs. Verify discrete-GPU and explicit host-cache sizing behavior remains unchanged.tests/unittest/_torch/executor/kv_cache/test_kvv2_host_tier_sizing.py: Covers integrated-GPU sizing, no-headroom handling, discrete-GPU fallbacks, memlock limits, and distributed quota synchronization. The suite is listed in the CItest-db/lists for H100, A10, CPU, and B200.Description
KVCacheManagerV2auto-provisions a pinned host cache tier sizedmin(device_quota, SC_AVPHYS_PAGES / local_ranks * 0.5, RLIMIT_MEMLOCK * 0.8).All three candidates assume host RAM is a pool separate from device memory. On an
integrated GPU (GB10 / DGX Spark) they are one physical LPDDR pool, so
SC_AVPHYS_PAGESreports bytes the device quota is about to consume:That is 128.5 GiB requested from a 119.69 GiB pool.
HostMemis prefaulted andpage-locked, so the kernel OOM-kills the worker — by signal, so there is no Python
traceback, only an MPI "non-zero exit code" message.
Charge the device quota against
mem_availablewhen the two tiers share one pool,gated on
is_device_integrated(). When no headroom is left, provision no host tierrather than falling back to the device quota — that fallback would request 2x the pool
and reinstate the OOM. Dropping the tier costs
MAX_UTILIZATIONsuspend/resume itsspill target, but fails with a diagnosable error naming
host_cache_sizeinstead of aSIGKILL.This is the
local_ranks == 1variant of the double-count the rank-aware divisoraddressed for co-located ranks on GB300 NVL72. Discrete-GPU behavior is unchanged:
shares_device_memorydefaults toFalse.Test Coverage
tests/unittest/_torch/executor/test_kvv2_host_tier_sizing.py:TestComputeAutoHostTierQuota::test_integrated_gpu_charges_device_quota_against_budgetTestComputeAutoHostTierQuota::test_integrated_gpu_without_headroom_provisions_no_tierExisting cases in the same class cover the unchanged discrete-GPU path.
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