[pi0]

Summary

• Schedule a setTimeout per TTL entry to proactively delete it from the internal Map when it expires
• Prevents unbounded memory growth from entries that are never read again (e.g. unique URLs with varying query params)
• Timers use .unref() so they don't prevent process exit
• Previous timers for the same key are cleared on overwrite or delete

Ref unjs/ocache#10 nitrojs/nitro#2138

Test plan

• Added regression test: stores entries with short TTL, waits for expiry without reading, verifies proactive cleanup
• All existing memory driver tests pass

Summary by CodeRabbit

• New Features

  • The in-memory driver now supports Time-to-Live (TTL) expiration for individual items, automatically removing items after a configured duration.
  • Expired items are proactively cleaned up and no longer accessible via storage queries.

• Tests

  • Added regression tests validating TTL expiration behavior and automatic cleanup without requiring manual key reads.

[coderabbitai]

Caution

Review failed

The pull request is closed.

ℹ️ Recent review info

⚙️ Run configuration

Configuration used: defaults

Review profile: CHILL

Plan: Pro

Run ID: 9338e45a-a883-4676-9696-978667f66b97

📥 Commits

Reviewing files that changed from the base of the PR and between e9bdc8b and 7ac54a3.

📒 Files selected for processing (2)

• src/drivers/memory.ts
• test/drivers/memory.test.ts

---

📝 Walkthrough

Walkthrough

Added per-key TTL support to the in-memory cache driver using a timers map. When setting items with optional TTL, existing timers are cleared and new expiry timers are scheduled to auto-delete keys. A regression test validates automatic expiration after TTL expires without explicit reads.

Changes

Cohort / File(s)	Summary
In-memory TTL implementation src/drivers/memory.ts	Added timers map to track expiry timers per key. Updated setItem and setItemRaw to accept optional opts with ttl parameter; clearing existing timers before scheduling new expiry timers. Updated removeItem, clear, and dispose to cancel and clean up timers.
TTL regression test test/drivers/memory.test.ts	Added async test validating that items with short TTL (0.01s) are automatically removed from the in-memory driver after expiration, confirming proactive cleanup without requiring explicit reads.

Sequence Diagram

sequenceDiagram
    actor User
    participant Driver as Memory Driver
    participant Storage as Storage Map
    participant Timers as Timers Map
    participant Timer as Node Timer

    User->>Driver: setItem(key, value, {ttl: 0.01})
    Driver->>Timers: Check & clear existing timer
    alt Timer exists
        Timers->>Timer: clearTimeout()
    end
    Driver->>Storage: Store value
    Driver->>Timer: setTimeout(callback, 10ms)
    Timer->>Timers: Store timer reference
    Note over Driver: ~10ms delay
    Timer->>Driver: Timer fires (expiry callback)
    Driver->>Storage: Delete key
    Driver->>Timers: Remove timer reference
    Driver->>User: Confirm deletion

Loading

Estimated code review effort

🎯 3 (Moderate) | ⏱️ ~20 minutes

Poem

🐰 A hopping tale of TTL grace,
Expired crumbs we've now erased!
Timers tick, then melt away,
No stale cache to clutter our day. ✨

✨ Finishing Touches

📝 Generate docstrings

• Create stacked PR
• Commit on current branch

🧪 Generate unit tests (beta)

• Create PR with unit tests
• Commit unit tests in branch fix/mem-ttl

📝 Coding Plan

• Generate coding plan for human review comments

---

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[codecov]

Codecov Report

❌ Patch coverage is 86.20690% with 4 lines in your changes missing coverage. Please review.
✅ Project coverage is 64.81%. Comparing base (e9bdc8b) to head (7ac54a3).
⚠️ Report is 1 commits behind head on main.

Files with missing lines	Patch %	Lines
src/drivers/memory.ts	86.20%	4 Missing ⚠️

Additional details and impacted files

@@            Coverage Diff             @@
##             main     #759      +/-   ##
==========================================
+ Coverage   64.52%   64.81%   +0.29%     
==========================================
  Files          43       43              
  Lines        2207     2234      +27     
  Branches      520      523       +3     
==========================================
+ Hits         1424     1448      +24     
- Misses        675      678       +3     
  Partials      108      108              

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