In SystemVerilog language there are two usages for operator <=
- traditional less-or-equal
- non-blocking assignment http://www.asic-world.com/tidbits/blocking.html more like left fat arrow.
Less-or-equal glyph looks wired as fat-arrow. Is any way to disable particular glyph? or switch depend on context?
I am using Atom
In SystemVerilog language there are two usages for operator
<=Less-or-equal glyph looks wired as fat-arrow. Is any way to disable particular glyph? or switch depend on context?
I am using Atom