When I used CubeMX to verify clock settings of NUCLEO-H563ZI, an error occurred.
I also looked at reference datasheet for H563ZI chip and found some parts that were not optimized.
- ADC/DAC input clock is too high
|
PeriphClkInitStruct.OspiClockSelection = RCC_OSPICLKSOURCE_HCLK; |
The maximum clock for ADC/DAC components is 125MHz, but HCLK is 250MHz, so input clock is too high.
As an idea, by setting PLL2 to N = 125 R = 4 it is possible to supply 125MHz from PLL2R to ADC/DAC.
- LPUART clock is low
|
PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; |
The LPUART will accept up to 250MHz, but PLL2Q is set to 32MHz, which may result in reduced performance.
I think using a PCLK3 (250MHz) would be fine.
The H563ZI Generic board seems to have same problem.
|
PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; |
When I used CubeMX to verify clock settings of NUCLEO-H563ZI, an error occurred.
I also looked at reference datasheet for H563ZI chip and found some parts that were not optimized.
Arduino_Core_STM32/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/variant_NUCLEO_H563ZI.cpp
Line 238 in 6e60087
The maximum clock for ADC/DAC components is 125MHz, but HCLK is 250MHz, so input clock is too high.
As an idea, by setting PLL2 to
N = 125R = 4it is possible to supply 125MHz from PLL2R to ADC/DAC.Arduino_Core_STM32/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/variant_NUCLEO_H563ZI.cpp
Line 237 in 6e60087
The LPUART will accept up to 250MHz, but PLL2Q is set to 32MHz, which may result in reduced performance.
I think using a PCLK3 (250MHz) would be fine.
The H563ZI Generic board seems to have same problem.
Arduino_Core_STM32/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/generic_clock.c
Line 81 in 6e60087