broken atomic lock when starting multiple cores #463

Hello,

Synchronization between cores in SMP mode relies on STLR/LDAR instructions to implement release/acquire semantics on the print_lock flag. These instructions depend on proper cache coherency and on memory being mapped as Normal, Inner Shareable.

Therefore, all cores must have the MMU (and caches) enabled with consistent attributes in order to use locks across cores0

In loader.c:main(), the MMU on logical core 0 is enabled after the secondary cores have already been started.
As a result, core 0 does not participate in the coherency domain when the other cores begin execution. Consequently, updates to the print_lock flag performed by secondary cores are not observed by core 0, leading to an infinite loop.

Workarounds are: Disabling the data cache via SCTLR.C, or using Normal_NC in MAIR for the translation tables

The MMU on core 0 should be enabled before releasing secondary cores.

Originally posted by @bruelc in #446 (comment)