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Support Intel IceLake ISAs through target_feature #67329

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@elalfer

Working on CPUID based dispatch for Vector AES code for https://crates.io/crates/crypto_pimitives library.

Based on https://doc.rust-lang.org/reference/attributes/codegen.html#x86-or-x86_64 Rust doesn't support any AVX512 targets.

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  1. added
    O-x86_64Target: x86-64 processors (like x86_64-*) (also known as amd64 and x64)
    A-SIMDArea: SIMD (Single Instruction Multiple Data)
    T-compilerRelevant to the compiler team, which will review and decide on the PR/issue.
    on Feb 6, 2020
  2. workingjubilee commented on Sep 18, 2020

    @workingjubilee
    Member

    The reference is outdated only concerned with stable here, there is partial AVX512 support in core::arch and the compiler on nightly, as can be seen here: https://doc.rust-lang.org/core/arch/x86_64/index.html

    As there is quite a lot to support it has not been finished (nor stabilized) however: rust-lang/stdarch#310
    So I believe it does not yet include the specifics of the AVX512 VAES extension you want, either.

  3. DevJPM commented on Oct 18, 2020

    @DevJPM
    Contributor

    I have looked into implementing this (for nightly at least over on rust-lang/stdarch) however it appears that support is blocked by the compiler not being willing to accept the VAES (and vaguely related VPCLMULQDQ) feature flags for enabling the relevant LLVM intrinsics. And I would be willing to make a PR for the compiler to add that flag, but I'm not sure if there's more to it than "just" adding the "vaes" string here and here. Though the feature seems to be supported in std::detect already though it is named avx512vaes there.

  4. added 2 commits that reference this issue on Nov 18, 2020
  5. workingjubilee commented on Apr 29, 2021

    @workingjubilee
    Member

    In #78361, a large amount of support for AVX512 features was added to the compiler, including all the ones (afaict) that IceLake included, resolving this issue for the Rust compiler, and many intrinsics have been added to std::arch since.

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    A-SIMDArea: SIMD (Single Instruction Multiple Data)C-feature-requestCategory: A feature request, i.e: not implemented / a PR.O-x86_64Target: x86-64 processors (like x86_64-*) (also known as amd64 and x64)T-compilerRelevant to the compiler team, which will review and decide on the PR/issue.

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