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Documentation says that SSE4.1 includes SSE3, but LLVM says SSSE3 #891
Description
The list of available target features says that sse4.1 implicitly enables sse3 (but not ssse3). However, looking at LLVM source code, it looks like that SSE4.1 also includes SSSE3.
def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
"Enable SSE instructions">;
def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
"Enable SSE2 instructions",
[FeatureSSE1]>;
def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
"Enable SSE3 instructions",
[FeatureSSE2]>;
def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
"Enable SSSE3 instructions",
[FeatureSSE3]>;
def FeatureSSE41 : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
"Enable SSE 4.1 instructions",
[FeatureSSSE3]>;
def FeatureSSE42 : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
"Enable SSE 4.2 instructions",
[FeatureSSE41]>;
Activity
ehuss commentedon Oct 11, 2020
Yea, looks like a mistake. Ugh, I remember spending a lot of time pouring through LLVM code to try to make sure those were correct. 😦 Would you be willing to submit a PR to fix it?
eduardosm commentedon Oct 11, 2020
No problem, I'll do it
tesuji commentedon Oct 12, 2020
ssse3 implicits sse3.