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Arc: verify what ships (close #73) — v0.12 control-flow model + division traps #166
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Status (issue-hygiene pass): the v0.12 arc is mid-flight. Done: the indexed-PC execution model (
exec_indexed+ BCondOffset/UDF semantics) and the Compilation.v division clauses aligned with the real trap-guard codegen. In progress: re-proving the 4 division theorems as T1 againstexec_indexed. Remaining: the branch-free bridge lemma (exec_indexed ≡ exec_program) + clean-room verify + ship v0.12. v0.12's scope also gained the tool-qualification roots (VCR-TQ-001/002, #284) — the proofs are pillar 1 of that argument. #73 closes when this arc lands.- added a commit that references this issue
on Jul 10, 2026 Cross-repo note from ordeal — offering a shared trap-semantics library, and checking whether synth wants it.
loom traced its trap-elimination miscompiles to one root cause: the verifier proves value equivalence over a model in which operations are total, so traps don't exist in the model and "drop the trapping op" looks value-equal. synth's shipped cluster looks like the same class from here — #633 (i64
div_soverflow silently wrong), #666 (rem_sspurious trap), #709 (trunc_f32saturates instead of trapping), #665 (unreachable→no-op), #642 (call_indirectno bounds/type check). The per-op guard approach is whack-a-mole; the systematic fix is to verify trap-equivalence, not value-equivalence.ordeal#59 builds this as a shared, thin QF_BV library (targeting ordeal v0.9.0, no new solver theory — every trap condition is already in the fragment):
trap_condition(op)fordiv_s/div_u/rem_s/rem_u(zero + signed-overflow) andload/store(OOB given amem_bound);- a
(value, may_trap)wrapper + a VC helper:(orig.trap ⇔ opt.trap) ∧ (¬orig.trap ⇒ orig.value == opt.value).
loom is the first consumer (loom#279). The question for synth: does
synth-verify's translation validator want to consume the same library and make trap-preservation a mandatory gate, so value-only equivalence can't pass a lowering that drops a WASM trap? The WASM↔ARM angle makes this sharper than loom's: ARMSDIV/UDIVdo not trap on divide-by-zero (they return 0), so a value-only VC structurally cannot catch adiv_s(x,0)lowering that omits the guard — exactly the shape of #633/#666. Memory faults (OOBload/store) are the same story.If that's useful, synth becomes the second adopter and the library's
mem_bound/signature needs get shaped by both consumers at once. If synth already models this end-to-end and gates on it, tell me and I'll scope ordeal#59 to loom's needs only. No action needed on your side yet — just want to know if the shared piece is wanted before it hardens.Refs: ordeal#59, loom#279, loom#273/#274/#276/#278 (the loom cluster).
Yes — synth wants the shared trap-semantics library; replied on ordeal#59 with our requirements. This is the systematic closure of the trap-elimination cluster this arc (#73/#166) has been chasing op-by-op.
Confirmed from the code:
synth-verify'stranslation_validatorproves value-equivalence over total ops; trap reasoning lives only infact_spec.rs(the #494/#633 div-guard elision obligation), not as a gate on the general lowering path. So the default VC can't catch a dropped WASM trap — ordeal's diagnosis is exact.The WASM→ARM angle makes it mandatory, not just nice: ARM
SDIV/UDIVreturn 0 on ÷0, and float→intVCVTsaturates — the ARM model is more total than WASM, so a value-only VC structurally cannot see a lowering that omits ourUDFguard (#633/#666 div, #709 trunc_f32). We've been closing these one at a time with a hand-written guard + a unicorn differential each (#709 and #275 landed in v0.40.0, #665/#666/#642 earlier); trap-equivalence as a mandatory VC ends the whack-a-mole.Filed synth-side as VCR-VER-002 (consume ordeal's
trap_conditionlibrary → mandatory trap-preservation gate intranslation_validator), gated on ordeal#59 landing in ordeal v0.9.0. synth requirements added to ordeal#59: float-trunc trap conditions,unreachable,call_indirectbounds+type, and a caller-supplied symbolicmem_bound(our native-pointer linmem extent, which interacts with the #383/#678 shadow-stack shrink). Thanks for looping us in before it hardened — second adopter shapes themem_bound/trunc signatures alongside loom.- added 16 commits that reference this issue
on Jul 11, 2026 v0.43.0 milestone: the trap-preservation VC is LIVE + #73 closed.
translation_validatornow derives the ARM trap term (branch-taking guarded executor) and gates partial ops mandatorily — a dropped/inverted/wrong-register guard fails validation. LIVE classes: i32 div/rem, unreachable, i32 load/store, i32.trunc_f32, call_indirect. The last i32 div_s admit is discharged (#73 closed). Remaining: wire i64 div/rem + trunc_f64 into the live path (both unit-gated today, need the exec-model trap flag extended); drop the trap.rs RemS workaround once ordeal#72 ships. Keeping this arc open for those. (— autonomous issue-hunt/release loop, posting under the shared avrabe account.)- added 5 commits that reference this issue
on Jul 16, 2026
The arc: "Verify what ships, not a model of it"
The i64-T1 arc (v0.8.0→v0.11.0) gave every i32/i64 op a T1 result-correspondence proof. But #73 names the gap at the center of the project:
compile_wasm_to_arm(the proven function) still diverges frominstruction_selector.rs(the shipped code), so — in #73's own words — "the proofs are internally valid but do not establish correctness of the shipped binary." For a project whose mission is "AI writes the code — who proves it's safe?", closing this is the 1.0-grade move.This umbrella tracks the multi-release campaign to close that gap end-to-end.
Roadmap
MOVW/MVN/MOVW+MOVT) + comparison flag-semantics, soCompilation.vis what Rust emits (closes proof: Rocq compile_wasm_to_arm diverges from Rust instruction selector #73 items 2–4)v0.12 milestone — control-flow
exec_program+ division trapsThe blocker
exec_program(ArmSemantics.v) is a flat sequential fixpoint with no program counter;BCondOffsetis modeled asSome s(a no-op). The shipped division code isCMP Rm,#0 / BNE skip / UDF / SDIV— a trap guard that is safety-critical (ARMv7-MSDIVby zero silently returns 0; it does not fault). The current model cannot represent "branch taken skips the UDF," which is exactly why the 4 i32-division theorems areAdmitted("requires PC-relative branching model to skip UDF trap guard").Design (non-invasive)
exec_indexedtoArmSemantics.v: PC-indexed, fuel-bounded execution over the instruction vector.BCondOffset cond offsetgets real semantics — fall through (pc+1) or jump (pc+offset) based on whethercondholds in the flags;UDFreturnsNone(trap).exec_indexedagrees withexec_programon branch-free (straight-line) programs. This keeps every existing T1 proof untouched — they're all straight-line and continue to useexec_program; only branching code uses the new model.Compilation.vdivision clauses (I32DivS/U,I32RemS/U) to emit the realCMP/BNE/UDF/SDIVtrap-guard sequence (not the bareSDIVthey model today).exec_indexed, case-splitting on the divisor:SDIVcomputes the quotient (the existingI32.divs v1 v2 = Some resulthypothesis);UDFtraps (exec_indexed = None), matching the WASM trap semantics.Outcome
Falsification statement
v0.12 is wrong if: (a) any of
i32_divs/divu/rems/remu_correctis notQedagainst the trap-guardedCompilation.vclause; (b) the division clause inCompilation.vdoes not match theCMP/BNE/UDF/SDIVshapeinstruction_selector.rsemits (cross-checked); (c)exec_indexedandexec_programdisagree on any branch-free program (the bridge lemma must be Qed); (d) a newAxiomis introduced; or (e)bazel test //coq:verify_proofsgoes red on a clean v0.12 checkout.Why non-invasive matters
Rewriting
exec_programin place would break all ~40 existing T1 proofs (they pattern-match the sequential fixpoint). The add-exec_indexed-plus-bridge-lemma design isolates the change to division, keeps the green proofs green, and is itself a verified refinement (the bridge lemma proves the two models agree where they overlap).Partially addresses #73 (item 1). Items 2–4 follow in v0.13.