prjunnamed needs "prototypes" for all target cells, which involve the list and widths of all input, output, and inout pins, as well as types, constraints, and default values of all parameters. We should provide a list of prototypes as part of the database.
The database need not describe all the constraints of a target cell — for more complex cases, it's fine to just special-case it in target-specific code.
The database also doesn't need to contain all cells — the representation of logic cell bits will likely be adjusted by prjunnamed to be convenient for synthesis and P&R. We should focus on the huge boring cells with lots of ports and parametrs, ie. mostly hard IP. prjunnamed will adjust the database as it sees fit before using it as prototype list.
For SiliconBlue, we already have such a list, though it will have to be adjusted a bit to fit prjunnamed needs.
For Xilinx, we already have port lists, though they also need adjustment to gather single-bit ports into buses, which has ugly cases (sigh PowerPC). ise-hammer also already has long lists of parameters for hard IP and transceivers, which could be cleaned up a bit and moved someplace better.
prjunnamed needs "prototypes" for all target cells, which involve the list and widths of all input, output, and inout pins, as well as types, constraints, and default values of all parameters. We should provide a list of prototypes as part of the database.
The database need not describe all the constraints of a target cell — for more complex cases, it's fine to just special-case it in target-specific code.
The database also doesn't need to contain all cells — the representation of logic cell bits will likely be adjusted by prjunnamed to be convenient for synthesis and P&R. We should focus on the huge boring cells with lots of ports and parametrs, ie. mostly hard IP. prjunnamed will adjust the database as it sees fit before using it as prototype list.
For SiliconBlue, we already have such a list, though it will have to be adjusted a bit to fit prjunnamed needs.
For Xilinx, we already have port lists, though they also need adjustment to gather single-bit ports into buses, which has ugly cases (sigh PowerPC).
ise-hammeralso already has long lists of parameters for hard IP and transceivers, which could be cleaned up a bit and moved someplace better.