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This repository was archived by the owner on Mar 12, 2026. It is now read-only.
This repository was archived by the owner on Mar 12, 2026. It is now read-only.

Xilinx in-hardware verification #6

Description

@wanda-phi
  • prepare a (possibly quick-and-dirty) JTAG stack with support for relevant devices
    • Glasgow
    • Xilinx Platform Cable
    • FTDI MPSSE
    • Digilent Adept
  • implement Bitstream assembler and disassembler #15
  • make a generic interconnect tester (creates completely random paths through the device, makes sure to exercise all possible wires and connections, makes sure the paths actually correctly route signals)
  • obtain devboards
    • Virtex
    • Virtex E
    • Virtex 2
    • Virtex 2 Pro
    • Spartan 3
    • Spartan 3E
    • Spartan 3A
    • Spartan 3A DSP
    • Spartan 6
    • Virtex 4
    • Virtex 5
    • Virtex 6
    • Virtex 7
  • slowly go through all relevant primitives of all devices, verify and document them
    • ... idk fill out the list at some point

Activity

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