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fix: use DSB SY barrier and system-scope atomic load in fence for RDMA GPU visibility #3141

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fix: use DSB SY barrier and system-scope atomic load in fence for RDMA GPU visibility #3141

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8 changes: 7 additions & 1 deletion mlx/backend/metal/fence.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4,6 +4,8 @@
#include "mlx/scheduler.h"
#include "mlx/utils.h"

#include <arm_acle.h>

namespace mlx::core {

struct FenceImpl {
Expand Down Expand Up @@ -111,7 +113,11 @@ void Fence::update(Stream stream, const array& x, bool cross_device) {
return;
}

f.cpu_value()[0] = count;
// seq_cst compiles to DMB ISH (inner-shareable) on ARM64,
// which is not visible to the GPU. Use DSB SY (full system)
// to force the store to the point of coherence.
f.cpu_value()->store(count, std::memory_order_seq_cst);
__dsb(0xF);
});
return;
}
Expand Down
23 changes: 17 additions & 6 deletions mlx/backend/metal/kernels/fence.metal
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Expand Up @@ -41,12 +41,23 @@ constexpr constant metal::thread_scope thread_scope_system =
volatile coherent(system) device uint* timestamp [[buffer(0)]],
constant uint& value [[buffer(1)]]) {
while (1) {
metal::atomic_thread_fence(
metal::mem_flags::mem_device,
metal::memory_order_seq_cst,
metal::thread_scope_system);
if (timestamp[0] >= value) {
break;
// Fast path: volatile reads through GPU cache + system-scope fence
for (uint i = 0; i < 1000000; i++) {
metal::atomic_thread_fence(
metal::mem_flags::mem_device,
metal::memory_order_seq_cst,
metal::thread_scope_system);
if (timestamp[0] >= value) {
return;
}
}
// System-scope atomic load to force GPU cache refresh from SLC
uint cur = __metal_atomic_load_explicit(
timestamp,
int(metal::memory_order_relaxed),
__METAL_MEMORY_SCOPE_SYSTEM__);
if (cur >= value) {
return;
}
}
}