Multi-cycle divider improvements: FSM enum, 1's complement, and quotient-only mode

[joserochh]

Description & Motivation

This PR refactors and extends the MultiCycleDivider with two key changes:

1. FSM Refactor (divider.dart): Replaces the manual ad-hoc FSM (using _MultiCycleDividerState static constants, raw Combinational/Sequential blocks, and a currentState/nextState pair) with ROHD's FiniteStateMachine. The state constants are promoted to a proper enum MultiCycleDividerStates. This reduces boilerplate, improves readability, and aligns with idiomatic ROHD patterns.

2. Quotient-only mode (computeRemainder flag): Adds a computeRemainder parameter to MultiCycleDivider. When false, the divider uses a faster O(n) binary long-division algorithm (one quotient bit per clock cycle) instead of the full O(n²) greedy algorithm, and the remainder output is always 0.

3. New OnesComplementDivider (ones_complement_divider.dart): Adds a new sibling divider that uses one's complement signed arithmetic instead of two's complement. It shares the same MultiCycleDividerInterface and MultiCycleDividerStates FSM but replaces the sign-negate operation (~x + 1) with a simpler bitwise invert (~x), reducing the critical path in the convert state. It also supports the computeRemainder flag with both O(n²) and O(n) modes.

Related Issue(s)

#139

Testing

• Existing tests for MultiCycleDivider were extended to run in both computeRemainder: true and computeRemainder: false modes (all test groups are now parameterised over both modes).
• New VF test infrastructure added for OnesComplementDivider: dedicated OnesComplementInputMonitor, OnesComplementScoreboard, OnesComplementAgent, OnesComplementEnv, and OnesComplementTest classes.
• New test sequences added: OnesCompBasicSequence, OnesCompEvilSequence (including negative-zero divisor edge cases), OnesCompVolumeSequence (1000 random vectors), and OnesCompSignedCornerSequence (all four sign quadrants + both divide-by-zero forms).
• Corner-case sequence (MultiCycleDividerCornerSequence) added for the two's complement divider covering signed boundaries, overflow (MIN_INT ÷ −1), and divide-by-zero.
• A fix to currIndex width (logDataWidth + 1 bits) ensures the loop-exit condition works correctly for all data widths.

Backwards-compatibility

Is this a breaking change that will not be backwards-compatible? If yes, how so?

No

Documentation

Does the change require any updates to documentation? If so, where? Are they included?

Doc changes included in this PR.

[desmonddak]

I wonder about the organization -- both dividers could share a common class that has all the state management, and this could be called MultiCycleDivider, and then we could have a TwosComplementDivider and a OnesComplementDivider extend and use some customization of the logic. Right now, OnesComplementDivider uses the states of the MultiCycleDivider, but everything else is different, and it isn't clear why.

One good reason to figure this out is that we may end up with other 1 versus 2s complement arithmetics and we might be able to borrow some of the key differences (say during accumulation you need to do slightly different things).