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Don't drop umasks of 0 - #388
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If the umask is 0 the UMaskExt wasn't being considered as a UMask of 0 was being encoded as None/unnecessary.
edwarddavidbaker
self-requested a review
September 24, 2026 20:54
Contributor
|
Good catch! Attaching a full diff of the outputs compared to main. Does perf use the same concatenated output ARL core examplediff -rup main/arrowlake/cache.json pr/arrowlake/cache.json
--- main/arrowlake/cache.json 2026-09-25 08:39:00.198019605 -0700
+++ pr/arrowlake/cache.json 2026-09-25 08:39:30.842015981 -0700
@@ -1107,6 +1107,7 @@
"EventName": "MEM_LOAD_RETIRED.L1_HIT_L1",
"PublicDescription": "Counts retired load instructions with at least one uop that hit in the Level 1 of the L1 data cache. Available PDIST counters: 0,1",
"SampleAfterValue": "1000003",
+ "UMask": "0x100",
"Unit": "cpu_core"
},
{From event configuration: {
"EventCode": "0xd1",
"UMask": "0x00",
"UMaskExt": "0x01",
"EventName": "MEM_LOAD_RETIRED.L1_HIT_L1",
"BriefDescription": "Counts retired load instructions with at least one uop that hit in the Level 1 of the L1 data cache.",
"PublicDescription": "Counts retired load instructions with at least one uop that hit in the Level 1 of the L1 data cache.",
"Counter": "0,1,2,3",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"Precise": "1",
"CollectPEBSRecord": "2",
"TakenAlone": "0",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0",
"Data_LA": "0",
"L1_Hit_Indication": "0",
"Errata": "null",
"Offcore": "0",
"Deprecated": "0",
"Equal": "0",
"PDISTCounter": "0,1",
"Speculative": "0"
},CLX uncore examplediff -rup main/cascadelakex/uncore-interconnect.json pr/cascadelakex/uncore-interconnect.json
--- main/cascadelakex/uncore-interconnect.json 2026-09-25 08:39:03.190018915 -0700
+++ pr/cascadelakex/uncore-interconnect.json 2026-09-25 08:39:33.110015729 -0700
@@ -13563,6 +13563,7 @@
"EventName": "UNC_UPI_TxL_HDR_MATCH.DATA_HDR",
"Experimental": "1",
"PerPkg": "1",
+ "UMask": "0x800",
"Unit": "UPI"
},
{
@@ -13573,6 +13574,7 @@
"EventName": "UNC_UPI_TxL_HDR_MATCH.DUAL_SLOT_HDR",
"Experimental": "1",
"PerPkg": "1",
+ "UMask": "0x2000",
"Unit": "UPI"
},
{Where the event configuration is {
"Unit": "UPI LL",
"EventCode": "0x4",
"UMask": "0x0",
"PortMask": "0x00",
"FCMask": "0x00",
"UMaskExt": "0x08",
"EventName": "UNC_UPI_TxL_HDR_MATCH.DATA_HDR",
"BriefDescription": "This event is deprecated.",
"PublicDescription": "This event is deprecated.",
"Counter": "0,1,2,3",
"ELLC": "0",
"Filter": "na",
"ExtSel": "0",
"Deprecated": "1",
"FILTER_VALUE": "0"
},
{
"Unit": "UPI LL",
"EventCode": "0x4",
"UMask": "0x0",
"PortMask": "0x00",
"FCMask": "0x00",
"UMaskExt": "0x20",
"EventName": "UNC_UPI_TxL_HDR_MATCH.DUAL_SLOT_HDR",
"BriefDescription": "This event is deprecated.",
"PublicDescription": "This event is deprecated.",
"Counter": "0,1,2,3",
"ELLC": "0",
"Filter": "na",
"ExtSel": "0",
"Deprecated": "1",
"FILTER_VALUE": "0"
}, |
Contributor
Author
|
Yes, same logic for both core and uncore and we don't know the umask field width which is why the hacky string concatenation is done. I sent to LKML a full series with the fixes in: |
|
|
||
| # Fix ups. | ||
| # Fix up the umask. | ||
| # Drop additional umasks. |
Contributor
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Offmodule response depends on multiple UMasks. Would it be easier to resolve in a separate PR? In the following event UMask 0x01 can only be used when programming MSR 0x3E0 (https://github.com/intel/perfmon#programmingrestriction).
Input JSON
{
"EventCode": "0x2A",
"UMask": "0x01,0x02,0x04,0x08",
"UMaskExt": "0x00",
"EventName": "OMR.DEMAND_DATA_RD.ANY_MEMORY",
"BriefDescription": "OMR.DEMAND_DATA_RD.ANY_MEMORY",
"PublicDescription": "OMR.DEMAND_DATA_RD.ANY_MEMORY",
"Counter": "0,1,2,3,4,5,6,7",
"PEBScounters": "0",
"SampleAfterValue": "100003",
"MSRIndex": "0x3E0,0x3E1,0x3E2,0x3E3",
"MSRValue": "0xF5030000000001",
"Precise": "0",
"CollectPEBSRecord": "0",
"TakenAlone": "0",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0",
"Data_LA": "0",
"L1_Hit_Indication": "0",
"Errata": "null",
"Offmodule": "1",
"Deprecated": "0",
"Equal": "0",
"PDISTCounter": "0",
"CounterType": "PGMABLE",
"ProgrammingRestriction": "MSRIndex-UMask",
"Speculative": "0"
},Output
perfmon/scripts$ grep -rn -C4 OMR.DEMAND_DATA_RD.ANY_MEMORY ./pr/
./pr/novalake/other.json-151- "UMask": "0x1",
./pr/novalake/other.json-152- "Unit": "cpu_core"
./pr/novalake/other.json-153- },
./pr/novalake/other.json-154- {
./pr/novalake/other.json:155: "BriefDescription": "OMR.DEMAND_DATA_RD.ANY_MEMORY",
./pr/novalake/other.json-156- "Counter": "0,1,2,3,4,5,6,7",
./pr/novalake/other.json-157- "EventCode": "0x2A",
./pr/novalake/other.json:158: "EventName": "OMR.DEMAND_DATA_RD.ANY_MEMORY",
./pr/novalake/other.json-159- "MSRIndex": "0x3E0,0x3E1,0x3E2,0x3E3",
./pr/novalake/other.json-160- "MSRValue": "0xF5030000000001",
./pr/novalake/other.json:161: "PublicDescription": "OMR.DEMAND_DATA_RD.ANY_MEMORY Available PDIST counters: 0",
./pr/novalake/other.json-162- "SampleAfterValue": "100003",
./pr/novalake/other.json-163- "UMask": "0x1",
./pr/novalake/other.json-164- "Unit": "cpu_core"
./pr/novalake/other.json-165- },
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So I think this is a separate issue. For "UMask": "0x01,0x02,0x04,0x08" we use 0x01 as the UMask and the driver will use a different UMask as necessary given the other counter usage. Similarly for the MSRIndex.
edwarddavidbaker
approved these changes
Sep 25, 2026
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If the umask is 0 the UMaskExt wasn't being considered as a UMask of 0 was being encoded as None/unnecessary.