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blog: the seed moved Fmax 1.22x, the pins moved it 2.6x - #1204
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Two bench questions as two commands: tri fpga-seeds reports Fmax as a range over placement seeds, tri fpga-jtag identifies the chip on the chain without programming it. Bilingual, nextpnr estimates labelled as such, open questions in both languages. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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blog: the seed moved Fmax 1.22x, the pins moved it 2.6x (#1204) Two bench questions as two commands: tri fpga-seeds reports Fmax as a range over placement seeds, tri fpga-jtag identifies the chip on the chain without programming it. Bilingual, nextpnr estimates labelled as such, open questions in both languages. Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com>
This was referenced Oct 1, 2026
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Publishes the post "The seed moved Fmax 1.22x. The pins moved it 2.6x." (slug
the-seed-moved-it-the-pins-moved-it-more, EN + RU). The content was approved for publication by the maintainer in chat on 2026-10-01.{ "version": 1, "head_sha": "b37315d8c6051c159782a130ab39336193377bbc", "summary": "New bilingual blog post about two bench questions that became two commands. tri fpga-seeds treats Fmax as a range over nextpnr placement seeds: a 321-LUT ternary dot-product unit ran 164.15 to 200.40 MHz over 20 seeds and 62.68 to 76.75 MHz with its pins spread across the package, with the same netlist on every run. tri fpga-jtag reads which chip is on the JTAG chain without programming it, and tells a silent TDO from a broken cable. All Fmax figures are labelled as nextpnr post-route estimates, not sign-off timing.", "changes": [ "apps/website/src/data/blog/bodies/the-seed-moved-it-the-pins-moved-it-more.ts: new EN and RU body", "apps/website/src/data/blog/index.ts: new PostMeta entry (published: true) with receipts and five open questions in both languages", "apps/website/src/data/blog/posts.ts: import and map entry for the new body" ], "tests": [ { "command": "npx vite build (apps/website)", "status": "passed", "result": "build succeeds; the post title is present in the Blog chunk", "evidence": "local build of this head in a clean worktree off origin/main, 2026-10-01" }, { "command": "npm run typecheck:ratchet && npm run check:api", "status": "passed", "result": "no file gained type errors; api contract at baseline. The first run caught an unescaped apostrophe in the body (50 errors), fixed before this commit", "evidence": "same local run, 2026-10-01" }, { "command": "claim_guard.py on the body and the index entry", "status": "passed", "result": "clean, no forbidden claims", "evidence": "same local run, 2026-10-01" } ], "limitations": [ "Every Fmax is a nextpnr-xilinx post-route estimate on xc7a200tfbg484-2, not sign-off timing.", "The unit is measured stand-alone on synthetic pins; its Fmax inside a real SoC is not claimed.", "The spread-pinout sweep has 10 seeds, not 20.", "The second bench (XC7A100T on a DLC10 clone) still returns no JTAG chain; cause not found.", "The two commands live in a private repository for now, so readers cannot run them yet; stated in the post's open questions." ], "tags": ["FPGA", "OpenToolchain", "Verification", "Tooling"], "blog": { "title": "The seed moved Fmax 1.22x. The pins moved it 2.6x.", "summary": "This PR is itself the blog article: a placement seed sweep and a pinout sweep on the same netlist, and a read-only JTAG identity check that caught the wrong chip on our bench.", "outline": [ "Two questions every open-toolchain bench meets: which chip is on the cable, and is the logged Fmax a property of the design or of one seed.", "fpga-seeds: 20 seeds give 164.15 to 200.40 MHz (1.22x); spreading the pins gives 62.68 to 76.75 MHz, about 2.6x lower, same netlist; fpga-jtag caught an XC7A200T where an XC7A100T was expected.", "Open: stand-alone unit only, 10-seed pinout sweep, the XC7A100T bench still silent, commands not yet public." ] } }🤖 Generated with Claude Code