feat(fpga): pipeline the phi scale and take the cycles back

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#591 measured the iterative φ scale honestly and the honest answer was bad: smaller and faster on the clock, and 2.15× slower per output element at the |k| = 8 a deployed layer needs.

That was a property of the implementation, not of the lattice. This removes it.

Why not the closed form

φ^k = F(k−1) + F(k)·φ, so scaling (a,b) by φ^k is a' = a·F(k-1) + b·F(k), b' = a·F(k) + b·F(k+1) — two multiplications by Fibonacci constants. A barrel built that way puts back the operator this whole line exists to remove, so it was not built.

What was built

scale_phi_pipe.v unrolls the step: K_MAX stages, stage j applying (a,b) → (b, a+b) when j < k and passing through otherwise. One adder and one mux per stage, latency K_MAX, one element per cycle, no multiplier.

Verified before measured — 40 elements fed back to back against an independent golden model:

40 checks, 0 errors
one element per cycle, 40 accepted back to back

Negative control: breaking the adder by one is caught on 38 of 40.

Measured — nextpnr-ice40, hx8k ct256, N=8, ACC=16

layer	ICESTORM_LC	Fmax	elements/s
φ pipelined	660	204.08 MHz	204.08 M
multiplier	1098	69.21 MHz	69.21 M

1.66× smaller and 2.95× faster, on clock and throughput.

The ratio is 2.95× and not 5.90×. The multiplier arm has two cycles of latency and still accepts one element per cycle — prod is combinational from a registered accumulator and nothing gates the input. Counting its latency as cycles-per-element would have doubled the claim, and I checked the RTL before quoting it.

Cost against the iterative version

	LC	Fmax	cycles/element
iterative	97	182.78 MHz	k
pipelined	354	206.44 MHz	1

3.6× the scale-block area for k× the throughput. At the deployed |k| = 8 that is a good trade; below k = 4 the iterative version delivers the same rate for less.

A fold, caught by its own implausibility

The first version synthesised to 2 logic cells for an eight-stage 16-bit pipeline. Two always blocks drove the same array — a reset block writing every element and the generate stages writing their own — so yosys pruned nearly all of it. A fold never announces itself: it reports a number far too small rather than an error, and 2 is what made it visible.

What this does not establish

iCE40, not Artix-7, and iCE40 has no DSP blocks so the multiplier arm is maximally penalised. N=8 because at 16 the pair output needs 217 pins on a 206-pin package. No board, one output element, no weight or activation memory.