[W35][Lane V][RTL] LUT-NPU PE — OP_LUT_NPU=0xE3, 81-entry static LUT (zero *, 9/9 TB PASS)

[gHashTag]

Wave-35 Lane V — LUT-NPU PE RTL (OP_LUT_NPU = 0xE3)

Closes #123
Refs #120 (Wave-35 ONE SHOT)
Refs #61 (EPIC TT-shuttle)

Sibling lanes (already merged)

Lane	PR	Merge SHA
V Coq	t27#651	8e4f2a8a
V' JSON	trios#859	f2ee3613

What this PR adds

A synthesisable Verilog PE that materialises the Lane V Coq theorem in silicon.

rtl/lut_npu/lut_npu_pe.sv      158 lines — module
tb/lut_npu/lut_npu_pe_tb.sv    183 lines — TB (9 directed)
scripts/run_lut_npu_tb.sh             — iverilog driver + R-SI-1 gate
rtl/lut_npu/README.md                 — architecture notes

Architecture

• 9 ternary inputs × 9 ternary weights (encoding: 2'b01=+1, 2'b10=−1, 2'b00=0)
• Per-lane prod_plus[i] / prod_minus[i] from a single 2-bit comparison (no *, no FMA)
• Adder-tree popcount → n_plus, n_minus (each 0..9)
• Horner trick: 9 * n_plus = (n_plus << 3) + n_plus — pure shift+add
• addr = 9*n_plus + n_minus (7-bit, clamped to 80)
• Static lut_rom[k] = (k/9) − (k%9) for k=0..80 — hand-unrolled, no / or % at runtime (R-SI-1 clean)
• Outputs: lut_addr[6:0], lut_out signed [5:0], valid_out, wave35_marker = 4'b1110

Verification

$ bash scripts/run_lut_npu_tb.sh
LUT-NPU PE TB: 9 PASS / 0 FAIL
W35-G5 GATE: PASS (>=9/9)
R-SI-1 check: Star count: 0, Slash count: 0, Percent count: 0

Acceptance Gates

Gate	Spec	Observed	Status
W35-G1	OP_LUT_NPU = 8'hE3 decoded	yes	✅
W35-G2	No * / / / % at runtime	Star=0 Slash=0 Percent=0	✅
W35-G3	lut_rom[k] = (k/9)−(k%9) static	81 entries unrolled	✅
W35-G4	9×9 ternary 2-bit decode	per-lane comparison	✅
W35-G5	TB ≥ 9/9 PASS	9 PASS / 0 FAIL	✅
W35-G6	addr ≥ 7 bits	[6:0]	✅
W35-G7	wave35_marker = 4'b1110	yes	✅

ISA Chain

0xDF (Lane V LUT) → 0xE0 (Lane W BitROM) → 0xE1 TENET (W33 Lane T') 
  → 0xE2 TOM (W34 Lane Y) → 0xE3 LUT-NPU (W35 Lane V) ◀━ THIS

TOPS/W ladder (R5 sim-grade)

W33 TENET 195 → W34 TOM 225 → W35 LUT-NPU 270 → W41 IHP 22FDX 756 (Q4 2026)

Constitutional compliance

• R1 CROWN: Verilog only, no Rust/Coq drift
• R3 parent ONE SHOT 🎯 ONE SHOT — Wave-35 L-DPC32 LUT-NPU (Lever #9) · 270 TOPS/W · ×1.20 stack multiplier #120 has the contract
• R6 Zero Free Parameters: 81 LUT entries fully determined by (k/9)−(k%9), no tunables
• R7 Falsification Witness: TB 9/9 PASS is the witness
• R-SI-1: zero *///% at runtime — gate enforces in script
• R8 Author: admin@t27.ai (Vasilev Dmitrii, ORCID 0009-0008-4294-6159)
• R18 Layer Frozen: no Sacred ROM mutation (LUT is L1, not L0)

Pattern reference

Mirrors W34 Lane U RTL TOM (trinity-fpga#119, 243823a9).

φ²+φ⁻²=3 · γ=φ⁻³ · C=φ⁻¹ · G=π³γ²/φ · QUANTUM BRAIN 1:1 SILICON · 3-STRAND DNA · TRI NET · DOI 10.5281/zenodo.19227877 · NEVER STOP