fix(codegen): improve Verilog + C backend quality for all specs

[gHashTag]

Summary

• Implements ExprSwitch as nested ternary operators in Verilog backend (eliminates 12 unsupported expression placeholders)
• Implements StmtFor as Verilog for-loops with integer iteration (eliminates 15 unsupported statement placeholders)
• Fixes ExprReturn to assign to function name (Verilog semantics) instead of /* return */ placeholder (fixes 577 instances)
• Sanitizes module names: hyphens/special chars → underscores (fixes 5 invalid Verilog module identifiers)
• Adds current_fn_name tracking to VerilogCodegen struct

Results

Backend	Failures Before	Failures After	Target
gen-verilog	0 (exit code) / 27 unsupported exprs	0 / 0	< 5
gen-c	0	0	< 5
gen (Zig)	0	0	No regression

Test plan

• All 28 spec files pass gen-verilog (exit code 0)
• All 28 spec files pass gen-c (exit code 0)
• All 28 spec files pass gen (Zig — no regression)
• Zero /* unsupported expr */ markers in Verilog output
• Zero /* return */ placeholders in Verilog output
• Zero hyphenated module names in Verilog output
• cargo build --release succeeds
• cargo test passes

Closes #49

🤖 Generated with Claude Code