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Port fpga/verilog/e8m0_jtag.v (Verilog, 1 module) to specs/port/fpga/verilog/e8m0_jtag.t27 - #5103

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gHashTag merged 2 commits into
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queen-5096
Sep 28, 2026
Merged

gHashTag merged 2 commits into
masterfrom
queen-5096

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Closes #5096

Written by a bee on queen-5096 and published by tools/queen/publish.py. The branch itself is the bee's; the second commit is the coordination entry every pull request must add, which a bee has no way to know about.

1 file changed, 327 insertions(+)

🤖 Generated with Claude Code

Trinity Bee and others added 2 commits September 28, 2026 19:50
- Create T27 specification for E8M0 JTAG test module
- Port reset counter, probe generation, accumulator logic, beat counter, and JTAG shift register functions
- Add comprehensive tests for all key functions
- Maintain original module parameter and behavior

Closes #5096
A pull request must add exactly one docs/now entry and a bee has no way
to know that: its brief names a boundary file and acceptance criteria,
and docs/now/ is neither. The publisher adds it rather than failing the
gate.

Closes #5096

Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
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This notebook contains session context, decisions, and artifacts for this work.

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Generated at: 2026-09-28 19:54:53 UTC

Summary

Status Count
Total Open PRs 46
PRs with Failing Checks 42
PRs with All Checks Green 4
READY 3
FAILING 42
PENDING 0
NO CHECKS YET 0

These columns do not partition: 3 + 42 + 0 + 0 = 45, and there are 46 open PRs. A PR is being counted twice or not at all.

Seal Status

  • ⚠️ STALE -- sha256(compiler.rs)=403499176a5d != manifest seal=87e5cbd3ad94.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

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Port fpga/verilog/e8m0_jtag.v (Verilog, 1 module) to specs/port/fpga/verilog/e8m0_jtag.t27

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