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Port fpga/vivado/gf16_dot4.v (Verilog, 1 module) to specs/port/fpga/vivado/gf16_dot4.t27 - #4914

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gHashTag merged 2 commits into
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queen-4895
Sep 27, 2026
Merged

gHashTag merged 2 commits into
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queen-4895

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Closes #4895

Written by a bee on queen-4895 and published by tools/queen/publish.py. The branch itself is the bee's; the second commit is the coordination entry every pull request must add, which a bee has no way to know about.

1 file changed, 208 insertions(+)

🤖 Generated with Claude Code

Trinity Bee and others added 2 commits September 27, 2026 11:25
Implement GF(16) dot product module: result = (a0*b0 + a1*b1) + (a2*b2 + a3*b3)

Add structs for input/output vectors and intermediate results.
Implement compute_dot_product function matching original Verilog structure.
Add tests for zero input, ones input, simple pattern, and intermediate structure.
Add invariants for data width and associativity.

Closes #4895
A pull request must add exactly one docs/now entry and a bee has no way
to know that: its brief names a boundary file and acceptance criteria,
and docs/now/ is neither. The publisher adds it rather than failing the
gate.

Closes #4895

Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
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PR Dashboard

Generated at: 2026-09-27 11:34:07 UTC

Summary

Status Count
Total Open PRs 50
PRs with Failing Checks 41
PRs with All Checks Green 9
READY 3
FAILING 41
PENDING 0
NO CHECKS YET 0

These columns do not partition: 3 + 41 + 0 + 0 = 44, and there are 50 open PRs. A PR is being counted twice or not at all.

Seal Status

  • ⚠️ STALE -- sha256(compiler.rs)=403499176a5d != manifest seal=87e5cbd3ad94.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

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📓 NotebookLM Notebook linked to this PR

This notebook contains session context, decisions, and artifacts for this work.

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Port fpga/vivado/gf16_dot4.v (Verilog, 1 module) to specs/port/fpga/vivado/gf16_dot4.t27

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