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feat(gen-verilog): spec-first data ports + BitNet & GF-T hardware stack (Refs #1764) - #1791

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Aug 6, 2026
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feat/land-spec-first-hardware

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@gHashTag gHashTag commented Aug 6, 2026

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Refs #1764

Lands the spec-first hardware work from 11 improvement cycles, now that master is unblocked (#1790). Builds cleanly on master; 1535 unit tests + all 12 spec tests pass.

Compiler: opt-in data ports (seal-neutral)

Gated on on_clock/on_comb function names, so every existing spec is byte-identical:

  • on_clock module var state exposed as output reg ports (registered state observable → synthesizes to real FFs).
  • on_clock/on_comb params become input data ports.
  • on_comb return drives an output wire result (combinational designs become real hardware).

Specs (each iverilog + yosys + oracle cross-checked)

BitNet — synthesizes to Artix-7: comb_ternary_dot (dot27 → ~317 LUT), comb_bitnet_neuron (quantize(dot27) → ~319 LUT, a full neuron), comb_bitnet_layer (4 neurons → 288 LUT const / ~1287 general), stream_ternary_mac (streaming MAC → 32 FDCE), clocked_counter (8 FDCE). See docs/SYNTH_REPORT.md.

GF-T — bit-exact to the AX7203 silicon: gft_dot2 (the silicon MAC), gft_dot4/gft_dot8 (matmul/attention tiles), gft_layer2 (matmul row) — bit-exact to the silicon reduction tree over 2000 random vectors each.

GF-T RNE — bit-exact to the ideal oracle, MORE ACCURATE than silicon: gft_mul_rne + gft_add_rne + gft_dot2_rne (round-to-nearest-even, matching gft16_ref.py; the silicon truncates ~1 ULP low). 300 oracle vectors each.

FROZEN_HASH resealed; new-spec seals regenerated. Supersedes the stale-base PR #1786.

🤖 Generated with Claude Code

…e stack

Now that master is unblocked (#1790), land the spec-first hardware work
from 11 improvement cycles.

Compiler: opt-in data ports -- `on_clock` var state exposed as
`output reg`; `on_clock`/`on_comb` params become `input` data ports;
`on_comb` return drives an `output wire result`. Seal-neutral (gated on
on_clock/on_comb fn names, so existing specs are byte-identical).

Specs (each iverilog + yosys + oracle cross-checked):
- BitNet, synthesizes to Artix-7: comb_ternary_dot, comb_bitnet_neuron
  (a full neuron, ~319 LUT), comb_bitnet_layer, stream_ternary_mac
  (32 FDCE), clocked_counter. docs/SYNTH_REPORT.md.
- GF-T, bit-exact to the AX7203 silicon: gft_dot2/dot4/dot8/layer2.
- GF-T RNE, bit-exact to the ideal oracle (more accurate than the
  truncating silicon): gft_mul_rne, gft_add_rne, gft_dot2_rne.

Verified: 1535 unit tests pass; all 12 spec tests green on master's
compiler; FROZEN_HASH resealed; new-spec seals regenerated.

Refs #1764

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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📓 NotebookLM Notebook linked to this PR

This notebook contains session context, decisions, and artifacts for this work.

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PR Dashboard

Generated at: 2026-08-06 13:49:42 UTC

Summary

Status Count
Total Open PRs 3
PRs with Failing Checks 1
PRs with All Checks Green 2
READY 1
FAILING 1
PENDING 0

Seal Status

  • ⚠️ STALE -- sha256(compiler.rs)=de57378ec0e2 != manifest seal=87e5cbd3ad94.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

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gHashTag merged commit 96df462 into master Aug 6, 2026
21 of 23 checks passed
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