Wave Loop 859 — module-scope [537][2]^6 Pt non-power-of-two outer-dimension array-of-struct variable from call with indexed signed writes

.claude/plans/loop-w774-full-cycle.md

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+# /loop Iteration Plan — W774 Closeout + Audit + Literature + Skills
+
+**Date:** 2026-07-24  
+**Branch:** `wave-loop-774`  
+**Issue:** TBD (next available GitHub issue)  
+**Anchor:** φ² + φ⁻² = 3 | TRINITY
+
+## 0. Prompt from user
+
+> 15m loop: исследуй слабые места работы, исследуй научные работы по теме, создай декомпозированный план и реализуй все и в конце отчет и три варианта сотрудничества для следующего Wave лупа! сохрани в конце скилы.
+
+## 1. Weak-point audit (done in this iteration)
+
+| Metric | Current | Previous (W773) | Verdict |
+|--------|---------|-----------------|---------|
+| 30-day commits | 66 | — | — |
+| Subject-line `Closes #N` / `Fixes #N` | 10 / 66 ≈ 15.2% | ~84% | **REGRESSION** — many merge/closeout commits carry link only in body |
+| `.t27` specs without `test`/`invariant`/`bench` | 51 / 880 ≈ 5.8% | ~6.5% | **IMPROVED** |
+| `scripts/*.sh` on critical path | 19 | 19 | **STABLE** |
+| Untracked worktree noise | `specs/scratch/w485_*.t27` × 3 + `wave-loop-485.md` | — | **WEAK POINT** — stale W485 artefacts |
+| Pre-existing FPGA/formal CI failures | `sby` missing, Yosys Verilog-2005 static-cast in `build/fpga/generated/uart.v` | same | tracked as #1245, unrelated |
+
+**Top weak points to address during this cycle:**
+1. **L1 traceability drift:** 30-day subject-line issue-link rate dropped from ~84% to ~15%. Continue putting `Closes #<ISSUE>` in subject lines for feat/merge/closeout commits.
+2. **Stale W485 artefacts:** untracked `specs/scratch/w485_*.t27` and `.claude/plans/wave-loop-485.md` should be either committed or removed before W774 closeout.
+3. **NOW.md staleness:** `NOW.md` last updated 2026-05-24 and does not reflect current wave-loop work.
+
+## 2. Literature scan (done in this iteration)
+
+### Ternary / MVL EDA (2025–2026)
+- **SONIC** — event-driven gate-level simulator/verifier for ternary VLSI using delta cycles, BCT Verilog FPGA export (IEEE ISMVL 2026) [doi:10.1109/ismvl68998.2026.00042](https://doi.org/10.1109/ismvl68998.2026.00042).
+- **TVHDL** — balanced-ternary extension to IEEE 1076-2008 VHDL, verified with GHDL/GTKWave (IEEE ISMVL 2026) [doi:10.1109/ismvl68998.2026.00041](https://doi.org/10.1109/ismvl68998.2026.00041).
+- **KULeuven ternary-lut-dse** — Chisel generator for LUT-based ternary MatMul targeting 1.58-bit LLMs, accepted IEEE ISPASS 2026 ([GitHub](https://github.com/KULeuven-MICAS/ternary-lut-dse)).
+- **TerEffic** — ternary LLM inference on AMD Alveo U280 with LUT-based TMat Core, arXiv 2025 ([arXiv:2502.16473](https://arxiv.org/html/2502.16473v2)).
+
+### Verification / cocotb (2025–2026)
+- **DVCon EU 2025** — unified FPGA firmware verification with cocotb + pytest + shared scoreboard/Python reference model ([paper PDF](https://dvcon-proceedings.org/wp-content/uploads/DVConEU_2025_paper_95.pdf)).
+- **cocotb 2.0/2.1** — `@cocotb.parametrize`, `cocotb_tools.runner.Runner`, pytest integration, JUnit XML improvements ([release notes](https://docs.cocotb.org/en/development/release_notes.html)).
+
+### Relevance to t27
+- t27’s scalar packed-vector lowering avoids native Icarus/Yosys gaps with arrays of packed structs, consistent with literature trend of flattening to wide vectors.
+- cocotb 2.x pytest convergence supports the existing `t27c icarus-cocotb` reference-model path.
+
+## 3. Decomposed implementation plan
+
+### Phase A — Housekeeping (15 min)
+1. Decide fate of stale W485 artefacts:
+   - Option 1: delete untracked `specs/scratch/w485_*.t27` and `wave-loop-485.md` if W485 is abandoned.
+   - Option 2: open issue #1455, branch `wave-loop-485`, and stage them.
+   - **Recommendation:** delete from this branch; W485 can be recreated from the plan file in git history if needed.
+2. Update `.trinity/current-issue.md` with actual GitHub issue number once known.
+
+### Phase B — W774 Spec + Test (30 min)
+3. Generate `scripts/gen_w774.py` from `scripts/gen_w773.py` with `OUTER = 367`, `MID_IDX = 183`.
+4. Run generator to produce `specs/scratch/w774_bench_module_367x2p6_aos_var_call_write.t27`.
+5. Manually fix the f-string module header (`{OUTER}` → actual number) if generator emits it literally.
+6. Add integration test `accepts_w774_bench_module_367x2p6_aos_var_call_write` to `bootstrap/tests/icarus_lowerable.rs`.
+
+### Phase C — Build + Seal + Verify (45 min)
+7. `cd bootstrap && cargo build --release -p t27c`.
+8. `t27c parse`, `icarus-lowerable`, `icarus-simulate` (17 cycles), `icarus-cocotb` on the W774 witness.
+9. `t27c seal --save` the witness; confirm `FROZEN_HASH` unchanged.
+10. `cargo test -p t27c --bin t27c`, `cargo test -p tri`, `cargo test -p t27c --test icarus_lowerable`.
+
+### Phase D — Closeout + Cooperation Variants (30 min)
+11. Write `docs/reports/FPGA_LOOP_CLOSEOUT_W774_2026-07-24.md` with:
+    - what worked, what changed behavior, validation matrix, scientific background, weak-point audit, literature scan.
+12. Append W774 learnings to `.trinity/experience.md`.
+13. Propose three cooperation variants for W775 in the closeout report and in `.trinity/current-issue.md`.
+
+### Phase E — Save Skills (15 min)
+14. Read `.claude/skills/t27-wave-loop.md`.
+15. Update it with any new W774 pattern (if any; expected: same pattern as W773, no new compiler behaviour).
+16. Save one-line memory pointer in `MEMORY.md` via `/experience-save`.
+
+## 4. Cooperation variants for next Wave Loop
+
+- **Variant A (recommended):** continue odd outer-dimension ladder with `[369][2]^6 Pt` (~0.721 MiBit, 23,616 elements, 755,712-bit packed vector). Zero compiler changes expected.
+- **Variant B:** keep `[367][2]^6 Pt` width but move the packed var to bench/function scope to exercise function-local non-power-of-two packed arrays.
+- **Variant C:** add conditional (`if`) guarded indexed signed field writes at current `[367][2]^6 Pt` width to exercise control-flow + packed-vector writes.
+
+## 5. Exit criteria
+
+- W774 witness parses, lowers, simulates, cocotb-matches, and seals.
+- All cargo suites green.
+- Closeout report written and committed with `Closes #<ISSUE>`.
+- `.trinity/experience.md` updated.
+- Skills file updated and memory pointer saved.
+- Worktree clean of stale W485 artefacts.

.claude/plans/loop-w775-full-cycle.md

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+# /loop Iteration Plan — W775 Closeout + Audit + Literature + Skills
+
+**Date:** 2026-07-24  
+**Branch:** `wave-loop-775` (to be created from `master` after PR #1484 lands)  
+**Issue:** TBD (next available GitHub issue)  
+**Anchor:** φ² + φ⁻² = 3 | TRINITY
+
+## 0. Prompt from user
+
+> исследуй слабые места работы, исследуй научные работы по теме, создай
+> декомпозированный план и реализуй все и в конце отчет и три варианта
+> сотрудничества для следующего Wave лупа! сохрани в конце скилы.
+
+## 1. Weak-point audit (done in this iteration)
+
+| Metric | Current | Previous (W774) | Verdict |
+|--------|---------|-----------------|---------|
+| 30-day commits | 68 | 66 | +2 |
+| Subject-line `Closes #N` / `Fixes #N` | 11 / 68 ≈ 16.2% | ~15.2% | **STABLE LOW** — links still mostly in body |
+| `.t27` specs without `test`/`invariant`/`bench` | 51 / 881 ≈ 5.8% | ~5.8% | **STABLE** |
+| `scripts/*.sh` on critical path | 19 | 19 | **STABLE** |
+| Open PR in flight | #1484 (W774) BLOCKED, no review | — | **WEAK POINT** — wave closeout blocked on external review |
+| Untracked worktree noise | `specs/scratch/w485_*.t27` × 3 + `wave-loop-485.md` | same | **WEAK POINT** — stale W485 artefacts |
+| `NOW.md` currency | last updated 2026-05-24 | same | **WEAK POINT** |
+| Pre-existing FPGA/formal CI failures | `sby` missing, Yosys Verilog-2005 static-cast in `build/fpga/generated/uart.v` | same | tracked as #1245, unrelated |
+
+**Top weak points to address:**
+1. **PR #1484 is BLOCKED** without review. Awaiting human merge to `master` before
+   `wave-loop-775` can branch cleanly.
+2. **L1 traceability remains low:** subject-line issue-link rate ~16%. Continue
+   putting `Closes #N` in subject lines for feat/merge/closeout commits.
+3. **Stale W485 artefacts and `NOW.md`** still untracked/stale.
+
+## 2. Literature scan (done in this iteration)
+
+### Ternary / MVL EDA and CPUs (2025–2026)
+- **REBEL-6** — 32-trit balanced ternary ISA with RV32I-to-REBEL (R2R) compiler
+  pipeline for C; 1.4% fewer instructions, 33.2% lower dynamic power vs. RV32I
+  (IEEE ISMVL 2025, [DOI 10.1109/ismvl64713.2025.00028](https://doi.org/10.1109/ismvl64713.2025.00028)).
+- **SONIC** — event-driven gate-level simulator for ternary VLSI using delta
+  cycles, automates REBEL-2 CPU verification, exports BCT Verilog for FPGA/ASIC
+  (IEEE ISMVL 2026, [DOI 10.1109/ismvl68998.2026.00042](https://doi.org/10.1109/ismvl68998.2026.00042);
+  [GitHub](https://github.com/sonbit/SimulationEngine)).
+- **TVHDL** — balanced-ternary extension to IEEE 1076-2008 VHDL, verified with
+  GHDL/GTKWave (IEEE ISMVL 2026, [DOI 10.1109/ismvl68998.2026.00041](https://doi.org/10.1109/ismvl68998.2026.00041)).
+- **KULeuven ternary-lut-dse** — Chisel generator for LUT-based ternary MatMul
+  targeting 1.58-bit LLMs, accepted IEEE ISPASS 2026
+  ([GitHub](https://github.com/KULeuven-MICAS/ternary-lut-dse)).
+- **VTX1** — open-source balanced-ternary SoC with CPU, memory/cache, UART/SPI/I2C/GPIO/DMA,
+  RTL-to-silicon flow using Icarus/Yosys, SkyWater 130nm tape-out planned
+  ([GitHub](https://github.com/itworks99/vtx1)).
+
+### SystemVerilog tooling gaps (2025–2026)
+- **Yosys** native `read_verilog -sv` still lists arrays of packed structs as
+  unsupported; PR #5143 (May 2025) fixed a global typedef packed-struct assertion
+  but did not add array-of-struct support
+  ([issue #4653](https://github.com/YosysHQ/yosys/issues/4653),
+  [issue #2677](https://github.com/YosysHQ/yosys/issues/2677)).
+- **Icarus Verilog** issue #1134 (2024–2025) shows assertion failures for
+  unpacked arrays of packed structs; packed arrays of simple packed structs can
+  work, but t27’s scalar packed-vector flattening avoids the construct entirely.
+  A Jan 2026 PR #1292 claims fixes for several open Icarus bugs.
+
+### Relevance to t27
+- t27’s scalar flattening to a single wide packed vector remains the correct
+  workaround for both Yosys and Icarus gaps with arrays of packed structs.
+- The REBEL/SONIC/TVHDL ecosystem confirms active research in native ternary ISA,
+  simulation, and HDL tooling, reinforcing the long-term value of t27’s
+  ternary-first language design.
+
+## 3. Decomposed implementation plan
+
+### Phase A — Housekeeping + branch setup (15 min)
+1. Note PR #1484 status (BLOCKED, awaiting review). Decide not to merge without
+   explicit authorization.
+2. Because PR #1484 is still open, create `wave-loop-775` as a local branch from
+   current `wave-loop-774` HEAD so W775 implementation can proceed in parallel
+   without blocking on the merge gate. (Alternatively, branch from `master` if PR
+   has landed by execution time.)
+3. Decide fate of stale W485 artefacts: leave untouched for a dedicated W485 issue.
+
+### Phase B — W775 Spec + Test (30 min)
+4. Generate `scripts/gen_w775.py` from `scripts/gen_w774.py` with `OUTER = 369`,
+   `MID_IDX = 184`.
+5. Run generator to produce `specs/scratch/w775_bench_module_369x2p6_aos_var_call_write.t27`.
+6. Manually fix f-string module header if needed.
+7. Add integration test `accepts_w775_bench_module_369x2p6_aos_var_call_write` to
+   `bootstrap/tests/icarus_lowerable.rs`.
+
+### Phase C — Build + Seal + Verify (45 min)
+8. `cd bootstrap && cargo build --release -p t27c`.
+9. `t27c parse`, `icarus-lowerable`, `icarus-simulate` (expected 17 cycles),
+   `icarus-cocotb` on the W775 witness.
+10. `t27c seal --save` the witness; confirm `FROZEN_HASH` unchanged.
+11. `cargo test -p t27c --bin t27c`, `cargo test -p tri`,
+    `cargo test -p t27c --test icarus_lowerable`.
+
+### Phase D — Closeout + Cooperation Variants (30 min)
+12. Write `docs/reports/FPGA_LOOP_CLOSEOUT_W775_2026-07-24.md` with audit,
+    literature, validation, and three W776 cooperation variants.
+13. Append W775 learnings to `.trinity/experience.md`.
+14. Update `.trinity/current-issue.md` for W775 (issue TBD until GitHub assigns).
+
+### Phase E — Save Skills + Memory (15 min)
+15. Append W775 worked example to `.claude/skills/t27-wave-loop.md`.
+16. Save memory file `wave-loop-775.md` and pointer in `MEMORY.md`.
+
+## 4. Cooperation variants for Wave Loop 776
+
+- **Variant A (recommended):** continue odd outer-dimension ladder with
+  `[371][2]^6 Pt` (~0.725 MiBit, 23,744 elements, 759,808-bit packed vector).
+  Zero compiler changes expected.
+- **Variant B:** keep `[369][2]^6 Pt` width but move the packed var to bench/function
+  scope to exercise function-local non-power-of-two packed arrays.
+- **Variant C:** add conditional (`if`) guarded indexed signed field writes at the
+  current `[369][2]^6 Pt` width to exercise control-flow + packed-vector writes.
+
+## 5. Exit criteria
+
+- W775 witness parses, lowers, simulates, cocotb-matches, and seals.
+- All cargo suites green.
+- Closeout report written.
+- `.trinity/experience.md` updated.
+- Skills and memory saved.
+- PR #1484 noted as pending merge blocker; W775 branch prepared independently.

.claude/plans/loop-w776-full-cycle.md

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+# Wave Loop 776 — Full-cycle decomposed plan
+
+## Charter
+Investigate repository weak points, research scientific literature, create a
+decomposed plan, implement Wave Loop 776, write a closeout report with three
+cooperation variants for Wave Loop 777, and save skills / experience.
+
+## 1. Weak-point audit
+- [x] Branch / worktree hygiene: `wave-loop-775` is current; W774 PR #1484 and
+  W775 PR #1486 are open awaiting review, so W776 will branch from
+  `wave-loop-775` HEAD to avoid blocking.
+- [x] Traceability: 13 of 69 recent 30-day commit subjects carry
+  `Closes #N`/`Fixes #N`/`Refs #N` (~18.8%). Subjects remain low, but
+  closeout bodies still contain issue links.
+- [x] Testability: 57 of 882 `.t27` specs lack `test`/`invariant`/`bench`
+  (~6.5%). This is within the historical band but should be tracked.
+- [x] UNITY: 19 `*.sh` scripts remain under `scripts/`. No new shell scripts
+  will be added on the W776 critical path.
+- [x] Worktree needles: untracked W485 scratch artifacts
+  (`w485_bench_local_array_hoist.t27`, `w485_host_helper_shadow.t27`,
+  `w485_wildcard_binding.t27`) and stale `.claude/plans/w485*` remain
+  uncommitted and unrelated to the wave ladder.
+- [x] CI weak points: pre-existing Yosys/Icarus FPGA synthesis formal failures
+  (`sby` pip package missing, Yosys static-cast Verilog-2005 limitation in
+  `build/fpga/generated/uart.v`) are unchanged and out of scope for this wave.
+
+## 2. Literature scan (2025-2026)
+- SystemVerilog packed array / struct semantics: IEEE 1800-2017 7.4.1/7.4.3
+  confirm packed width is the product of dimensions, with no power-of-two
+  restriction. AMD UG901 2026.1 lists packed arrays and packed structs as
+  supported in Vivado synthesis/simulation.
+- Tool gaps: Yosys 0.65-dev docs still note that arrays of packed structs/unions
+  are not supported (YosysHQ/yosys#2677, #2908, #5837). t27's scalar
+  packed-vector flattening avoids the unsupported construct entirely.
+- Ternary/MVL ecosystem (IEEE ISMVL 2025/2026):
+  - REBEL-6 — 32-trit balanced ternary ISA with RV32I-to-REBEL C compiler.
+  - SONIC — event-driven gate-level ternary VLSI simulator with delta cycles.
+  - TVHDL — balanced ternary extension to IEEE 1076-2008 VHDL.
+  - VTX1 — open-source balanced-ternary SoC with Icarus/Yosys RTL-to-silicon flow.
+
+## 3. Implementation plan
+- Create `wave-loop-776` from `wave-loop-775` HEAD.
+- Copy `scripts/gen_w775.py` to `scripts/gen_w776.py`.
+- Update constants: `OUTER = 371`, `MID_IDX = 185`.
+- Update module name prefix to `w776_bench_module_371x2p6_aos_var_call_write`.
+- Run generator to produce
+  `specs/scratch/w776_bench_module_371x2p6_aos_var_call_write.t27`.
+- Add integration test `accepts_w776_bench_module_371x2p6_aos_var_call_write`
+  in `bootstrap/tests/icarus_lowerable.rs` after the W775 test.
+- Build `cargo build --release -p t27c`.
+- Seal the witness with `t27c seal --save`.
+- Verify: `parse`, `icarus-lowerable`, `icarus-simulate` (17 cycles),
+  `icarus-cocotb`.
+- Run cargo suites: `cargo test -p t27c --bin t27c`, `cargo test -p tri`,
+  `cargo test -p t27c --test icarus_lowerable`.
+- Create GitHub issue for W776.
+- Commit with `Closes #<issue>`.
+- Push `wave-loop-776` and open PR.
+
+## 4. Closeout / learning
+- Write `docs/reports/FPGA_LOOP_CLOSEOUT_W776_2026-07-24.md`.
+- Write `.claude/plans/wave-loop-777.md` with three cooperation variants.
+- Update `.trinity/experience.md`, `.claude/skills/t27-wave-loop.md`,
+  `.trinity/current-issue.md`, and `docs/NOW.md`.
+- Save memory file `wave-loop-776.md` and prepend pointer in `MEMORY.md`.
+
+## 5. Cooperation variants for Wave Loop 777
+- **Variant A (recommended):** continue the odd outer-dimension ladder with
+  `[373][2]^6 Pt` (~0.725 MiBit).
+- **Variant B:** keep width at ~0.723 MiBit but move the packed var to
+  bench/function scope at `[371][2]^6 Pt`.
+- **Variant C:** add `if`-guarded indexed signed field writes at the current
+  `[371][2]^6 Pt` width.