bit concatenation operator {a, b, ...} for Verilog bus composition (R-CG-4) #823

Problem

No way to express Verilog-style bit concatenation {hi, lo} in t27 source. This is the mirror of bit-range extraction — users can decompose buses (with W54 bit-range) but cannot recompose them.

Solution

New ExprConcat node kind: {a, b, c} parses as concatenation with N children.

• Verilog: emits {a, b, c} (native Verilog concatenation)
• C/Rust: emits /* concat(a, b, c) */ 0 (software backends need width info for proper shift+or; deferred to type inference wave)
• Supports nested concatenation: {{a, b}, c}

11 new tests. All pass.