Nine specs whose tests do not compile (blocked) cannot be sealed #7641

Goal

Nine specs added by merged PRs do not get a seal that proves anything, because their tests do not compile with Zig 0.16.0 (t27c seal records blocked). Each needs its generated test code to compile so that the seal can record passed == total > 0.

Success Criteria

Each spec either compiles under t27c test-report and is sealed with passed == total > 0, or the issue names the compiler defect it is blocked on. Why it matters: the Queen map counts a closed issue as covered only when its specs carry such a seal.

Scope note

Spec or generator fixes only; no gate changes.

User Scenarios

• Given nine specs whose generated test code fails to compile under Zig 0.16.0, When t27c seal is run on each spec, Then the seal records blocked instead of passed == total > 0

Requirements

• FR-001: Each of the nine cited specs MUST have its generated test code compile under Zig 0.16.0 via t27c test-report
• FR-002: Each spec MUST achieve passed == total > 0 when sealed via t27c seal
• FR-003: Fixes MUST be limited to spec or generator changes; no gate changes

Success Criteria

• t27c test-report specs/compiler/rust_repeat_counts.t27 compiles and t27c seal specs/compiler/rust_repeat_counts.t27 exits 0 with passed == total > 0
• t27c test-report specs/port/fpga/verilog/mvp_ternary_classifier_jtag_noport.t27 compiles and t27c seal specs/port/fpga/verilog/mvp_ternary_classifier_jtag_noport.t27 exits 0 with passed == total > 0
• t27c test-report specs/port/fpga/vivado/gf16_matmul_top.t27 compiles and t27c seal specs/port/fpga/vivado/gf16_matmul_top.t27 exits 0 with passed == total > 0
• t27c test-report specs/port/tools/check_conflict_markers.t27 compiles and t27c seal specs/port/tools/check_conflict_markers.t27 exits 0 with passed == total > 0
• t27c test-report specs/port/tools/jtag/link_relay.t27 compiles and t27c seal specs/port/tools/jtag/link_relay.t27 exits 0 with passed == total > 0
• t27c test-report specs/port/tools/jtag/mpsse_jtag.t27 compiles and t27c seal specs/port/tools/jtag/mpsse_jtag.t27 exits 0 with passed == total > 0
• t27c test-report specs/port/tools/jtag/read_user1.t27 compiles and t27c seal specs/port/tools/jtag/read_user1.t27 exits 0 with passed == total > 0
• t27c test-report specs/port/tools/jtag/read_verdict.t27 compiles and t27c seal specs/port/tools/jtag/read_verdict.t27 exits 0 with passed == total > 0
• t27c test-report specs/ui/viewport.t27 compiles and t27c seal specs/ui/viewport.t27 exits 0 with passed == total > 0

Boundary

• specs/compiler/rust_repeat_counts.t27
• specs/port/fpga/verilog/mvp_ternary_classifier_jtag_noport.t27
• specs/port/fpga/vivado/gf16_matmul_top.t27
• specs/port/tools/check_conflict_markers.t27
• specs/port/tools/jtag/link_relay.t27
• specs/port/tools/jtag/mpsse_jtag.t27
• specs/port/tools/jtag/read_user1.t27
• specs/port/tools/jtag/read_verdict.t27
• specs/ui/viewport.t27