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Wave Loop 408 — real CCLK measurement on P12 + complete SPI transaction model in Lean 4 #1318
Wave Loop 408 should close the remaining gap between the synthetic CCLK fixture and the physical board by capturing a real CCLK measurement on pin P12, and strengthen the formal argument with a complete SPI flash read-transaction model in Lean 4.
Background
W407 extended proofs/lean4/Trinity/TernaryFPGABoot.lean with static N25Q128_3V timing constants and a flash_spi_timing_ok predicate, and added tri fpga measure-cclk --synth so the measurement pipeline runs in CI without a wired probe (PR #1317). The real silicon anchor and a transaction-level proof are still missing.
Goals
Variant A — Real CCLK measurement on P12
Wire P12 (CCLK) → ADBUS4 and GND → GND on the Digilent FTDI cable (or use DSLogic/scope).
Run the canonical cold-POR protocol and capture the first ~1 ms after POR:
fpga/HARDWARE_SSOT.md contains the measured frequency and duty cycle.
tri fpga measure-cclk --live ... --validate passes on real hardware.
lake build Trinity.TernaryFPGABoot passes with the new transaction lemmas.
./scripts/tri test passes.
W408 report + three W409 cooperation variants committed.
Cooperation fallback
If P12 cannot be wired in W408, fall back to Variant C alone (formal transaction model). If CI automation is the priority, pick Variant B (relay-controlled cold-POR) in W409.
Activity
docs(w408): add W408 entry to NOW.md and experience log
feat(igla): Wave Loop 408 — real P12 CCLK attempt + SPI transaction m…
gHashTag commentedon Jul 4, 2026
Resolved: wave-loop work was merged to master through subsequent direct-to-master wave-loop PRs (W411-W414). Closing as hygiene cleanup.