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dts: jh7100: Fixing boot hang caused by booting from e24 instead of u74 #15

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dts: jh7100: Fixing boot hang caused by booting from e24 instead of u74 #15

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38 changes: 25 additions & 13 deletions arch/riscv/boot/dts/starfive/jh7100.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -11,6 +11,18 @@
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "sifive,e24", "riscv";
device_type = "cpu";
reg = <0>;
riscv,isa = "rv32imafbc";
status = "disabled";
cpu0_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu@1 {
compatible = "sifive,u74-mc", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
Expand All @@ -25,19 +37,19 @@
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
next-level-cache = <&ccache>;
reg = <0>;
reg = <1>;
riscv,isa = "rv64imafdc";
starfive,itim = <&itim0>;
status = "okay";
tlb-split;
cpu0_intc: interrupt-controller {
cpu1_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};

cpu@1 {
cpu@2 {
compatible = "sifive,u74-mc", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
Expand All @@ -52,12 +64,12 @@
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
next-level-cache = <&ccache>;
reg = <1>;
reg = <2>;
riscv,isa = "rv64imafdc";
starfive,itim = <&itim1>;
status = "okay";
tlb-split;
cpu1_intc: interrupt-controller {
cpu2_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
Expand Down Expand Up @@ -223,10 +235,10 @@
clint: clint@2000000 {
#interrupt-cells = <1>;
compatible = "riscv,clint0";
interrupts-extended = <&cpu0_intc 3>,
<&cpu0_intc 7>,
<&cpu1_intc 3>,
<&cpu1_intc 7>;
interrupts-extended = <&cpu1_intc 3>,
<&cpu1_intc 7>,
<&cpu2_intc 3>,
<&cpu2_intc 7>;
reg = <0x0 0x2000000 0x0 0x10000>;
reg-names = "control";
};
Expand All @@ -235,10 +247,10 @@
#interrupt-cells = <1>;
compatible = "riscv,plic0";
interrupt-controller;
interrupts-extended = <&cpu0_intc 11>,
<&cpu0_intc 9>,
<&cpu1_intc 11>,
<&cpu1_intc 9>;
interrupts-extended = <&cpu1_intc 11>,
<&cpu1_intc 9>,
<&cpu2_intc 11>,
<&cpu2_intc 9>;
reg = <0x0 0xc000000 0x0 0x4000000>;
reg-names = "control";
riscv,max-priority = <7>;
Expand Down