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Add SVE AES APIs #130859

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0a139c5
Add SVE AES APIs
a74nh Jun 30, 2026
27b2236
Rename polynomial to upper/lower
a74nh Jul 30, 2026
1391509
Use the AES versions of PolynomialMultiplyWidening
a74nh Jul 30, 2026
0d90e41
Add api compat
a74nh Jul 30, 2026
2832e6e
rename back to Even/Odd
a74nh Aug 3, 2026
f80e222
Revert "Add api compat"
a74nh Aug 3, 2026
b4849ac
use special codegen for PolynomialMultiplyWidening
a74nh Aug 3, 2026
1992af2
Move PolynomialMultiplyWidening to SvePmull128
a74nh Aug 3, 2026
c37eb3a
merge main
a74nh Aug 3, 2026
8d8a52b
fix SvePmull128 instruction set id
a74nh Aug 3, 2026
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1 change: 1 addition & 0 deletions src/coreclr/inc/clrconfigvalues.h
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Original file line number Diff line number Diff line change
Expand Up @@ -712,6 +712,7 @@ RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64Sve2, W("EnableArm64Sv
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64Sha3, W("EnableArm64Sha3"), 1, "Allows Arm64 Sha3+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64Sm4, W("EnableArm64Sm4"), 1, "Allows Arm64 Sm4+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64SveAes, W("EnableArm64SveAes"), 1, "Allows Arm64 SveAes+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64SvePmull128, W("EnableArm64SvePmull128"), 1, "Allows Arm64 SvePmull128+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64SveSha3, W("EnableArm64SveSha3"), 1, "Allows Arm64 SveSha3+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64SveSm4, W("EnableArm64SveSm4"), 1, "Allows Arm64 SveSm4+ hardware intrinsics to be disabled")
#elif defined(TARGET_RISCV64)
Expand Down
51 changes: 33 additions & 18 deletions src/coreclr/inc/corinfoinstructionset.h
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Expand Up @@ -38,24 +38,26 @@ enum CORINFO_InstructionSet
InstructionSet_Sha3=19,
InstructionSet_Sm4=20,
InstructionSet_SveAes=21,
InstructionSet_SveSha3=22,
InstructionSet_SveSm4=23,
InstructionSet_Cssc=24,
InstructionSet_ArmBase_Arm64=25,
InstructionSet_AdvSimd_Arm64=26,
InstructionSet_Aes_Arm64=27,
InstructionSet_Crc32_Arm64=28,
InstructionSet_Dp_Arm64=29,
InstructionSet_Rdm_Arm64=30,
InstructionSet_Sha1_Arm64=31,
InstructionSet_Sha256_Arm64=32,
InstructionSet_Sve_Arm64=33,
InstructionSet_Sve2_Arm64=34,
InstructionSet_Sha3_Arm64=35,
InstructionSet_Sm4_Arm64=36,
InstructionSet_SveAes_Arm64=37,
InstructionSet_SveSha3_Arm64=38,
InstructionSet_SveSm4_Arm64=39,
InstructionSet_SvePmull128=22,
InstructionSet_SveSha3=23,
InstructionSet_SveSm4=24,
InstructionSet_Cssc=25,
InstructionSet_ArmBase_Arm64=26,
InstructionSet_AdvSimd_Arm64=27,
InstructionSet_Aes_Arm64=28,
InstructionSet_Crc32_Arm64=29,
InstructionSet_Dp_Arm64=30,
InstructionSet_Rdm_Arm64=31,
InstructionSet_Sha1_Arm64=32,
InstructionSet_Sha256_Arm64=33,
InstructionSet_Sve_Arm64=34,
InstructionSet_Sve2_Arm64=35,
InstructionSet_Sha3_Arm64=36,
InstructionSet_Sm4_Arm64=37,
InstructionSet_SveAes_Arm64=38,
InstructionSet_SvePmull128_Arm64=39,
InstructionSet_SveSha3_Arm64=40,
InstructionSet_SveSm4_Arm64=41,
#endif // TARGET_ARM64
#ifdef TARGET_RISCV64
InstructionSet_RiscV64Base=1,
Expand Down Expand Up @@ -285,6 +287,8 @@ struct CORINFO_InstructionSetFlags
AddInstructionSet(InstructionSet_Sm4_Arm64);
if (HasInstructionSet(InstructionSet_SveAes))
AddInstructionSet(InstructionSet_SveAes_Arm64);
if (HasInstructionSet(InstructionSet_SvePmull128))
AddInstructionSet(InstructionSet_SvePmull128_Arm64);
if (HasInstructionSet(InstructionSet_SveSha3))
AddInstructionSet(InstructionSet_SveSha3_Arm64);
if (HasInstructionSet(InstructionSet_SveSm4))
Expand Down Expand Up @@ -399,6 +403,10 @@ inline CORINFO_InstructionSetFlags EnsureInstructionSetFlagsAreValid(CORINFO_Ins
resultflags.RemoveInstructionSet(InstructionSet_SveAes);
if (resultflags.HasInstructionSet(InstructionSet_SveAes_Arm64) && !resultflags.HasInstructionSet(InstructionSet_SveAes))
resultflags.RemoveInstructionSet(InstructionSet_SveAes_Arm64);
if (resultflags.HasInstructionSet(InstructionSet_SvePmull128) && !resultflags.HasInstructionSet(InstructionSet_SvePmull128_Arm64))
resultflags.RemoveInstructionSet(InstructionSet_SvePmull128);
if (resultflags.HasInstructionSet(InstructionSet_SvePmull128_Arm64) && !resultflags.HasInstructionSet(InstructionSet_SvePmull128))
resultflags.RemoveInstructionSet(InstructionSet_SvePmull128_Arm64);
if (resultflags.HasInstructionSet(InstructionSet_SveSha3) && !resultflags.HasInstructionSet(InstructionSet_SveSha3_Arm64))
resultflags.RemoveInstructionSet(InstructionSet_SveSha3);
if (resultflags.HasInstructionSet(InstructionSet_SveSha3_Arm64) && !resultflags.HasInstructionSet(InstructionSet_SveSha3))
Expand Down Expand Up @@ -441,6 +449,8 @@ inline CORINFO_InstructionSetFlags EnsureInstructionSetFlagsAreValid(CORINFO_Ins
resultflags.RemoveInstructionSet(InstructionSet_SveAes);
if (resultflags.HasInstructionSet(InstructionSet_SveAes) && !resultflags.HasInstructionSet(InstructionSet_Aes))
resultflags.RemoveInstructionSet(InstructionSet_SveAes);
if (resultflags.HasInstructionSet(InstructionSet_SvePmull128) && !resultflags.HasInstructionSet(InstructionSet_Sve))
resultflags.RemoveInstructionSet(InstructionSet_SvePmull128);
if (resultflags.HasInstructionSet(InstructionSet_SveSha3) && !resultflags.HasInstructionSet(InstructionSet_Sve))
resultflags.RemoveInstructionSet(InstructionSet_SveSha3);
if (resultflags.HasInstructionSet(InstructionSet_SveSha3) && !resultflags.HasInstructionSet(InstructionSet_Sha3))
Expand Down Expand Up @@ -741,6 +751,10 @@ inline const char *InstructionSetToString(CORINFO_InstructionSet instructionSet)
return "SveAes";
case InstructionSet_SveAes_Arm64 :
return "SveAes_Arm64";
case InstructionSet_SvePmull128 :
return "SvePmull128";
case InstructionSet_SvePmull128_Arm64 :
return "SvePmull128_Arm64";
case InstructionSet_SveSha3 :
return "SveSha3";
case InstructionSet_SveSha3_Arm64 :
Expand Down Expand Up @@ -964,6 +978,7 @@ inline CORINFO_InstructionSet InstructionSetFromR2RInstructionSet(ReadyToRunInst
case READYTORUN_INSTRUCTION_Sha3: return InstructionSet_Sha3;
case READYTORUN_INSTRUCTION_Sm4: return InstructionSet_Sm4;
case READYTORUN_INSTRUCTION_SveAes: return InstructionSet_SveAes;
case READYTORUN_INSTRUCTION_SvePmull128: return InstructionSet_SvePmull128;
case READYTORUN_INSTRUCTION_SveSha3: return InstructionSet_SveSha3;
case READYTORUN_INSTRUCTION_SveSm4: return InstructionSet_SveSm4;
case READYTORUN_INSTRUCTION_Cssc: return InstructionSet_Cssc;
Expand Down
10 changes: 5 additions & 5 deletions src/coreclr/inc/jiteeversionguid.h
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Expand Up @@ -37,11 +37,11 @@

#include <minipal/guid.h>

constexpr GUID JITEEVersionIdentifier = { /* 134b051a-e1ec-4f52-a1bf-f919908aa33c */
0x134b051a,
0xe1ec,
0x4f52,
{0xa1, 0xbf, 0xf9, 0x19, 0x90, 0x8a, 0xa3, 0x3c}
constexpr GUID JITEEVersionIdentifier = { /* 1af70442-f072-4066-a1c4-6ed018bd9498 */
0x1af70442,
0xf072,
0x4066,
{0xa1, 0xc4, 0x6e, 0xd0, 0x18, 0xbd, 0x94, 0x98}
};

#endif // JIT_EE_VERSIONING_GUID_H
2 changes: 2 additions & 0 deletions src/coreclr/inc/readytoruninstructionset.h
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Expand Up @@ -102,6 +102,8 @@ enum ReadyToRunInstructionSet
READYTORUN_INSTRUCTION_PackedSimd=92,
READYTORUN_INSTRUCTION_Cssc=93,
READYTORUN_INSTRUCTION_Zicond=94,
READYTORUN_INSTRUCTION_SvePmull128=95,

};

#endif // READYTORUNINSTRUCTIONSET_H
5 changes: 5 additions & 0 deletions src/coreclr/jit/compiler.cpp
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Expand Up @@ -6082,6 +6082,11 @@ int Compiler::compCompileAfterInit(CORINFO_MODULE_HANDLE classPtr,
instructionSetFlags.AddInstructionSet(InstructionSet_SveAes);
}

if (JitConfig.EnableArm64SvePmull128() != 0)
{
instructionSetFlags.AddInstructionSet(InstructionSet_SvePmull128);
}

if (JitConfig.EnableArm64SveSha3() != 0)
{
instructionSetFlags.AddInstructionSet(InstructionSet_SveSha3);
Expand Down
13 changes: 13 additions & 0 deletions src/coreclr/jit/emitarm64sve.cpp
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Expand Up @@ -2322,6 +2322,17 @@ void emitter::emitInsSve_R_R(instruction ins,
fmt = IF_SVE_BI_2A;
break;

case INS_sve_aesimc:
case INS_sve_aesmc:
assert(insScalableOptsNone(sopt));
assert(insOptsNone(opt) || (opt == INS_OPTS_SCALABLE_B));
assert(isVectorRegister(reg1));
assert(isVectorRegister(reg2));
assert(isScalableVectorSize(size));
emitInsSve_Mov(INS_sve_mov, EA_SCALABLE, reg1, reg2, /* canSkip */ true, INS_OPTS_SCALABLE_B);
emitInsSve_R(ins, attr, reg1, opt);
return;

case INS_sve_fmov:
assert(insOptsScalableAtLeastHalf(opt));
assert(isVectorRegister(reg1)); // ddddd
Expand Down Expand Up @@ -3016,6 +3027,8 @@ void emitter::emitInsSve_R_R_R(instruction ins,
emitInsSve_R_R(ins, attr, reg1, reg3, opt, sopt);
return;

case INS_sve_aesd:
case INS_sve_aese:
case INS_sve_sm4e:
case INS_sve_sqxtnt:
case INS_sve_uqxtnt:
Expand Down
4 changes: 3 additions & 1 deletion src/coreclr/jit/hwintrinsic.cpp
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Expand Up @@ -994,7 +994,8 @@ static const HWIntrinsicIsaRange hwintrinsicIsaRangeArray[] = {
{ FIRST_NI_Sve2, LAST_NI_Sve2 }, // Sve2
{ FIRST_NI_Sha3, LAST_NI_Sha3 }, // Sha3
{ FIRST_NI_Sm4, LAST_NI_Sm4 }, // Sm4
{ NI_Illegal, NI_Illegal }, // SveAes
{ FIRST_NI_SveAes, LAST_NI_SveAes }, // SveAes
{ FIRST_NI_SvePmull128, LAST_NI_SvePmull128 }, // SvePmull128
{ FIRST_NI_SveSha3, LAST_NI_SveSha3 }, // SveSha3
{ FIRST_NI_SveSm4, LAST_NI_SveSm4 }, // SveSm4
{ NI_Illegal, NI_Illegal }, // Cssc
Expand All @@ -1011,6 +1012,7 @@ static const HWIntrinsicIsaRange hwintrinsicIsaRangeArray[] = {
{ NI_Illegal, NI_Illegal }, // Sha3_Arm64
{ NI_Illegal, NI_Illegal }, // Sm4_Arm64
{ NI_Illegal, NI_Illegal }, // SveAes_Arm64
{ NI_Illegal, NI_Illegal }, // SvePmull128_Arm64
{ NI_Illegal, NI_Illegal }, // SveSha3_Arm64
{ NI_Illegal, NI_Illegal }, // SveSm4_Arm64
#elif defined(TARGET_WASM)
Expand Down
6 changes: 6 additions & 0 deletions src/coreclr/jit/hwintrinsicarm64.cpp
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Expand Up @@ -48,6 +48,8 @@ static CORINFO_InstructionSet Arm64VersionOfIsa(CORINFO_InstructionSet isa)
return InstructionSet_SveSha3_Arm64;
case InstructionSet_SveSm4:
return InstructionSet_SveSm4_Arm64;
case InstructionSet_SvePmull128:
return InstructionSet_SvePmull128_Arm64;
default:
return InstructionSet_NONE;
}
Expand Down Expand Up @@ -131,6 +133,10 @@ CORINFO_InstructionSet Compiler::lookupInstructionSet(const char* className)
{
return InstructionSet_SveAes;
}
if (strcmp(className, "SvePmull128") == 0)
{
return InstructionSet_SvePmull128;
}
if (strcmp(className, "SveSha3") == 0)
{
return InstructionSet_SveSha3;
Expand Down
8 changes: 8 additions & 0 deletions src/coreclr/jit/hwintrinsiccodegenarm64.cpp
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Expand Up @@ -3117,6 +3117,14 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
break;
}

case NI_SvePmull128_PolynomialMultiplyWideningEven:
case NI_SvePmull128_PolynomialMultiplyWideningOdd:
{
opt = INS_OPTS_SCALABLE_Q;
GetEmitter()->emitInsSve_R_R_R(ins, emitSize, targetReg, op1Reg, op2Reg, opt);
break;
}

case NI_SveSha3_BitwiseRotateLeftBy1AndXor:
{
opt = INS_OPTS_SCALABLE_D;
Expand Down
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