Fix checks to accommodate register wraparounds in multi-reg ops by SwapnilGaikwad · Pull Request #101430 · dotnet/runtime

SwapnilGaikwad · 2024-04-23T14:14:17Z

Fixes issue #101070

Fixes issue dotnet#101070

dotnet-policy-service · 2024-04-23T14:14:44Z

Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch
See info in area-owners.md if you want to be subscribed.

SwapnilGaikwad · 2024-04-23T14:18:45Z

@a74nh @kunalspathak @dotnet/arm64-contrib

a74nh

I'm happy with this.

amanasifkhalid

LGTM assuming CI passes. Thanks!

kunalspathak

LGTM. Thanks!

kunalspathak · 2024-04-23T16:32:38Z

@SwapnilGaikwad - did we end up assigning V31 here? I never found a case where we would have to wrap around. Do you mind pasting the codegen for the faulting method?

SwapnilGaikwad · 2024-04-24T10:22:34Z

@SwapnilGaikwad - did we end up assigning V31 here? I never found a case where we would have to wrap around. Do you mind pasting the codegen for the faulting method?

Yup, we are using more local variables in DecodeFromUtf8 and we use multiple instructions with requiring three or four consecutive registers. This seems to have led to higher register pressure.

The 'genGenerateCode' phase from the JIT dump

*************** In genGenerateCode()

---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   IBC [IL range]   [jump]                            [EH region]        [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1        [000..009)-> BB03(0.5),BB02(0.5)     ( cond )                     i LIR
BB02 [0001]  1       BB01                  0.50     [009..011)-> BB60(1)                 (always)                     i LIR hascall
BB03 [0002]  1       BB01                  0.50  50 [011..03F)-> BB05(0.5),BB04(0.5)     ( cond )                     i LIR IBC
BB04 [0067]  1       BB03                  0      0 [03E..03F)                           (throw )                     i LIR IBC rare hascall gcsafe
BB05 [0068]  1       BB03                  0.50  50 [03E..04F)-> BB07(0.5),BB06(0.5)     ( cond )                     i LIR IBC
BB06 [0003]  1       BB05                  0.50     [04F..057)-> BB07(1)                 (always)                     i LIR hascall
BB07 [0004]  2       BB05,BB06             0.50     [057..074)-> BB20(0.5),BB08(0.5)     ( cond )                     i LIR
BB08 [0005]  1       BB07                  0.50     [074..09C)-> BB25(0.5),BB09(0.5)     ( cond )                     i LIR
BB09 [0009]  1       BB08                  0.50     [09C..0AD)-> BB10(1)                 (always)                     i LIR
BB10 [0071]  2       BB09,BB72             4        [09C..09D)-> BB12(0.5),BB11(0.5)     ( cond )                     i LIR loophead hascall gcsafe bwd bwd-target
BB11 [0072]  1       BB10                  4        [09C..09D)-> BB72(0.5),BB71(0.5)     ( cond )                     i LIR hascall gcsafe bwd bwd-src
BB71 [0159]  1       BB11                  2        [???..???)-> BB12(1)                 (always)                     LIR internal
BB12 [0073]  2       BB10,BB71             0.50     [09C..0B6)-> BB24(0.5),BB13(0.5)     ( cond )                     i LIR
BB13 [0048]  1       BB12                  0.25     [???..???)-> BB14(1)                 (always)                     i LIR internal hascall
BB14 [0010]  2       BB13,BB25             0.50     [0B6..0D2)-> BB23(0.5),BB15(0.5)     ( cond )                     i LIR
BB15 [0012]  1       BB14                  0.50     [0D2..0E3)-> BB16(1)                 (always)                     i LIR hascall gcsafe
BB16 [0082]  2       BB15,BB74             4    400 [0D2..0D3)-> BB18(0.5),BB17(0.5)     ( cond )                     i LIR IBC loophead hascall gcsafe bwd bwd-target
BB17 [0083]  1       BB16                  4    400 [0D2..0D3)-> BB74(0.5),BB73(0.5)     ( cond )                     i LIR IBC hascall gcsafe bwd
BB73 [0161]  1       BB17                  2    200 [???..???)-> BB18(1)                 (always)                     LIR IBC internal
BB18 [0086]  2       BB16,BB73             0.50     [0D2..0EC)-> BB22(0.5),BB19(0.5)     ( cond )                     i LIR
BB19 [0051]  1       BB18                  0.25     [???..???)-> BB20(1)                 (always)                     i LIR internal hascall
BB20 [0013]  3       BB07,BB19,BB23        0.50     [0EC..0F0)-> BB26(0.5),BB21(0.5)     ( cond )                     i LIR
BB21 [0014]  1       BB20                  0.50     [0F0..0F3)-> BB27(1)                 (always)                     i LIR
BB74 [0162]  1       BB17                  2    200 [???..???)-> BB16(1)                 (always)                     LIR IBC internal bwd
BB72 [0160]  1       BB11                  2        [???..???)-> BB10(1)                 (always)                     LIR internal bwd
BB22 [0052]  1       BB18                  0.25     [???..???)-> BB59(1)                 (always)                     i LIR internal hascall
BB23 [0050]  1       BB14                  0.25     [???..???)-> BB20(1)                 (always)                     i LIR internal hascall
BB24 [0049]  1       BB12                  0.25     [???..???)-> BB59(1)                 (always)                     i LIR internal hascall
BB25 [0047]  1       BB08                  0.25     [???..???)-> BB14(1)                 (always)                     i LIR internal hascall
BB26 [0015]  1       BB20                  0.50     [0F3..0F4)-> BB27(1)                 (always)                     i LIR hascall
BB27 [0016]  2       BB21,BB26             0.50     [0F4..0FC)-> BB29(0.5),BB28(0.5)     ( cond )                     i LIR
BB28 [0017]  1       BB27                  0.50     [0FC..105)-> BB30(1)                 (always)                     i LIR
BB29 [0018]  1       BB27                  0.50     [105..11B)-> BB30(1)                 (always)                     i LIR hascall gcsafe
BB30 [0019]  2       BB28,BB29             0.50  50 [11B..12F)-> BB75(0.5),BB31(0.5)     ( cond )                     i LIR IBC
BB31 [0157]  2       BB30,BB76             4    400 [12F..142)-> BB41(0.5),BB33(0.5)     ( cond )                     i LIR IBC bwd
BB33 [0021]  1       BB31                  4        [142..15D)-> BB76(0.5),BB34(0.5)     ( cond )                     i LIR hascall bwd
BB34 [0158]  2       BB33,BB75             0.50     [15D..169)-> BB64(0.5),BB36(0.5)     ( cond )                     i LIR
BB36 [0024]  1       BB34                  0.50     [169..16F)-> BB42(0.5),BB37(0.5)     ( cond )                     i LIR
BB37 [0025]  1       BB36                  0.50     [16F..176)-> BB40(0.5),BB38(0.5)     ( cond )                     i LIR
BB38 [0026]  1       BB37                  0.50     [176..186)-> BB59(0.5),BB39(0.5)     ( cond )                     i LIR
BB39 [0043]  1       BB38                  0.50     [2EF..305)-> BB66(1)                 (always)                     i LIR hascall
BB76 [0164]  1       BB33                  2        [???..???)-> BB31(1)                 (always)                     LIR internal bwd
BB75 [0163]  1       BB30                  0.25  25 [???..???)-> BB34(1)                 (always)                     LIR IBC internal
BB40 [0054]  1       BB37                  0.25     [???..???)-> BB67(1)                 (always)                     i LIR internal hascall
BB41 [0053]  1       BB31                  0.25     [???..???)-> BB67(1)                 (always)                     i LIR internal hascall
BB42 [0028]  1       BB36                  0.50     [18B..1E6)-> BB48(0.5),BB43(0.5)     ( cond )                     i LIR
BB43 [0029]  1       BB42                  0.50     [1E6..21C)-> BB47(0.5),BB44(0.5)     ( cond )                     i LIR
BB44 [0030]  1       BB43                  0.50     [21C..227)-> BB46(0.5),BB45(0.5)     ( cond )                     i LIR
BB45 [0031]  1       BB44                  0.50     [227..238)-> BB57(1)                 (always)                     i LIR
BB46 [0056]  1       BB44                  0.25     [???..???)-> BB64(1)                 (always)                     i LIR internal hascall
BB47 [0055]  1       BB43                  0.25     [???..???)-> BB67(1)                 (always)                     i LIR internal hascall
BB48 [0032]  1       BB42                  0.50     [238..23E)-> BB54(0.5),BB49(0.5)     ( cond )                     i LIR
BB49 [0033]  1       BB48                  0.50     [23E..260)-> BB53(0.5),BB50(0.5)     ( cond )                     i LIR
BB50 [0034]  1       BB49                  0.50     [260..268)-> BB52(0.5),BB51(0.5)     ( cond )                     i LIR
BB51 [0035]  1       BB50                  0.50     [268..283)-> BB57(1)                 (always)                     i LIR hascall
BB52 [0058]  1       BB50                  0.25     [???..???)-> BB64(1)                 (always)                     i LIR internal hascall
BB53 [0057]  1       BB49                  0.25     [???..???)-> BB67(1)                 (always)                     i LIR internal hascall
BB54 [0036]  1       BB48                  0.50     [283..288)-> BB63(0.5),BB55(0.5)     ( cond )                     i LIR
BB55 [0037]  1       BB54                  0.50     [288..290)-> BB62(0.5),BB56(0.5)     ( cond )                     i LIR
BB56 [0038]  1       BB55                  0.50     [290..29F)-> BB57(1)                 (always)                     i LIR hascall
BB57 [0039]  3       BB45,BB51,BB56        0.50     [29F..2B0)-> BB61(0.5),BB58(0.5)     ( cond )                     i LIR
BB58 [0061]  1       BB57                  0.25     [???..???)-> BB59(1)                 (always)                     i LIR internal hascall
BB59 [0040]  4       BB22,BB24,BB38,BB58   0.50     [2B0..2C6)-> BB60(1)                 (always)                     i LIR hascall
BB60 [0152]  2       BB02,BB59             0.50     [???..???)                           (return)                     LIR internal
BB61 [0062]  1       BB57                  0.25     [???..???)-> BB67(1)                 (always)                     i LIR internal hascall
BB62 [0060]  1       BB55                  0.25     [???..???)-> BB64(1)                 (always)                     i LIR internal hascall
BB63 [0059]  1       BB54                  0.25     [???..???)-> BB67(1)                 (always)                     i LIR internal hascall
BB64 [0041]  4       BB34,BB46,BB52,BB62   0.50     [2C6..2D9)-> BB67(0.5),BB65(0.5)     ( cond )                     i LIR
BB65 [0042]  1       BB64                  0.50     [2D9..2EF)                           (return)                     i LIR hascall
BB66 [0154]  1       BB39                  0.50     [???..???)                           (return)                     LIR internal
BB67 [0044]  7       BB40,BB41,BB47,BB53,BB61,BB63,BB64   0.50     [305..31D)-> BB69(0.5),BB68(0.5)     ( cond )                     i LIR
BB68 [0045]  1       BB67                  0.50     [31D..31F)-> BB70(1)                 (always)                     i LIR hascall
BB69 [0046]  1       BB67                  0.50     [31F..32B)-> BB70(1)                 (always)                     i LIR hascall gcsafe
BB70 [0155]  2       BB68,BB69             0.50     [???..???)                           (return)                     LIR internal
---------------------------------------------------------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Generate code
*************** In fgDebugCheckBBlist
Finalizing stack frame
Recording Var Locations at start of BB01
  V122(x19)  V02(x20)  V03(x21)  V120(x22)  V04(x23)  V119(x24)  V121(x25)  V05(x26)
must init V07 because it has a GC ref
must init V09 because it has a GC ref
Modified regs: [x0-xip1 x19-x28 lr d0-d31]
Callee-saved registers pushed: 20 [x19-x28 fp lr d8-d15]
*************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT)
Adjusting offset of dependent V00 of arg V119: parent 2673 field 0 net 2673
Adjusting offset of dependent V00 of arg V120: parent 2673 field 8 net 2681
Adjusting offset of dependent V01 of arg V121: parent 2650 field 0 net 2650
Adjusting offset of dependent V01 of arg V122: parent 2650 field 8 net 2658
Setting genSaveFpLrWithAllCalleeSavedRegisters to false
Assign V07 loc1, size=8, stkOffs=-0x98
Assign V08 loc2, size=8, stkOffs=-0xa0
Assign V09 loc3, size=8, stkOffs=-0xa8
Assign V10 loc4, size=4, stkOffs=-0xac
Assign V11 loc5, size=4, stkOffs=-0xb0
Assign V12 loc6, size=4, stkOffs=-0xb4
Assign V13 loc7, size=4, stkOffs=-0xb8
Assign V14 loc8, size=8, stkOffs=-0xc0
Assign V15 loc9, size=8, stkOffs=-0xc8
Assign V16 loc10, size=8, stkOffs=-0xd0
Assign V17 loc11, size=8, stkOffs=-0xd8
Assign V18 loc12, size=4, stkOffs=-0xdc
Assign V20 loc14, size=4, stkOffs=-0xe0
Assign V21 loc15, size=4, stkOffs=-0xe4
Assign V22 loc16, size=4, stkOffs=-0xe8
Assign V23 loc17, size=4, stkOffs=-0xec
Assign V24 loc18, size=4, stkOffs=-0xf0
Assign V26 loc20, size=8, stkOffs=-0xf8
Assign V27 loc21, size=8, stkOffs=-0x100
Assign V33 tmp1, size=4, stkOffs=-0x104
Pad V45 tmp13, size=8, stkOffs=-0x108, pad=4
Assign V45 tmp13, size=8, stkOffs=-0x110
Assign V46 tmp14, size=8, stkOffs=-0x118
Pad V47 tmp15, size=16, stkOffs=-0x120, pad=8
Assign V47 tmp15, size=16, stkOffs=-0x130
Pad V51 tmp19, size=16, stkOffs=-0x130, pad=0
Assign V51 tmp19, size=16, stkOffs=-0x140
Pad V52 tmp20, size=16, stkOffs=-0x140, pad=0
Assign V52 tmp20, size=16, stkOffs=-0x150
Pad V53 tmp21, size=16, stkOffs=-0x150, pad=0
Assign V53 tmp21, size=16, stkOffs=-0x160
Pad V54 tmp22, size=16, stkOffs=-0x160, pad=0
Assign V54 tmp22, size=16, stkOffs=-0x170
Pad V55 tmp23, size=16, stkOffs=-0x170, pad=0
Assign V55 tmp23, size=16, stkOffs=-0x180
Pad V56 tmp24, size=16, stkOffs=-0x180, pad=0
Assign V56 tmp24, size=16, stkOffs=-0x190
Pad V57 tmp25, size=16, stkOffs=-0x190, pad=0
Assign V57 tmp25, size=16, stkOffs=-0x1a0
Pad V58 tmp26, size=16, stkOffs=-0x1a0, pad=0
Assign V58 tmp26, size=16, stkOffs=-0x1b0
Pad V59 tmp27, size=16, stkOffs=-0x1b0, pad=0
Assign V59 tmp27, size=16, stkOffs=-0x1c0
Pad V60 tmp28, size=16, stkOffs=-0x1c0, pad=0
Assign V60 tmp28, size=16, stkOffs=-0x1d0
Pad V61 tmp29, size=16, stkOffs=-0x1d0, pad=0
Assign V61 tmp29, size=16, stkOffs=-0x1e0
Pad V62 tmp30, size=16, stkOffs=-0x1e0, pad=0
Assign V62 tmp30, size=16, stkOffs=-0x1f0
Pad V69 tmp37, size=16, stkOffs=-0x1f0, pad=0
Assign V69 tmp37, size=16, stkOffs=-0x200
Pad V70 tmp38, size=16, stkOffs=-0x200, pad=0
Assign V70 tmp38, size=16, stkOffs=-0x210
Pad V71 tmp39, size=16, stkOffs=-0x210, pad=0
Assign V71 tmp39, size=16, stkOffs=-0x220
Pad V75 tmp43, size=16, stkOffs=-0x220, pad=0
Assign V75 tmp43, size=16, stkOffs=-0x230
Pad V76 tmp44, size=16, stkOffs=-0x230, pad=0
Assign V76 tmp44, size=16, stkOffs=-0x240
Pad V77 tmp45, size=16, stkOffs=-0x240, pad=0
Assign V77 tmp45, size=16, stkOffs=-0x250
Assign V78 tmp46, size=8, stkOffs=-0x258
Assign V79 tmp47, size=8, stkOffs=-0x260
Pad V80 tmp48, size=16, stkOffs=-0x260, pad=0
Assign V80 tmp48, size=16, stkOffs=-0x270
Pad V81 tmp49, size=16, stkOffs=-0x270, pad=0
Assign V81 tmp49, size=16, stkOffs=-0x280
Pad V82 tmp50, size=16, stkOffs=-0x280, pad=0
Assign V82 tmp50, size=16, stkOffs=-0x290
Pad V83 tmp51, size=16, stkOffs=-0x290, pad=0
Assign V83 tmp51, size=16, stkOffs=-0x2a0
Pad V92 tmp60, size=16, stkOffs=-0x2a0, pad=0
Assign V92 tmp60, size=16, stkOffs=-0x2b0
Pad V100 tmp68, size=16, stkOffs=-0x2b0, pad=0
Assign V100 tmp68, size=16, stkOffs=-0x2c0
Assign V112 tmp80, size=4, stkOffs=-0x2c4
Assign V118 tmp86, size=4, stkOffs=-0x2c8
Pad V131 tmp99, size=16, stkOffs=-0x2d0, pad=8
Assign V131 tmp99, size=16, stkOffs=-0x2e0
Pad V132 tmp100, size=16, stkOffs=-0x2e0, pad=0
Assign V132 tmp100, size=16, stkOffs=-0x2f0
Pad V133 tmp101, size=16, stkOffs=-0x2f0, pad=0
Assign V133 tmp101, size=16, stkOffs=-0x300
Pad V134 tmp102, size=16, stkOffs=-0x300, pad=0
Assign V134 tmp102, size=16, stkOffs=-0x310
Pad V135 tmp103, size=16, stkOffs=-0x310, pad=0
Assign V135 tmp103, size=16, stkOffs=-0x320
Pad V136 tmp104, size=16, stkOffs=-0x320, pad=0
Assign V136 tmp104, size=16, stkOffs=-0x330
Pad V137 tmp105, size=16, stkOffs=-0x330, pad=0
Assign V137 tmp105, size=16, stkOffs=-0x340
Pad V138 tmp106, size=16, stkOffs=-0x340, pad=0
Assign V138 tmp106, size=16, stkOffs=-0x350
Pad V139 tmp107, size=16, stkOffs=-0x350, pad=0
Assign V139 tmp107, size=16, stkOffs=-0x360
Pad V140 tmp108, size=16, stkOffs=-0x360, pad=0
Assign V140 tmp108, size=16, stkOffs=-0x370
Assign V149 tmp117, size=8, stkOffs=-0x378
Pad V151 rat1, size=16, stkOffs=-0x380, pad=8
Assign V151 rat1, size=16, stkOffs=-0x390
Pad V152 rat2, size=16, stkOffs=-0x390, pad=0
Assign V152 rat2, size=16, stkOffs=-0x3a0
Assign V19 loc13, size=8, stkOffs=-0x3a8
--- delta bump 960 for FP frame
--- virtual stack offset to actual stack offset delta is 960
-- V07 was -152, now 808
-- V08 was -160, now 800
-- V09 was -168, now 792
-- V10 was -172, now 788
-- V11 was -176, now 784
-- V12 was -180, now 780
-- V13 was -184, now 776
-- V14 was -192, now 768
-- V15 was -200, now 760
-- V16 was -208, now 752
-- V17 was -216, now 744
-- V18 was -220, now 740
-- V19 was -936, now 24
-- V20 was -224, now 736
-- V21 was -228, now 732
-- V22 was -232, now 728
-- V23 was -236, now 724
-- V24 was -240, now 720
-- V26 was -248, now 712
-- V27 was -256, now 704
-- V32 was 0, now 960
-- V33 was -260, now 700
-- V45 was -272, now 688
-- V46 was -280, now 680
-- V47 was -304, now 656
-- V51 was -320, now 640
-- V52 was -336, now 624
-- V53 was -352, now 608
-- V54 was -368, now 592
-- V55 was -384, now 576
-- V56 was -400, now 560
-- V57 was -416, now 544
-- V58 was -432, now 528
-- V59 was -448, now 512
-- V60 was -464, now 496
-- V61 was -480, now 480
-- V62 was -496, now 464
-- V69 was -512, now 448
-- V70 was -528, now 432
-- V71 was -544, now 416
-- V75 was -560, now 400
-- V76 was -576, now 384
-- V77 was -592, now 368
-- V78 was -600, now 360
-- V79 was -608, now 352
-- V80 was -624, now 336
-- V81 was -640, now 320
-- V82 was -656, now 304
-- V83 was -672, now 288
-- V92 was -688, now 272
-- V100 was -704, now 256
-- V112 was -708, now 252
-- V118 was -712, now 248
-- V131 was -736, now 224
-- V132 was -752, now 208
-- V133 was -768, now 192
-- V134 was -784, now 176
-- V135 was -800, now 160
-- V136 was -816, now 144
-- V137 was -832, now 128
-- V138 was -848, now 112
-- V139 was -864, now 96
-- V140 was -880, now 80
-- V149 was -888, now 72
-- V151 was -912, now 48
-- V152 was -928, now 32
; Final local variable assignments
;
;* V00 arg0         [V00    ] (  0,  0   )  struct (16) zero-ref    multireg-arg ld-addr-op single-def <System.ReadOnlySpan`1[ubyte]>
;* V01 arg1         [V01    ] (  0,  0   )  struct (16) zero-ref    multireg-arg ld-addr-op single-def <System.Span`1[ubyte]>
;  V02 arg2         [V02,T14] (  8,  5   )   byref  ->  x20         single-def
;  V03 arg3         [V03,T15] (  8,  5   )   byref  ->  x21         single-def
;  V04 arg4         [V04,T18] (  6,  4   )   ubyte  ->  x23         single-def
;  V05 arg5         [V05,T22] (  3,  2.50)   ubyte  ->  x26         single-def
;  V06 loc0         [V06,T08] ( 14, 14   )    long  ->  x28
;  V07 loc1         [V07    ] (  1,  0.50)   byref  ->  [fp+0x328]  must-init pinned single-def
;  V08 loc2         [V08,T11] ( 10, 12   )    long  ->  [fp+0x320]  spill-single-def
;  V09 loc3         [V09    ] (  1,  0.50)   byref  ->  [fp+0x318]  must-init pinned single-def
;  V10 loc4         [V10,T23] (  7,  3.50)     int  ->  [fp+0x314]  spill-single-def
;  V11 loc5         [V11,T30] (  3,  1.50)     int  ->  [fp+0x310]  spill-single-def
;  V12 loc6         [V12,T10] ( 12, 13   )     int  ->  [fp+0x30C]
;  V13 loc7         [V13,T31] (  3,  1.50)     int  ->  [fp+0x308]  spill-single-def
;  V14 loc8         [V14,T00] ( 21, 35   )    long  ->  [fp+0x300]  ld-addr-op
;  V15 loc9         [V15,T01] ( 28, 31.50)    long  ->  [fp+0x2F8]  ld-addr-op
;  V16 loc10        [V16,T19] ( 10,  5   )    long  ->  [fp+0x2F0]  spill-single-def
;  V17 loc11        [V17,T17] (  6,  6.50)    long  ->  [fp+0x2E8]
;  V18 loc12        [V18,T32] (  3,  1.50)     int  ->  [fp+0x2E4]  spill-single-def
;  V19 loc13        [V19,T05] ( 10, 19   )   byref  ->  [fp+0x18]  spill-single-def
;  V20 loc14        [V20,T35] (  2,  1   )     int  ->  [fp+0x2E0]
;  V21 loc15        [V21,T36] (  2,  1   )     int  ->  [fp+0x2DC]
;  V22 loc16        [V22,T26] (  4,  2   )     int  ->  [fp+0x2D8]
;  V23 loc17        [V23,T33] (  3,  1.50)     int  ->  [fp+0x2D4]
;  V24 loc18        [V24,T13] ( 14,  7   )     int  ->  [fp+0x2D0]
;* V25 loc19        [V25    ] (  0,  0   )     int  ->  zero-ref
;  V26 loc20        [V26,T27] (  4,  2   )    long  ->  [fp+0x2C8]
;  V27 loc21        [V27,T12] (  6, 10   )    long  ->  [fp+0x2C0]
;* V28 loc22        [V28    ] (  0,  0   )     int  ->  zero-ref
;* V29 loc23        [V29    ] (  0,  0   )     int  ->  zero-ref
;* V30 loc24        [V30    ] (  0,  0   )     int  ->  zero-ref
;* V31 loc25        [V31    ] (  0,  0   )     int  ->  zero-ref
;# V32 OutArgs      [V32    ] (  1,  1   )  struct ( 0) [sp+0x00]  do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
;  V33 tmp1         [V33,T34] (  3,  1.50)     int  ->  [fp+0x2BC]
;* V34 tmp2         [V34    ] (  0,  0   )  struct (16) zero-ref    "spilled call-like call argument" <System.ReadOnlySpan`1[byte]>
;* V35 tmp3         [V35    ] (  0,  0   )  struct (16) zero-ref    ld-addr-op "Inlining Arg" <System.ReadOnlySpan`1[ubyte]>
;* V36 tmp4         [V36    ] (  0,  0   )  struct (16) zero-ref    ld-addr-op "Inlining Arg" <System.Span`1[ubyte]>
;* V37 tmp5         [V37,T78] (  0,  0   )  simd16  ->  zero-ref    HFA(simd16)  "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
;* V38 tmp6         [V38,T79] (  0,  0   )  simd16  ->  zero-ref    HFA(simd16)  "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
;* V39 tmp7         [V39,T80] (  0,  0   )  simd16  ->  zero-ref    HFA(simd16)  "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
;* V40 tmp8         [V40,T81] (  0,  0   )  simd16  ->  zero-ref    HFA(simd16)  "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
;* V41 tmp9         [V41,T82] (  0,  0   )  simd16  ->  zero-ref    HFA(simd16)  "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
;* V42 tmp10        [V42,T83] (  0,  0   )  simd16  ->  zero-ref    HFA(simd16)  "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
;* V43 tmp11        [V43,T84] (  0,  0   )  simd16  ->  zero-ref    HFA(simd16)  "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
;* V44 tmp12        [V44,T85] (  0,  0   )  simd16  ->  zero-ref    HFA(simd16)  "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
;  V45 tmp13        [V45,T02] (  7, 21   )    long  ->  [fp+0x2B0]  "Inline stloc first use temp"
;  V46 tmp14        [V46,T06] (  6, 17   )    long  ->  [fp+0x2A8]  "Inline stloc first use temp"
;  V47 tmp15        [V47,T38] (  9, 32.50)  simd16  ->  [fp+0x290]  HFA(simd16)  spill-single-def "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
;* V48 tmp16        [V48    ] (  0,  0   )  struct (64) zero-ref    HFA(simd16)  ld-addr-op "Inline ldloca(s) first use temp" <System.ValueTuple`4[System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]]>
;* V49 tmp17        [V49    ] (  0,  0   )  struct (64) zero-ref    HFA(simd16)  ld-addr-op "Inline ldloca(s) first use temp" <System.ValueTuple`4[System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]]>
;* V50 tmp18        [V50    ] (  0,  0   )  struct (64) zero-ref    HFA(simd16)  multireg-ret "Return value temp for multireg return" <System.ValueTuple`4[System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]]>
;  V51 tmp19        [V51,T56] (  3, 12   )  simd16  ->  [fp+0x280]  HFA(simd16)  "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
;  V52 tmp20        [V52,T51] (  4, 16   )  simd16  ->  [fp+0x270]  HFA(simd16)  "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
;  V53 tmp21        [V53,T52] (  4, 16   )  simd16  ->  [fp+0x260]  HFA(simd16)  "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
;  V54 tmp22        [V54,T57] (  3, 12   )  simd16  ->  [fp+0x250]  HFA(simd16)  "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
;  V55 tmp23        [V55,T41] (  5, 20   )  simd16  ->  [fp+0x240]  HFA(simd16)  "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
;  V56 tmp24        [V56,T42] (  5, 20   )  simd16  ->  [fp+0x230]  HFA(simd16)  "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
;  V57 tmp25        [V57,T43] (  5, 20   )  simd16  ->  [fp+0x220]  HFA(simd16)  "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
;  V58 tmp26        [V58,T44] (  5, 20   )  simd16  ->  [fp+0x210]  HFA(simd16)  "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
;  V59 tmp27        [V59,T65] (  2,  8   )  simd16  ->  [fp+0x200]  HFA(simd16)  "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
;  V60 tmp28        [V60,T66] (  2,  8   )  simd16  ->  [fp+0x1F0]  HFA(simd16)  "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
;  V61 tmp29        [V61,T67] (  2,  8   )  simd16  ->  [fp+0x1E0]  HFA(simd16)  "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
;  V62 tmp30        [V62,T68] (  2,  8   )  simd16  ->  [fp+0x1D0]  HFA(simd16)  "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
;* V63 tmp31        [V63    ] (  0,  0   )  simd16  ->  zero-ref    HFA(simd16)  "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
;  V64 tmp32        [V64,T69] (  2,  8   )  simd16  ->   d8         HFA(simd16)  "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
;  V65 tmp33        [V65,T70] (  2,  8   )  simd16  ->  d11         HFA(simd16)  "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
;  V66 tmp34        [V66,T71] (  2,  8   )  simd16  ->  d12         HFA(simd16)  "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
;* V67 tmp35        [V67    ] (  0,  0   )  struct (48) zero-ref    HFA(simd16)  ld-addr-op "NewObj constructor temp" <System.ValueTuple`3[System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte],System.Runtime.Intrinsics.Vector128`1[ubyte]]>
;* V68 tmp36        [V68    ] (  0,  0   )     int  ->  zero-ref
;  V69 tmp37        [V69,T75] (  2,  4.50)  simd16  ->  [fp+0x1C0]  HFA(simd16)  spill-single-def "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
;  V70 tmp38        [V70,T76] (  2,  4.50)  simd16  ->  [fp+0x1B0]  HFA(simd16)  spill-single-def "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
;  V71 tmp39        [V71,T77] (  2,  4.50)  simd16  ->  [fp+0x1A0]  HFA(simd16)  spill-single-def "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector128`1[byte]>
;* V72 tmp40        [V72,T86] (  0,  0   )  simd16  ->  zero-ref    HFA(simd16)  "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector128`1[byte]>
;* V73 tmp41        [V73    ] (  0,  0   )  simd16  ->  zero-ref    HFA(simd16)  "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
;* V74 tmp42        [V74    ] (  0,  0   )  simd16  ->  zero-ref    HFA(simd16)  "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector128`1[short]>
;  V75 tmp43        [V75,T64] (  3,  8.50)  simd16  ->  [fp+0x190]  HFA(simd16)  spill-single-def "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
;  V76 tmp44        [V76,T54] (  4, 12.50)  simd16  ->  [fp+0x180]  HFA(simd16)  spill-single-def "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
;  V77 tmp45        [V77,T55] (  4, 12.50)  simd16  ->  [fp+0x170]  HFA(simd16)  spill-single-def "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
;  V78 tmp46        [V78,T03] (  7, 21   )    long  ->  [fp+0x168]  "Inline stloc first use temp"
;  V79 tmp47        [V79,T07] (  6, 17   )    long  ->  [fp+0x160]  "Inline stloc first use temp"
;  V80 tmp48        [V80,T37] ( 10, 40   )  simd16  ->  [fp+0x150]  HFA(simd16)  "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
;  V81 tmp49        [V81,T58] (  3, 12   )  simd16  ->  [fp+0x140]  HFA(simd16)  spill-single-def "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
;  V82 tmp50        [V82,T72] (  2,  8   )  simd16  ->  [fp+0x130]  HFA(simd16)  spill-single-def "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
;  V83 tmp51        [V83,T73] (  2,  8   )  simd16  ->  [fp+0x120]  HFA(simd16)  spill-single-def "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
;* V84 tmp52        [V84    ] (  0,  0   )  simd16  ->  zero-ref    HFA(simd16)  "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
;* V85 tmp53        [V85    ] (  0,  0   )  simd16  ->  zero-ref    HFA(simd16)  "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
;* V86 tmp54        [V86    ] (  0,  0   )  simd16  ->  zero-ref    HFA(simd16)  "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
;* V87 tmp55        [V87    ] (  0,  0   )  simd16  ->  zero-ref    HFA(simd16)  "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector128`1[ushort]>
;* V88 tmp56        [V88    ] (  0,  0   )  simd16  ->  zero-ref    HFA(simd16)  "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector128`1[ushort]>
;  V89 tmp57        [V89,T59] (  3, 12   )  simd16  ->  d20         HFA(simd16)  "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector128`1[short]>
;* V90 tmp58        [V90    ] (  0,  0   )  simd16  ->  zero-ref    HFA(simd16)  "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector128`1[int]>
;* V91 tmp59        [V91    ] (  0,  0   )  simd16  ->  zero-ref    HFA(simd16)  "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector128`1[int]>
;  V92 tmp60        [V92,T74] (  2,  8   )  simd16  ->  [fp+0x110]  HFA(simd16)  spill-single-def "Inline stloc first use temp" <System.Runtime.Intrinsics.Vector128`1[int]>
;* V93 tmp61        [V93    ] (  0,  0   )     int  ->  zero-ref
;* V94 tmp62        [V94    ] (  0,  0   )  simd16  ->  zero-ref    HFA(simd16)  "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
;* V95 tmp63        [V95    ] (  0,  0   )  simd16  ->  zero-ref    HFA(simd16)  "Inline return value spill temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
;* V96 tmp64        [V96    ] (  0,  0   )     int  ->  zero-ref
;* V97 tmp65        [V97    ] (  0,  0   )  simd16  ->  zero-ref    HFA(simd16)  "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
;* V98 tmp66        [V98    ] (  0,  0   )  simd16  ->  zero-ref    HFA(simd16)  "Inline return value spill temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
;* V99 tmp67        [V99    ] (  0,  0   )     int  ->  zero-ref
;  V100 tmp68       [V100,T53] (  2, 16   )  simd16  ->  [fp+0x100]  HFA(simd16)  spill-single-def "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
;* V101 tmp69       [V101    ] (  0,  0   )  simd16  ->  zero-ref    HFA(simd16)  "Inline return value spill temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
;* V102 tmp70       [V102    ] (  0,  0   )     int  ->  zero-ref
;* V103 tmp71       [V103    ] (  0,  0   )  simd16  ->  zero-ref    HFA(simd16)  "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
;* V104 tmp72       [V104    ] (  0,  0   )  simd16  ->  zero-ref    HFA(simd16)  "Inline return value spill temp" <System.Runtime.Intrinsics.Vector128`1[ubyte]>
;* V105 tmp73       [V105    ] (  0,  0   )  struct (16) zero-ref    ld-addr-op "NewObj constructor temp" <System.ReadOnlySpan`1[byte]>
;* V106 tmp74       [V106    ] (  0,  0   )  struct (16) zero-ref    ld-addr-op "Inlining Arg" <System.ReadOnlySpan`1[byte]>
;* V107 tmp75       [V107    ] (  0,  0   )    long  ->  zero-ref    "Inlining Arg"
;* V108 tmp76       [V108    ] (  0,  0   )     int  ->  zero-ref    "Inline stloc first use temp"
;* V109 tmp77       [V109    ] (  0,  0   )     int  ->  zero-ref    "Inline stloc first use temp"
;* V110 tmp78       [V110    ] (  0,  0   )     int  ->  zero-ref    "Inline stloc first use temp"
;* V111 tmp79       [V111    ] (  0,  0   )     int  ->  zero-ref    "Inline stloc first use temp"
;  V112 tmp80       [V112,T04] (  5, 20   )     int  ->  [fp+0xFC]  spill-single-def "Inline stloc first use temp"
;* V113 tmp81       [V113    ] (  0,  0   )     int  ->  zero-ref    "Inline stloc first use temp"
;* V114 tmp82       [V114    ] (  0,  0   )     int  ->  zero-ref    "Inline stloc first use temp"
;* V115 tmp83       [V115    ] (  0,  0   )     int  ->  zero-ref    "Inline stloc first use temp"
;* V116 tmp84       [V116    ] (  0,  0   )    long  ->  zero-ref    "Inlining Arg"
;* V117 tmp85       [V117    ] (  0,  0   )    long  ->  zero-ref    "Inlining Arg"
;  V118 tmp86       [V118,T24] (  3,  3   )     int  ->  [fp+0xF8]  "Single return block return value"
;  V119 tmp87       [V119,T20] (  4,  2.50)   byref  ->  x24         single-def "field V00._reference (fldOffset=0x0)" P-INDEP
;  V120 tmp88       [V120,T16] (  7,  4.50)     int  ->  x22         single-def "field V00._length (fldOffset=0x8)" P-INDEP
;  V121 tmp89       [V121,T21] (  4,  2.50)   byref  ->  x25         single-def "field V01._reference (fldOffset=0x0)" P-INDEP
;  V122 tmp90       [V122,T09] (  9, 12   )     int  ->  x19         single-def "field V01._length (fldOffset=0x8)" P-INDEP
;* V123 tmp91       [V123    ] (  0,  0   )   byref  ->  zero-ref    "field V34._reference (fldOffset=0x0)" P-INDEP
;* V124 tmp92       [V124    ] (  0,  0   )     int  ->  zero-ref    "field V34._length (fldOffset=0x8)" P-INDEP
;* V125 tmp93       [V125    ] (  0,  0   )   byref  ->  zero-ref    single-def "field V35._reference (fldOffset=0x0)" P-INDEP
;* V126 tmp94       [V126    ] (  0,  0   )     int  ->  zero-ref    "field V35._length (fldOffset=0x8)" P-INDEP
;* V127 tmp95       [V127    ] (  0,  0   )   byref  ->  zero-ref    single-def "field V36._reference (fldOffset=0x0)" P-INDEP
;* V128 tmp96       [V128    ] (  0,  0   )     int  ->  zero-ref    "field V36._length (fldOffset=0x8)" P-INDEP
;* V129 tmp97       [V129,T87] (  0,  0   )  simd16  ->  zero-ref    HFA(simd16)  "field V48.Item1 (fldOffset=0x0)" P-INDEP
;* V130 tmp98       [V130,T88] (  0,  0   )  simd16  ->  zero-ref    HFA(simd16)  "field V48.Item2 (fldOffset=0x10)" P-INDEP
;  V131 tmp99       [V131,T45] (  5, 16.50)  simd16  ->  [fp+0xE0]  HFA(simd16)  spill-single-def "field V48.Item3 (fldOffset=0x20)" P-INDEP
;  V132 tmp100      [V132,T46] (  5, 16.50)  simd16  ->  [fp+0xD0]  HFA(simd16)  spill-single-def "field V48.Item4 (fldOffset=0x30)" P-INDEP
;  V133 tmp101      [V133,T47] (  5, 16.50)  simd16  ->  [fp+0xC0]  HFA(simd16)  spill-single-def "field V49.Item1 (fldOffset=0x0)" P-INDEP
;  V134 tmp102      [V134,T48] (  5, 16.50)  simd16  ->  [fp+0xB0]  HFA(simd16)  spill-single-def "field V49.Item2 (fldOffset=0x10)" P-INDEP
;  V135 tmp103      [V135,T49] (  5, 16.50)  simd16  ->  [fp+0xA0]  HFA(simd16)  spill-single-def "field V49.Item3 (fldOffset=0x20)" P-INDEP
;  V136 tmp104      [V136,T50] (  5, 16.50)  simd16  ->  [fp+0x90]  HFA(simd16)  spill-single-def "field V49.Item4 (fldOffset=0x30)" P-INDEP
;  V137 tmp105      [V137,T60] (  3, 12   )  simd16  ->  [fp+0x80]  HFA(simd16)  "field V50.Item1 (fldOffset=0x0)" P-INDEP
;  V138 tmp106      [V138,T61] (  3, 12   )  simd16  ->  [fp+0x70]  HFA(simd16)  "field V50.Item2 (fldOffset=0x10)" P-INDEP
;  V139 tmp107      [V139,T62] (  3, 12   )  simd16  ->  [fp+0x60]  HFA(simd16)  "field V50.Item3 (fldOffset=0x20)" P-INDEP
;  V140 tmp108      [V140,T63] (  3, 12   )  simd16  ->  [fp+0x50]  HFA(simd16)  "field V50.Item4 (fldOffset=0x30)" P-INDEP
;* V141 tmp109      [V141    ] (  0,  0   )  simd16  ->  zero-ref    HFA(simd16)  "field V67.Item1 (fldOffset=0x0)" P-INDEP
;* V142 tmp110      [V142    ] (  0,  0   )  simd16  ->  zero-ref    HFA(simd16)  "field V67.Item2 (fldOffset=0x10)" P-INDEP
;* V143 tmp111      [V143    ] (  0,  0   )  simd16  ->  zero-ref    HFA(simd16)  "field V67.Item3 (fldOffset=0x20)" P-INDEP
;* V144 tmp112      [V144    ] (  0,  0   )   byref  ->  zero-ref    single-def "field V105._reference (fldOffset=0x0)" P-INDEP
;* V145 tmp113      [V145    ] (  0,  0   )     int  ->  zero-ref    "field V105._length (fldOffset=0x8)" P-INDEP
;* V146 tmp114      [V146    ] (  0,  0   )   byref  ->  zero-ref    single-def "field V106._reference (fldOffset=0x0)" P-INDEP
;* V147 tmp115      [V147    ] (  0,  0   )     int  ->  zero-ref    "field V106._length (fldOffset=0x8)" P-INDEP
;  V148 tmp116      [V148,T28] (  2,  2   )    long  ->  x27         "Cast away GC"
;  V149 tmp117      [V149,T29] (  2,  2   )    long  ->  [fp+0x48]  "Cast away GC"
;  V150 rat0        [V150,T25] (  3,  3   )     int  ->   x4         "ReplaceWithLclVar is creating a new local variable"
;  V151 rat1        [V151,T39] (  3, 24   )  simd16  ->  [fp+0x30]  "ReplaceWithLclVar is creating a new local variable"
;  V152 rat2        [V152,T40] (  3, 24   )  simd16  ->  [fp+0x20]  "ReplaceWithLclVar is creating a new local variable"
;
; Lcl frame size = 800
Created:
      G_M30837_IG02:        ; offs=0x000000, size=0x0000, bbWeight=1, gcrefRegs=0000 {}
Mark labels for codegen
  BB01 : first block
  BB03 : branch target
  BB60 : branch target
  BB05 : branch target
  BB07 : branch target
  BB20 : branch target
  BB25 : branch target
  BB12 : branch target
  BB72 : branch target
  BB24 : branch target
  BB23 : branch target
  BB18 : branch target
  BB74 : branch target
  BB22 : branch target
  BB26 : branch target
  BB27 : branch target
  BB16 : branch target
  BB10 : branch target
  BB59 : branch target
  BB20 : branch target
  BB59 : branch target
  BB14 : branch target
  BB29 : branch target
  BB30 : branch target
  BB75 : branch target
  BB41 : branch target
  BB76 : branch target
  BB64 : branch target
  BB42 : branch target
  BB40 : branch target
  BB59 : branch target
  BB66 : branch target
  BB31 : branch target
  BB34 : branch target
  BB67 : branch target
  BB67 : branch target
  BB48 : branch target
  BB47 : branch target
  BB46 : branch target
  BB57 : branch target
  BB64 : branch target
  BB67 : branch target
  BB54 : branch target
  BB53 : branch target
  BB52 : branch target
  BB57 : branch target
  BB64 : branch target
  BB67 : branch target
  BB63 : branch target
  BB62 : branch target
  BB61 : branch target
  BB67 : branch target
  BB64 : branch target
  BB67 : branch target
  BB67 : branch target
  BB69 : branch target
  BB70 : branch target
*************** After genMarkLabelsForCodegen()

---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   IBC [IL range]   [jump]                            [EH region]        [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1        [000..009)-> BB03(0.5),BB02(0.5)     ( cond )                     i LIR label
BB02 [0001]  1       BB01                  0.50     [009..011)-> BB60(1)                 (always)                     i LIR hascall
BB03 [0002]  1       BB01                  0.50  50 [011..03F)-> BB05(0.5),BB04(0.5)     ( cond )                     i LIR IBC label
BB04 [0067]  1       BB03                  0      0 [03E..03F)                           (throw )                     i LIR IBC rare hascall gcsafe
BB05 [0068]  1       BB03                  0.50  50 [03E..04F)-> BB07(0.5),BB06(0.5)     ( cond )                     i LIR IBC label
BB06 [0003]  1       BB05                  0.50     [04F..057)-> BB07(1)                 (always)                     i LIR hascall
BB07 [0004]  2       BB05,BB06             0.50     [057..074)-> BB20(0.5),BB08(0.5)     ( cond )                     i LIR label
BB08 [0005]  1       BB07                  0.50     [074..09C)-> BB25(0.5),BB09(0.5)     ( cond )                     i LIR
BB09 [0009]  1       BB08                  0.50     [09C..0AD)-> BB10(1)                 (always)                     i LIR
BB10 [0071]  2       BB09,BB72             4        [09C..09D)-> BB12(0.5),BB11(0.5)     ( cond )                     i LIR loophead label hascall gcsafe bwd bwd-target
BB11 [0072]  1       BB10                  4        [09C..09D)-> BB72(0.5),BB71(0.5)     ( cond )                     i LIR hascall gcsafe bwd bwd-src
BB71 [0159]  1       BB11                  2        [???..???)-> BB12(1)                 (always)                     LIR internal
BB12 [0073]  2       BB10,BB71             0.50     [09C..0B6)-> BB24(0.5),BB13(0.5)     ( cond )                     i LIR label
BB13 [0048]  1       BB12                  0.25     [???..???)-> BB14(1)                 (always)                     i LIR internal hascall
BB14 [0010]  2       BB13,BB25             0.50     [0B6..0D2)-> BB23(0.5),BB15(0.5)     ( cond )                     i LIR label
BB15 [0012]  1       BB14                  0.50     [0D2..0E3)-> BB16(1)                 (always)                     i LIR hascall gcsafe
BB16 [0082]  2       BB15,BB74             4    400 [0D2..0D3)-> BB18(0.5),BB17(0.5)     ( cond )                     i LIR IBC loophead label hascall gcsafe bwd bwd-target
BB17 [0083]  1       BB16                  4    400 [0D2..0D3)-> BB74(0.5),BB73(0.5)     ( cond )                     i LIR IBC hascall gcsafe bwd
BB73 [0161]  1       BB17                  2    200 [???..???)-> BB18(1)                 (always)                     LIR IBC internal
BB18 [0086]  2       BB16,BB73             0.50     [0D2..0EC)-> BB22(0.5),BB19(0.5)     ( cond )                     i LIR label
BB19 [0051]  1       BB18                  0.25     [???..???)-> BB20(1)                 (always)                     i LIR internal hascall
BB20 [0013]  3       BB07,BB19,BB23        0.50     [0EC..0F0)-> BB26(0.5),BB21(0.5)     ( cond )                     i LIR label
BB21 [0014]  1       BB20                  0.50     [0F0..0F3)-> BB27(1)                 (always)                     i LIR
BB74 [0162]  1       BB17                  2    200 [???..???)-> BB16(1)                 (always)                     LIR IBC internal label bwd
BB72 [0160]  1       BB11                  2        [???..???)-> BB10(1)                 (always)                     LIR internal label bwd
BB22 [0052]  1       BB18                  0.25     [???..???)-> BB59(1)                 (always)                     i LIR internal label hascall
BB23 [0050]  1       BB14                  0.25     [???..???)-> BB20(1)                 (always)                     i LIR internal label hascall
BB24 [0049]  1       BB12                  0.25     [???..???)-> BB59(1)                 (always)                     i LIR internal label hascall
BB25 [0047]  1       BB08                  0.25     [???..???)-> BB14(1)                 (always)                     i LIR internal label hascall
BB26 [0015]  1       BB20                  0.50     [0F3..0F4)-> BB27(1)                 (always)                     i LIR label hascall
BB27 [0016]  2       BB21,BB26             0.50     [0F4..0FC)-> BB29(0.5),BB28(0.5)     ( cond )                     i LIR label
BB28 [0017]  1       BB27                  0.50     [0FC..105)-> BB30(1)                 (always)                     i LIR
BB29 [0018]  1       BB27                  0.50     [105..11B)-> BB30(1)                 (always)                     i LIR label hascall gcsafe
BB30 [0019]  2       BB28,BB29             0.50  50 [11B..12F)-> BB75(0.5),BB31(0.5)     ( cond )                     i LIR IBC label
BB31 [0157]  2       BB30,BB76             4    400 [12F..142)-> BB41(0.5),BB33(0.5)     ( cond )                     i LIR IBC label bwd
BB33 [0021]  1       BB31                  4        [142..15D)-> BB76(0.5),BB34(0.5)     ( cond )                     i LIR hascall bwd
BB34 [0158]  2       BB33,BB75             0.50     [15D..169)-> BB64(0.5),BB36(0.5)     ( cond )                     i LIR label
BB36 [0024]  1       BB34                  0.50     [169..16F)-> BB42(0.5),BB37(0.5)     ( cond )                     i LIR
BB37 [0025]  1       BB36                  0.50     [16F..176)-> BB40(0.5),BB38(0.5)     ( cond )                     i LIR
BB38 [0026]  1       BB37                  0.50     [176..186)-> BB59(0.5),BB39(0.5)     ( cond )                     i LIR
BB39 [0043]  1       BB38                  0.50     [2EF..305)-> BB66(1)                 (always)                     i LIR hascall
BB76 [0164]  1       BB33                  2        [???..???)-> BB31(1)                 (always)                     LIR internal label bwd
BB75 [0163]  1       BB30                  0.25  25 [???..???)-> BB34(1)                 (always)                     LIR IBC internal label
BB40 [0054]  1       BB37                  0.25     [???..???)-> BB67(1)                 (always)                     i LIR internal label hascall
BB41 [0053]  1       BB31                  0.25     [???..???)-> BB67(1)                 (always)                     i LIR internal label hascall
BB42 [0028]  1       BB36                  0.50     [18B..1E6)-> BB48(0.5),BB43(0.5)     ( cond )                     i LIR label
BB43 [0029]  1       BB42                  0.50     [1E6..21C)-> BB47(0.5),BB44(0.5)     ( cond )                     i LIR
BB44 [0030]  1       BB43                  0.50     [21C..227)-> BB46(0.5),BB45(0.5)     ( cond )                     i LIR
BB45 [0031]  1       BB44                  0.50     [227..238)-> BB57(1)                 (always)                     i LIR
BB46 [0056]  1       BB44                  0.25     [???..???)-> BB64(1)                 (always)                     i LIR internal label hascall
BB47 [0055]  1       BB43                  0.25     [???..???)-> BB67(1)                 (always)                     i LIR internal label hascall
BB48 [0032]  1       BB42                  0.50     [238..23E)-> BB54(0.5),BB49(0.5)     ( cond )                     i LIR label
BB49 [0033]  1       BB48                  0.50     [23E..260)-> BB53(0.5),BB50(0.5)     ( cond )                     i LIR
BB50 [0034]  1       BB49                  0.50     [260..268)-> BB52(0.5),BB51(0.5)     ( cond )                     i LIR
BB51 [0035]  1       BB50                  0.50     [268..283)-> BB57(1)                 (always)                     i LIR hascall
BB52 [0058]  1       BB50                  0.25     [???..???)-> BB64(1)                 (always)                     i LIR internal label hascall
BB53 [0057]  1       BB49                  0.25     [???..???)-> BB67(1)                 (always)                     i LIR internal label hascall
BB54 [0036]  1       BB48                  0.50     [283..288)-> BB63(0.5),BB55(0.5)     ( cond )                     i LIR label
BB55 [0037]  1       BB54                  0.50     [288..290)-> BB62(0.5),BB56(0.5)     ( cond )                     i LIR
BB56 [0038]  1       BB55                  0.50     [290..29F)-> BB57(1)                 (always)                     i LIR hascall
BB57 [0039]  3       BB45,BB51,BB56        0.50     [29F..2B0)-> BB61(0.5),BB58(0.5)     ( cond )                     i LIR label
BB58 [0061]  1       BB57                  0.25     [???..???)-> BB59(1)                 (always)                     i LIR internal hascall
BB59 [0040]  4       BB22,BB24,BB38,BB58   0.50     [2B0..2C6)-> BB60(1)                 (always)                     i LIR label hascall
BB60 [0152]  2       BB02,BB59             0.50     [???..???)                           (return)                     LIR internal label
BB61 [0062]  1       BB57                  0.25     [???..???)-> BB67(1)                 (always)                     i LIR internal label hascall
BB62 [0060]  1       BB55                  0.25     [???..???)-> BB64(1)                 (always)                     i LIR internal label hascall
BB63 [0059]  1       BB54                  0.25     [???..???)-> BB67(1)                 (always)                     i LIR internal label hascall
BB64 [0041]  4       BB34,BB46,BB52,BB62   0.50     [2C6..2D9)-> BB67(0.5),BB65(0.5)     ( cond )                     i LIR label
BB65 [0042]  1       BB64                  0.50     [2D9..2EF)                           (return)                     i LIR hascall
BB66 [0154]  1       BB39                  0.50     [???..???)                           (return)                     LIR internal label
BB67 [0044]  7       BB40,BB41,BB47,BB53,BB61,BB63,BB64   0.50     [305..31D)-> BB69(0.5),BB68(0.5)     ( cond )                     i LIR label
BB68 [0045]  1       BB67                  0.50     [31D..31F)-> BB70(1)                 (always)                     i LIR hascall
BB69 [0046]  1       BB67                  0.50     [31F..32B)-> BB70(1)                 (always)                     i LIR label hascall gcsafe
BB70 [0155]  2       BB68,BB69             0.50     [???..???)                           (return)                     LIR internal label
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
Setting stack level from -572662307 to 0

=============== Generating BB01 [0000] [000..009) -> BB03(0.5),BB02(0.5) (cond), preds={} succs={BB02,BB03} flags=0x00000000.00008011: i LIR label
BB01 IN (8)={V122 V02 V03 V120 V04 V119 V121 V05} + ByrefExposed + GcHeap
     OUT(8)={V122 V02 V03 V120 V04 V119 V121 V05} + ByrefExposed + GcHeap

Recording Var Locations at start of BB01
  V122(x19)  V02(x20)  V03(x21)  V120(x22)  V04(x23)  V119(x24)  V121(x25)  V05(x26)
Change life 00000000000000000000000000000000 {} -> 0000000000000000000000000075C200 {V02 V03 V04 V05 V119 V120 V121 V122}
							V122 in reg x19 is becoming live  [------]
							Live regs: 0000000000000000 {} + {x19} => 0000000000080000 {x19}
							V02 in reg x20 is becoming live  [------]
							Live regs: 0000000000080000 {x19} + {x20} => 0000000000180000 {x19 x20}
Debug: New V02 debug range: first
							V03 in reg x21 is becoming live  [------]
							Live regs: 0000000000180000 {x19 x20} + {x21} => 0000000000380000 {x19 x20 x21}
Debug: New V03 debug range: first
							V120 in reg x22 is becoming live  [------]
							Live regs: 0000000000380000 {x19 x20 x21} + {x22} => 0000000000780000 {x19 x20 x21 x22}
							V04 in reg x23 is becoming live  [------]
							Live regs: 0000000000780000 {x19 x20 x21 x22} + {x23} => 0000000000F80000 {x19 x20 x21 x22 x23}
Debug: New V04 debug range: first
							V119 in reg x24 is becoming live  [------]
							Live regs: 0000000000F80000 {x19 x20 x21 x22 x23} + {x24} => 0000000001F80000 {x19 x20 x21 x22 x23 x24}
							V121 in reg x25 is becoming live  [------]
							Live regs: 0000000001F80000 {x19 x20 x21 x22 x23 x24} + {x25} => 0000000003F80000 {x19 x20 x21 x22 x23 x24 x25}
							V05 in reg x26 is becoming live  [------]
							Live regs: 0000000003F80000 {x19 x20 x21 x22 x23 x24 x25} + {x26} => 0000000007F80000 {x19 x20 x21 x22 x23 x24 x25 x26}
Debug: New V05 debug range: first
							Live regs: (unchanged) 0000000007F80000 {x19 x20 x21 x22 x23 x24 x25 x26}
							GC regs: (unchanged) 0000 {}
							Byref regs: (unchanged) 3300000 {x20 x21 x24 x25}

      L_M30837_BB01:
Label: G_M30837_IG02, GCvars=00000000000000000000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=3300000 {x20 x21 x24 x25}

Scope info: begin block BB01, IL range [000..009)
Added IP mapping: 0x0000 STACK_EMPTY (G_M30837_IG02,ins#0,ofs#0) label
Generating: N003 (???,???) [001570] -----------                            IL_OFFSET void   INLRT @ 0x000[E-] REG NA
Generating: N005 (  1,  1) [000570] -----------                  t570 =    LCL_VAR   int    V120 tmp88       u:1 x22 REG x22 $100
Generating: N007 (  1,  2) [000571] -c---------                  t571 =    CNS_INT   int    0 REG NA $49
                                                                        /--*  t570   int
                                                                        +--*  t571   int
Generating: N009 (  5,  6) [000005] -----------                         *  JCMP      void   REG NA
Mapped BB01 to G_M30837_IG02
IN0001:             cbnz    (LARGEJMP)L_M30837_BB03

Variable Live Range History Dump for BB01
V02 arg2: x20 [(G_M30837_IG02,ins#0,ofs#0), ...]
V03 arg3: x21 [(G_M30837_IG02,ins#0,ofs#0), ...]
V04 arg4: x23 [(G_M30837_IG02,ins#0,ofs#0), ...]
V05 arg5: x26 [(G_M30837_IG02,ins#0,ofs#0), ...]

=============== Generating BB02 [0001] [009..011) -> BB60(1) (always), preds={BB01} succs={BB60} flags=0x00000000.10000011: i LIR hascall
BB02 IN (2)={V02 V03} + ByrefExposed + GcHeap
     OUT(0)={       }

Recording Var Locations at start of BB02
  V02(x20)  V03(x21)
Change life 0000000000000000000000000075C200 {V02 V03 V04 V05 V119 V120 V121 V122} -> 0000000000000000000000000000C000 {V02 V03}
							V122 in reg x19 is becoming dead  [------]
							Live regs: (unchanged) 0000000000000000 {}
							V120 in reg x22 is becoming dead  [------]
							Live regs: (unchanged) 0000000000000000 {}
							V04 in reg x23 is becoming dead  [------]
							Live regs: (unchanged) 0000000000000000 {}
Debug: Closing V04 debug range.
							V119 in reg x24 is becoming dead  [------]
							Live regs: (unchanged) 0000000000000000 {}
							V121 in reg x25 is becoming dead  [------]
							Live regs: (unchanged) 0000000000000000 {}
							V05 in reg x26 is becoming dead  [------]
							Live regs: (unchanged) 0000000000000000 {}
Debug: Closing V05 debug range.
							Live regs: 0000000000000000 {} + {x20 x21} => 0000000000300000 {x20 x21}
							GC regs: (unchanged) 0000 {}
							Byref regs: 0000 {} => 300000 {x20 x21}

      L_M30837_BB02:
Adding label due to BB weight difference: BBJ_COND BB01 with weight 100 different from BB02 with weight 50
Saved:
      G_M30837_IG02:        ; offs=0x000000, size=0x0008, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=3300000 {x20 x21 x24 x25}, BB01 [0000], byref
Created:
      G_M30837_IG03:        ; offs=0x000008, size=0x0000, bbWeight=0.50, gcrefRegs=0000 {}
Label: G_M30837_IG03, GCvars=00000000000000000000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=300000 {x20 x21}

Scope info: begin block BB02, IL range [009..011)
Generating: N013 (  3, 12) [000512] H----------                  t512 =    CNS_INT(h) long   0xffff6658dbb0 bbc REG x0 $228
Mapped BB02 to G_M30837_IG03
IN0002:             movz    x0, #0xDBB0
IN0003:             movk    x0, #0x6658 LSL #16
IN0004:             movk    x0, #0xFFFF LSL #32
                                                                        /--*  t512   long
Generating: N015 (???,???) [001736] -----------                 t1736 = *  PUTARG_REG long   REG x0
                                                                        /--*  t1736  long   arg0 in x0
Generating: N017 ( 17, 15) [000513] --CXG------                  u513 = *  CALL help int    CORINFO_HELP_COUNTPROFILE32 REG x0 $8f8
Call: GCvars=00000000000000000000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=300000 {x20 x21}
[05] Rec call GC vars = 00000000000000000000000000000000
IN0005:             bl      CORINFO_HELP_COUNTPROFILE32
Added IP mapping: 0x0009 STACK_EMPTY (G_M30837_IG03,ins#4,ofs#16) label
Generating: N019 (???,???) [001571] -----------                            IL_OFFSET void   INLRT @ 0x009[E-] REG NA
Generating: N021 (  1,  1) [000504] -----------                  t504 =    LCL_VAR   byref  V02 arg2         u:1 x20 (last use) REG x20 $80
Generating: N023 (  1,  2) [000505] -c---------                  t505 =    CNS_INT   int    0 REG NA $49
                                                                        /--*  t504   byref
                                                                        +--*  t505   int
Generating: N025 (  5,  5) [000506] -A-XG------                         *  STOREIND  int    REG NA $874
							V02 in reg x20 is becoming dead  [000504]
							Live regs: 0000000000300000 {x20 x21} - {x20} => 0000000000200000 {x21}
Debug: Closing V02 debug range.
							Live vars after [000504]: {V02 V03} -{V02} => {V03}
							Byref regs: 300000 {x20 x21} => 200000 {x21}
IN0006:             str     wzr, [x20]
Added IP mapping: 0x000C STACK_EMPTY (G_M30837_IG03,ins#5,ofs#20)
Generating: N027 (???,???) [001572] -----------                            IL_OFFSET void   INLRT @ 0x00C[E-] REG NA
Generating: N029 (  1,  1) [000507] -----------                  t507 =    LCL_VAR   byref  V03 arg3         u:1 x21 (last use) REG x21 $81
Generating: N031 (  1,  2) [000508] -c---------                  t508 =    CNS_INT   int    0 REG NA $49
                                                                        /--*  t507   byref
                                                                        +--*  t508   int
Generating: N033 (  5,  5) [000509] -A-XG------                         *  STOREIND  int    REG NA $876
							V03 in reg x21 is becoming dead  [000507]
							Live regs: 0000000000200000 {x21} - {x21} => 0000000000000000 {}
Debug: Closing V03 debug range.
							Live vars after [000507]: {V03} -{V03} => {}
							Byref regs: 200000 {x21} => 0000 {}
IN0007:             str     wzr, [x21]
IN0008:             b       L_M30837_BB60

Variable Live Range History Dump for BB02
V02 arg2: x20 [(G_M30837_IG02,ins#0,ofs#0), (G_M30837_IG03,ins#4,ofs#16)]
V03 arg3: x21 [(G_M30837_IG02,ins#0,ofs#0), (G_M30837_IG03,ins#5,ofs#20)]
V04 arg4: x23 [(G_M30837_IG02,ins#0,ofs#0), (G_M30837_IG02,ins#1,ofs#8)]
V05 arg5: x26 [(G_M30837_IG02,ins#0,ofs#0), (G_M30837_IG02,ins#1,ofs#8)]

=============== Generating BB03 [0002] [011..03F) -> BB05(0.5),BB04(0.5) (cond), preds={BB01} succs={BB04,BB05} flags=0x00000000.04008011: i LIR IBC label
BB03 IN (8)={    V122         V02 V03 V120 V04 V119 V121 V05        } + ByrefExposed + GcHeap
     OUT(13)={V06 V122 V12 V08 V02 V03 V120 V04 V119 V121 V05 V10 V11} + ByrefExposed + GcHeap

Recording Var Locations at start of BB03
  V122(x19)  V02(x20)  V03(x21)  V120(x22)  V04(x23)  V119(x24)  V121(x25)  V05(x26)
Change life 00000000000000000000000000000000 {} -> 0000000000000000000000000075C200 {V02 V03 V04 V05 V119 V120 V121 V122}
							V122 in reg x19 is becoming live  [------]
							Live regs: 0000000000000000 {} + {x19} => 0000000000080000 {x19}
							V02 in reg x20 is becoming live  [------]
							Live regs: 0000000000080000 {x19} + {x20} => 0000000000180000 {x19 x20}
Debug: New V02 debug range: new var or location
							V03 in reg x21 is becoming live  [------]
							Live regs: 0000000000180000 {x19 x20} + {x21} => 0000000000380000 {x19 x20 x21}
Debug: New V03 debug range: new var or location
							V120 in reg x22 is becoming live  [------]
							Live regs: 0000000000380000 {x19 x20 x21} + {x22} => 0000000000780000 {x19 x20 x21 x22}
							V04 in reg x23 is becoming live  [------]
							Live regs: 0000000000780000 {x19 x20 x21 x22} + {x23} => 0000000000F80000 {x19 x20 x21 x22 x23}
Debug: New V04 debug range: new var or location
							V119 in reg x24 is becoming live  [------]
							Live regs: 0000000000F80000 {x19 x20 x21 x22 x23} + {x24} => 0000000001F80000 {x19 x20 x21 x22 x23 x24}
							V121 in reg x25 is becoming live  [------]
							Live regs: 0000000001F80000 {x19 x20 x21 x22 x23 x24} + {x25} => 0000000003F80000 {x19 x20 x21 x22 x23 x24 x25}
							V05 in reg x26 is becoming live  [------]
							Live regs: 0000000003F80000 {x19 x20 x21 x22 x23 x24 x25} + {x26} => 0000000007F80000 {x19 x20 x21 x22 x23 x24 x25 x26}
Debug: New V05 debug range: new var or location
							Live regs: (unchanged) 0000000007F80000 {x19 x20 x21 x22 x23 x24 x25 x26}
							GC regs: (unchanged) 0000 {}
							Byref regs: (unchanged) 3300000 {x20 x21 x24 x25}

      L_M30837_BB03:
Saved:
      G_M30837_IG03:        ; offs=0x000008, size=0x001C, bbWeight=0.50, gcrefRegs=0000 {}, byrefRegs=300000 {x20 x21}, BB02 [0001], byref
Created:
      G_M30837_IG04:        ; offs=0x000024, size=0x0000, bbWeight=0.50, gcrefRegs=0000 {}
Label: G_M30837_IG04, GCvars=00000000000000000000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=3300000 {x20 x21 x24 x25}

Scope info: begin block BB03, IL range [011..03F)
Added IP mapping: 0x0011 STACK_EMPTY (G_M30837_IG04,ins#0,ofs#0) label
Generating: N037 (???,???) [001573] -----------                            IL_OFFSET void   INLRT @ 0x011[E-] REG NA
Generating: N039 (  1,  1) [000576] -----------                  t576 =    LCL_VAR   byref  V119 tmp87       u:1 x24 REG x24 $82
                                                                        /--*  t576   byref
Generating: N041 (  5,  4) [000009] DA---------                         *  STORE_LCL_VAR byref  V07 loc1          NA REG NA $VN.Void
Mapped BB03 to G_M30837_IG04
IN0009:             str     x24, [fp, #0x328]	// [V07 loc1]
Added IP mapping: 0x0018 STACK_EMPTY (G_M30837_IG04,ins#1,ofs#4)
Generating: N043 (???,???) [001574] -----------                            IL_OFFSET void   INLRT @ 0x018[E-] REG NA
Generating: N045 (  1,  1) [000010] -----------                   t10 =    LCL_VAR   byref  V119 tmp87       u:1 x24 REG x24 $82
                                                                        /--*  t10    byref
Generating: N047 (  1,  3) [001360] DA---------                         *  STORE_LCL_VAR long   V148 tmp116      d:1 x27 REG x27 $VN.Void
IN000a:             mov     x27, x24
							V148 in reg x27 is becoming live  [001360]
							Live regs: 0000000007F80000 {x19 x20 x21 x22 x23 x24 x25 x26} + {x27} => 000000000FF80000 {x19 x20 x21 x22 x23 x24 x25 x26 x27}
							Live vars after [001360]: {V02 V03 V04 V05 V119 V120 V121 V122} +{V148} => {V02 V03 V04 V05 V119 V120 V121 V122 V148}
Generating: N049 (  1,  1) [001361] -----------                 t1361 =    LCL_VAR   long   V148 tmp116      u:1 x27 (last use) REG x27 $1c0
                                                                        /--*  t1361  long
Generating: N051 (  2,  4) [000012] DA---------                         *  STORE_LCL_VAR long   V06 loc0         d:1 x28 REG x28 $VN.Void
							V148 in reg x27 is becoming dead  [001361]
							Live regs: 000000000FF80000 {x19 x20 x21 x22 x23 x24 x25 x26 x27} - {x27} => 0000000007F80000 {x19 x20 x21 x22 x23 x24 x25 x26}
							Live vars after [001361]: {V02 V03 V04 V05 V119 V120 V121 V122 V148} -{V148} => {V02 V03 V04 V05 V119 V120 V121 V122}
IN000b:             mov     x28, x27
							V06 in reg x28 is becoming live  [000012]
							Live regs: 0000000007F80000 {x19 x20 x21 x22 x23 x24 x25 x26} + {x28} => 0000000017F80000 {x19 x20 x21 x22 x23 x24 x25 x26 x28}
Debug: New V06 debug range: first
							Live vars after [000012]: {V02 V03 V04 V05 V119 V120 V121 V122} +{V06} => {V02 V03 V04 V05 V06 V119 V120 V121 V122}
Added IP mapping: 0x001B STACK_EMPTY (G_M30837_IG04,ins#3,ofs#12)
Generating: N053 (???,???) [001575] -----------                            IL_OFFSET void   INLRT @ 0x01B[E-] REG NA
Generating: N055 (  1,  1) [000581] -----------                  t581 =    LCL_VAR   byref  V121 tmp89       u:1 x25 REG x25 $83
                                                                        /--*  t581   byref
Generating: N057 (  5,  4) [000016] DA---------                         *  STORE_LCL_VAR byref  V09 loc3          NA REG NA $VN.Void
IN000c:             str     x25, [fp, #0x318]	// [V09 loc3]
Added IP mapping: 0x0022 STACK_EMPTY (G_M30837_IG04,ins#4,ofs#16)
Generating: N059 (???,???) [001576] -----------                            IL_OFFSET void   INLRT @ 0x022[E-] REG NA
Generating: N061 (  1,  1) [000017] -----------                   t17 =    LCL_VAR   byref  V121 tmp89       u:1 x25 REG x25 $83
                                                                        /--*  t17    byref
Generating: N063 (  1,  3) [001366] DA---------                         *  STORE_LCL_VAR long   V149 tmp117      d:1 x1 REG x1 $VN.Void
IN000d:             mov     x1, x25
							V149 in reg x1 is becoming live  [001366]
							Live regs: 0000000017F80000 {x19 x20 x21 x22 x23 x24 x25 x26 x28} + {x1} => 0000000017F80002 {x1 x19 x20 x21 x22 x23 x24 x25 x26 x28}
							Live vars after [001366]: {V02 V03 V04 V05 V06 V119 V120 V121 V122} +{V149} => {V02 V03 V04 V05 V06 V119 V120 V121 V122 V149}
Generating: N065 (  1,  1) [001367] -----------                 t1367 =    LCL_VAR   long   V149 tmp117      u:1 x1 (last use) REG x1 $1c1
                                                                        /--*  t1367  long
Generating: N067 (  2,  4) [000019] DA---------                         *  STORE_LCL_VAR long   V08 loc2         d:1 NA REG NA $VN.Void
							V149 in reg x1 is becoming dead  [001367]
							Live regs: 0000000017F80002 {x1 x19 x20 x21 x22 x23 x24 x25 x26 x28} - {x1} => 0000000017F80000 {x19 x20 x21 x22 x23 x24 x25 x26 x28}
							Live vars after [001367]: {V02 V03 V04 V05 V06 V119 V120 V121 V122 V149} -{V149} => {V02 V03 V04 V05 V06 V119 V120 V121 V122}
IN000e:             str     x1, [fp, #0x320]	// [V08 loc2]
Debug: New V08 debug range: first
							Live vars after [000019]: {V02 V03 V04 V05 V06 V119 V120 V121 V122} +{V08} => {V02 V03 V04 V05 V06 V08 V119 V120 V121 V122}
Added IP mapping: 0x0025 STACK_EMPTY (G_M30837_IG04,ins#6,ofs#24)
Generating: N069 (???,???) [001577] -----------                            IL_OFFSET void   INLRT @ 0x025[E-] REG NA
Generating: N071 (  1,  1) [000022] -----------                   t22 =    LCL_VAR   int    V120 tmp88       u:1 x22 REG x22 $100
Generating: N073 (  1,  2) [000023] -c---------                   t23 =    CNS_INT   int    -4 REG NA $4c
                                                                        /--*  t22    int
                                                                        +--*  t23    int
Generating: N075 (  3,  4) [000024] ----G------                   t24 = *  AND       int    REG x3 $181
IN000f:             and     w3, w22, #0xFFFFFFFC
                                                                        /--*  t24    int
Generating: N077 (  3,  4) [000025] DA--G-----#                         *  STORE_LCL_VAR int    V10 loc4         d:1 x3 REG x3 $VN.Void
IN0010:             str     w3, [fp, #0x314]	// [V10 loc4]
							V10 in reg x3 is becoming live  [000025]
							Live regs: 0000000017F80000 {x19 x20 x21 x22 x23 x24 x25 x26 x28} + {x3} => 0000000017F80008 {x3 x19 x20 x21 x22 x23 x24 x25 x26 x28}
Debug: New V10 debug range: first
							Live vars after [000025]: {V02 V03 V04 V05 V06 V08 V119 V120 V121 V122} +{V10} => {V02 V03 V04 V05 V06 V08 V10 V119 V120 V121 V122}
Added IP mapping: 0x0031 STACK_EMPTY (G_M30837_IG04,ins#8,ofs#32)
Generating: N079 (???,???) [001578] -----------                            IL_OFFSET void   INLRT @ 0x031[E-] REG NA
Generating: N081 (  1,  1) [000028] -----------                   t28 =    LCL_VAR   int    V122 tmp90       u:1 x19 REG x19 $101
                                                                        /--*  t28    int
Generating: N083 (  1,  3) [000029] DA--G-----#                         *  STORE_LCL_VAR int    V11 loc5         d:1 x4 REG x4 $VN.Void
IN0011:             sxtw    w4, w19
IN0012:             str     w4, [fp, #0x310]	// [V11 loc5]
							V11 in reg x4 is becoming live  [000029]
							Live regs: 0000000017F80008 {x3 x19 x20 x21 x22 x23 x24 x25 x26 x28} + {x4} => 0000000017F80018 {x3 x4 x19 x20 x21 x22 x23 x24 x25 x26 x28}
Debug: New V11 debug range: first
							Live vars after [000029]: {V02 V03 V04 V05 V06 V08 V10 V119 V120 V121 V122} +{V11} => {V02 V03 V04 V05 V06 V08 V10 V11 V119 V120 V121 V122}
Added IP mapping: 0x003A STACK_EMPTY (G_M30837_IG04,ins#10,ofs#40)
Generating: N085 (???,???) [001579] -----------                            IL_OFFSET void   INLRT @ 0x03A[E-] REG NA
Generating: N087 (  1,  1) [000030] ----------Z                   t30 =    LCL_VAR   int    V10 loc4         u:1 x3 REG x3 $181
                                                                        /--*  t30    int
Generating: N089 (  1,  3) [000031] DA---------                         *  STORE_LCL_VAR int    V12 loc6         d:1 x5 REG x5 $VN.Void
							V10 in reg x3 is becoming dead  [000030]
							Live regs: 0000000017F80018 {x3 x4 x19 x20 x21 x22 x23 x24 x25 x26 x28} - {x3} => 0000000017F80010 {x4 x19 x20 x21 x22 x23 x24 x25 x26 x28}
Debug: Closing V10 debug range.
Debug: New V10 debug range: not adjacent
IN0013:             sxtw    w5, w3
							V12 in reg x5 is becoming live  [000031]
							Live regs: 0000000017F80010 {x4 x19 x20 x21 x22 x23 x24 x25 x26 x28} + {x5} => 0000000017F80030 {x4 x5 x19 x20 x21 x22 x23 x24 x25 x26 x28}
Debug: New V12 debug range: first
							Live vars after [000031]: {V02 V03 V04 V05 V06 V08 V10 V11 V119 V120 V121 V122} +{V12} => {V02 V03 V04 V05 V06 V08 V10 V11 V12 V119 V120 V121 V122}
Added IP mapping: 0x003E STACK_EMPTY (G_M30837_IG04,ins#11,ofs#44)
Generating: N091 (???,???) [001580] -----------                            IL_OFFSET void   INL04 @ 0x000[E-] <- INLRT @ 0x03E[E-] REG NA
Generating: N093 (  1,  1) [000032] -----------                   t32 =    LCL_VAR   int    V12 loc6         u:1 x5 REG x5 $181
Generating: N095 (  1,  2) [000584] -c---------                  t584 =    CNS_INT   int    0x80000000 REG NA $49
                                                                        /--*  t32    int
                                                                        +--*  t584   int
Generating: N097 (  5,  6) [000586] -----------                         *  JTEST     void   REG NA
IN0014:             tbz     (LARGEJMP)L_M30837_BB05

Variable Live Range History Dump for BB03
V02 arg2: x20 [(G_M30837_IG03,ins#7,ofs#28), ...]
V03 arg3: x21 [(G_M30837_IG03,ins#7,ofs#28), ...]
V04 arg4: x23 [(G_M30837_IG03,ins#7,ofs#28), ...]
V05 arg5: x26 [(G_M30837_IG03,ins#7,ofs#28), ...]
V06 loc0: x28 [(G_M30837_IG04,ins#3,ofs#12), ...]
V08 loc2: fp[800] (1 slot) [(G_M30837_IG04,ins#6,ofs#24), ...]
V10 loc4: x3 [(G_M30837_IG04,ins#8,ofs#32), (G_M30837_IG04,ins#10,ofs#40)]; fp[788] (1 slot) [(G_M30837_IG04,ins#10,ofs#40), ...]
V11 loc5: x4 [(G_M30837_IG04,ins#10,ofs#40), ...]
V12 loc6: x5 [(G_M30837_IG04,ins#11,ofs#44), ...]

=============== Generating BB04 [0067] [03E..03F) (throw), preds={BB03} succs={} flags=0x00000000.14082011: i LIR IBC rare hascall gcsafe
BB04 IN (0)={} + ByrefExposed + GcHeap
     OUT(0)={}

Recording Var Locations at start of BB04
  <none>

Change life 00000000000000000000000040F5CF00 {V02 V03 V04 V05 V06 V08 V10 V11 V12 V119 V120 V121 V122} -> 00000000000000000000000000000000 {}
							V06 in reg x28 is becoming dead  [------]
							Live regs: (unchanged) 0000000000000000 {}
Debug: Closing V06 debug range.
							V122 in reg x19 is becoming dead  [------]
							Live regs: (unchanged) 0000000000000000 {}
							V12 in reg x5 is becoming dead  [------]
							Live regs: (unchanged) 0000000000000000 {}
Debug: Closing V12 debug range.
Debug: Closing V08 debug range.
							V02 in reg x20 is becoming dead  [------]
							Live regs: (unchanged) 0000000000000000 {}
Debug: Closing V02 debug range.
							V03 in reg x21 is becoming dead  [------]
							Live regs: (unchanged) 0000000000000000 {}
Debug: Closing V03 debug range.
							V120 in reg x22 is becoming dead  [------]
							Live regs: (unchanged) 0000000000000000 {}
							V04 in reg x23 is becoming dead  [------]
							Live regs: (unchanged) 0000000000000000 {}
Debug: Closing V04 debug range.
							V119 in reg x24 is becoming dead  [------]
							Live regs: (unchanged) 0000000000000000 {}
							V121 in reg x25 is becoming dead  [------]
							Live regs: (unchanged) 0000000000000000 {}
							V05 in reg x26 is becoming dead  [------]
							Live regs: (unchanged) 0000000000000000 {}
Debug: Closing V05 debug range.
Debug: Closing V10 debug range.
							V11 in reg x4 is becoming dead  [------]
							Live regs: (unchanged) 0000000000000000 {}
Debug: Closing V11 debug range.
							Live regs: (unchanged) 0000000000000000 {}
							GC regs: (unchanged) 0000 {}
							Byref regs: (unchanged) 0000 {}

      L_M30837_BB04:
Adding label due to BB weight difference: BBJ_COND BB03 with weight 50 different from BB04 with weight 0
Saved:
      G_M30837_IG04:        ; offs=0x000024, size=0x0034, bbWeight=0.50, gcrefRegs=0000 {}, byrefRegs=3300000 {x20 x21 x24 x25}, BB03 [0002], byref
Created:
      G_M30837_IG05:        ; offs=0x000058, size=0x0000, bbWeight=0, gcrefRegs=0000 {}
Label: G_M30837_IG05, GCvars=00000000000000000000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}

Scope info: begin block BB04, IL range [03E..03F)
genIPmappingAdd: ignoring duplicate IL offset 0x3e
Generating: N2303 (???,???) [001581] -----------                            IL_OFFSET void   INL04 @ 0x004[E-] <- INLRT @ 0x03E[E-] REG NA
Generating: N2305 (  1,  2) [000592] -----------                  t592 =    CNS_INT   int    40 REG x0 $70
Mapped BB04 to G_M30837_IG05
IN0015:             mov     w0, #40
                                                                        /--*  t592   int
Generating: N2307 (???,???) [001737] -----------                 t1737 = *  PUTARG_REG int    REG x0
Generating: N2309 (  3, 12) [001738] H----------                 t1738 =    CNS_INT(h) long   0xffff62cbf5e8 ftn REG x6
IN0016:             movz    x6, #0xF5E8      // code for System.ThrowHelper:ThrowArgumentOutOfRangeException(int)
IN0017:             movk    x6, #0x62CB LSL #16
IN0018:             movk    x6, #0xFFFF LSL #32
                                                                        /--*  t1738  long
Generating: N2311 (  6, 14) [001739] n---G------                 t1739 = *  IND       long   REG x6
IN0019:             ldr     x6, [x6]
                                                                        /--*  t1737  int    arg0 in x0
                                                                        +--*  t1739  long   control expr
Generating: N2313 ( 15,  5) [000593] --CXG------                         *  CALL      void   System.ThrowHelper:ThrowArgumentOutOfRangeException(int) REG NA $VN.Void
Call: GCvars=00000000000000000000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}
IN001a:             blr     x6
IN001b:             brk_unix #0

Variable Live Range History Dump for BB04
V02 arg2: x20 [(G_M30837_IG03,ins#7,ofs#28), (G_M30837_IG04,ins#12,ofs#52)]
V03 arg3: x21 [(G_M30837_IG03,ins#7,ofs#28), (G_M30837_IG04,ins#12,ofs#52)]
V04 arg4: x23 [(G_M30837_IG03,ins#7,ofs#28), (G_M30837_IG04,ins#12,ofs#52)]
V05 arg5: x26 [(G_M30837_IG03,ins#7,ofs#28), (G_M30837_IG04,ins#12,ofs#52)]
V06 loc0: x28 [(G_M30837_IG04,ins#3,ofs#12), (G_M30837_IG04,ins#12,ofs#52)]
V08 loc2: fp[800] (1 slot) [(G_M30837_IG04,ins#6,ofs#24), (G_M30837_IG04,ins#12,ofs#52)]
V10 loc4: fp[788] (1 slot) [(G_M30837_IG04,ins#10,ofs#40), (G_M30837_IG04,ins#12,ofs#52)]
V11 loc5: x4 [(G_M30837_IG04,ins#10,ofs#40), (G_M30837_IG04,ins#12,ofs#52)]
V12 loc6: x5 [(G_M30837_IG04,ins#11,ofs#44), (G_M30837_IG04,ins#12,ofs#52)]

=============== Generating BB05 [0068] [03E..04F) -> BB07(0.5),BB06(0.5) (cond), preds={BB03} succs={BB06,BB07} flags=0x00000000.04008011: i LIR IBC label
BB05 IN (13)={V06 V122 V12 V08 V02 V03 V120 V04 V119 V121 V05 V10 V11    } + ByrefExposed + GcHeap
     OUT(14)={V06 V122 V12 V08 V02 V03 V120 V04 V119 V121 V05 V10 V11 V13} + ByrefExposed + GcHeap

Recording Var Locations at start of BB05
  V06(x28)  V122(x19)  V12(x5)  V02(x20)  V03(x21)  V120(x22)  V04(x23)  V119(x24)  V121(x25)  V05(x26)  V11(x4)
Change life 00000000000000000000000000000000 {} -> 00000000000000000000000040F5CF00 {V02 V03 V04 V05 V06 V08 V10 V11 V12 V119 V120 V121 V122}
							V06 in reg x28 is becoming live  [------]
							Live regs: 0000000000000000 {} + {x28} => 0000000010000000 {x28}
Debug: New V06 debug range: new var or location
							V122 in reg x19 is becoming live  [------]
							Live regs: 0000000010000000 {x28} + {x19} => 0000000010080000 {x19 x28}
							V12 in reg x5 is becoming live  [------]
							Live regs: 0000000010080000 {x19 x28} + {x5} => 0000000010080020 {x5 x19 x28}
Debug: New V12 debug range: new var or location
Debug: New V08 debug range: new var or location
							V02 in reg x20 is becoming live  [------]
							Live regs: 0000000010080020 {x5 x19 x28} + {x20} => 0000000010180020 {x5 x19 x20 x28}
Debug: New V02 debug range: new var or location
							V03 in reg x21 is becoming live  [------]
							Live regs: 0000000010180020 {x5 x19 x20 x28} + {x21} => 0000000010380020 {x5 x19 x20 x21 x28}
Debug: New V03 debug range: new var or location
							V120 in reg x22 is becoming live  [------]
							Live regs: 0000000010380020 {x5 x19 x20 x21 x28} + {x22} => 0000000010780020 {x5 x19 x20 x21 x22 x28}
							V04 in reg x23 is becoming live  [------]
							Live regs: 0000000010780020 {x5 x19 x20 x21 x22 x28} + {x23} => 0000000010F80020 {x5 x19 x20 x21 x22 x23 x28}
Debug: New V04 debug range: new var or location
							V119 in reg x24 is becoming live  [------]
							Live regs: 0000000010F80020 {x5 x19 x20 x21 x22 x23 x28} + {x24} => 0000000011F80020 {x5 x19 x20 x21 x22 x23 x24 x28}
							V121 in reg x25 is becoming live  [------]
							Live regs: 0000000011F80020 {x5 x19 x20 x21 x22 x23 x24 x28} + {x25} => 0000000013F80020 {x5 x19 x20 x21 x22 x23 x24 x25 x28}
							V05 in reg x26 is becoming live  [------]
							Live regs: 0000000013F80020 {x5 x19 x20 x21 x22 x23 x24 x25 x28} + {x26} => 0000000017F80020 {x5 x19 x20 x21 x22 x23 x24 x25 x26 x28}
Debug: New V05 debug range: new var or location
Debug: New V10 debug range: new var or location
							V11 in reg x4 is becoming live  [------]
							Live regs: 0000000017F80020 {x5 x19 x20 x21 x22 x23 x24 x25 x26 x28} + {x4} => 0000000017F80030 {x4 x5 x19 x20 x21 x22 x23 x24 x25 x26 x28}
Debug: New V11 debug range: new var or location
							Live regs: (unchanged) 0000000017F80030 {x4 x5 x19 x20 x21 x22 x23 x24 x25 x26 x28}
							GC regs: (unchanged) 0000 {}
							Byref regs: (unchanged) 3300000 {x20 x21 x24 x25}

      L_M30837_BB05:
Saved:
      G_M30837_IG05:        ; offs=0x000058, size=0x001C, bbWeight=0, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB04 [0067], byref
Created:
      G_M30837_IG06:        ; offs=0x000074, size=0x0000, bbWeight=0.50, gcrefRegs=0000 {}
Label: G_M30837_IG06, GCvars=00000000000000000000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=3300000 {x20 x21 x24 x25}

Scope info: begin block BB05, IL range [03E..04F)
genIPmappingAdd: ignoring duplicate IL offset 0x3e
Generating: N101 (???,???) [001582] -----------                            IL_OFFSET void   INLRT @ 0x03E[E-] REG NA
Generating: N103 (  1,  1) [000587] ----------Z                  t587 =    LCL_VAR   int    V12 loc6         u:1 x5 REG x5 $181
Generating: N105 (  1,  2) [000588] -c---------                  t588 =    CNS_INT   int    2 REG NA $40
                                                                        /--*  t587   int
                                                                        +--*  t588   int
Generating: N107 (  3,  4) [000589] -----------                  t589 = *  RSH       int    REG x0 $183
Mapped BB05 to G_M30837_IG06
IN001c:             str     w5, [fp, #0x30C]	// [V12 loc6]
							V12 in reg x5 is becoming dead  [000587]
							Live regs: 0000000017F80030 {x4 x5 x19 x20 x21 x22 x23 x24 x25 x26 x28} - {x5} => 0000000017F80010 {x4 x19 x20 x21 x22 x23 x24 x25 x26 x28}
Debug: Closing V12 debug range.
Debug: New V12 debug range: not adjacent
IN001d:             asr     w0, w5, #2
Generating: N109 (  1,  2) [000590] -----------                  t590 =    CNS_INT   int    3 REG x6 $41
IN001e:             mov     w6, #3
                                                                        /--*  t589   int
                                                                        +--*  t590   int
Generating: N111 (  8,  9) [000591] -----------                  t591 = *  MUL       int    REG x6 $184
IN001f:             mul     w6, w0, w6
                                                                        /--*  t591   int
Generating: N113 ( 12, 12) [000035] DA--------#                         *  STORE_LCL_VAR int    V13 loc7         d:1 x6 REG x6 $VN.Void
IN0020:             str     w6, [fp, #0x308]	// [V13 loc7]
							V13 in reg x6 is becoming live  [000035]
							Live regs: 0000000017F80010 {x4 x19 x20 x21 x22 x23 x24 x25 x26 x28} + {x6} => 0000000017F80050 {x4 x6 x19 x20 x21 x22 x23 x24 x25 x26 x28}
Debug: New V13 debug range: first
							Live vars after [000035]: {V02 V03 V04 V05 V06 V08 V10 V11 V12 V119 V120 V121 V122} +{V13} => {V02 V03 V04 V05 V06 V08 V10 V11 V12 V13 V119 V120 V121 V122}
Added IP mapping: 0x0047 STACK_EMPTY (G_M30837_IG06,ins#5,ofs#20)
Generating: N115 (???,???) [001583] -----------                            IL_OFFSET void   INLRT @ 0x047[E-] REG NA
Generating: N117 (  1,  1) [000036] ----------Z                   t36 =    LCL_VAR   int    V11 loc5         u:1 x4 REG x4 $101
Generating: N119 (  3,  2) [000037] ----------Z                   t37 =    LCL_VAR   int    V13 loc7         u:1 x6 REG x6 $184
Generating: N121 (  1,  2) [000038] -c---------                   t38 =    CNS_INT   int    -2 REG NA $4d
                                                                        /--*  t37    int
                                                                        +--*  t38    int
Generating: N123 (  5,  5) [000039] -----------                   t39 = *  ADD       int    REG x0 $185
							V13 in reg x6 is becoming dead  [000037]
							Live regs: 0000000017F80050 {x4 x6 x19 x20 x21 x22 x23 x24 x25 x26 x28} - {x6} => 0000000017F80010 {x4 x19 x20 x21 x22 x23 x24 x25 x26 x28}
Debug: Closing V13 debug range.
Debug: New V13 debug range: not adjacent
IN0021:             sub     w0, w6, #2
                                                                        /--*  t36    int
                                                                        +--*  t39    int
Generating: N125 (  7,  7) [000040] -------N---                         *  CMP       void   REG NA
							V11 in reg x4 is becoming dead  [000036]
							Live regs: 0000000017F80010 {x4 x19 x20 x21 x22 x23 x24 x25 x26 x28} - {x4} => 0000000017F80000 {x19 x20 x21 x22 x23 x24 x25 x26 x28}
Debug: Closing V11 debug range.
Debug: New V11 debug range: not adjacent
IN0022:             cmp     w4, w0
Generating: N127 (  9,  9) [000041] -----------                            JCC       void   cond=SGE REG NA
IN0023:             bge     (LARGEJMP)L_M30837_BB07

Variable Live Range History Dump for BB05
V02 arg2: x20 [(G_M30837_IG05,ins#7,ofs#28), ...]
V03 arg3: x21 [(G_M30837_IG05,ins#7,ofs#28), ...]
V04 arg4: x23 [(G_M30837_IG05,ins#7,ofs#28), ...]
V05 arg5: x26 [(G_M30837_IG05,ins#7,ofs#28), ...]
V06 loc0: x28 [(G_M30837_IG05,ins#7,ofs#28), ...]
V08 loc2: fp[800] (1 slot) [(G_M30837_IG05,ins#7,ofs#28), ...]
V10 loc4: fp[788] (1 slot) [(G_M30837_IG05,ins#7,ofs#28), ...]
V11 loc5: x4 [(G_M30837_IG05,ins#7,ofs#28), (G_M30837_IG06,ins#6,ofs#24)]; fp[784] (1 slot) [(G_M30837_IG06,ins#6,ofs#24), ...]
V12 loc6: x5 [(G_M30837_IG05,ins#7,ofs#28), (G_M30837_IG06,ins#1,ofs#4)]; fp[780] (1 slot) [(G_M30837_IG06,ins#1,ofs#4), ...]
V13 loc7: x6 [(G_M30837_IG06,ins#5,ofs#20), (G_M30837_IG06,ins#5,ofs#20)]; fp[776] (1 slot) [(G_M30837_IG06,ins#5,ofs#20), ...]

=============== Generating BB06 [0003] [04F..057) -> BB07(1) (always), preds={BB05} succs={BB07} flags=0x00000000.10000011: i LIR hascall
BB06 IN (13)={V06 V122     V08 V02 V03 V120 V04 V119 V121 V05 V10 V11 V13} + ByrefExposed + GcHeap
     OUT(13)={V06 V122 V12 V08 V02 V03 V120 V04 V119 V121 V05 V10     V13} + ByrefExposed + GcHeap

Recording Var Locations at start of BB06
  V06(x28)  V122(x19)  V02(x20)  V03(x21)  V120(x22)  V04(x23)  V119(x24)  V121(x25)  V05(x26)
Change life 000000000000000000000000C0F5CF00 {V02 V03 V04 V05 V06 V08 V10 V11 V12 V13 V119 V120 V121 V122} -> 000000000000000000000000C0F5CB00 {V02 V03 V04 V05 V06 V08 V10 V11 V13 V119 V120 V121 V122}
Debug: Closing V12 debug range.
							Live regs: 0000000000000000 {} + {x19 x20 x21 x22 x23 x24 x25 x26 x28} => 0000000017F80000 {x19 x20 x21 x22 x23 x24 x25 x26 x28}
							GC regs: (unchanged) 0000 {}
							Byref regs: 0000 {} => 3300000 {x20 x21 x24 x25}

      L_M30837_BB06:

Scope info: begin block BB06, IL range [04F..057)
Generating: N131 (  3, 12) [000514] H----------                  t514 =    CNS_INT(h) long   0xffff6658dbb4 bbc REG x0 $200
Mapped BB06 to G_M30837_IG06
IN0024:             movz    x0, #0xDBB4
IN0025:             movk    x0, #0x6658 LSL #16
IN0026:             movk    x0, #0xFFFF LSL #32
                                                                        /--*  t514   long
Generating: N133 (???,???) [001740] -----------                 t1740 = *  PUTARG_REG long   REG x0
                                                                        /--*  t1740  long   arg0 in x0
Generating: N135 ( 17, 15) [000515] --CXG------                  u515 = *  CALL help int    CORINFO_HELP_COUNTPROFILE32 REG x0 $187
Call: GCvars=00000000000000000000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=3300000 {x20 x21 x24 x25}
[39] Rec call GC vars = 00000000000000000000000000000000
IN0027:             bl      CORINFO_HELP_COUNTPROFILE32
Added IP mapping: 0x004F STACK_EMPTY (G_M30837_IG06,ins#12,ofs#52) label
Generating: N137 (???,???) [001584] -----------                            IL_OFFSET void   INLRT @ 0x04F[E-] REG NA
Generating: N139 (  1,  1) [000498] ----------z                  t498 =    LCL_VAR   int    V11 loc5         u:1 x3 (last use) REG x3 $101
Generating: N141 (  1,  2) [000499] -----------                  t499 =    CNS_INT   int    0x55555556 REG x0 $41
IN0028:             movz    w0, #0x5556
IN0029:             movk    w0, #0x5555 LSL #16
                                                                        /--*  t499   int
                                                                        +--*  t498   int
Generating: N143 (???,???) [001741] -----------                 t1741 = *  MULHI     int    REG x4
IN002a:             ldr     w3, [fp, #0x310]	// [V11 loc5]
							V11 in reg x3 is becoming live  [000498]
							Live regs: 0000000017F80000 {x19 x20 x21 x22 x23 x24 x25 x26 x28} + {x3} => 0000000017F80008 {x3 x19 x20 x21 x22 x23 x24 x25 x26 x28}
							V11 in reg x3 is becoming dead  [000498]
							Live regs: 0000000017F80008 {x3 x19 x20 x21 x22 x23 x24 x25 x26 x28} - {x3} => 0000000017F80000 {x19 x20 x21 x22 x23 x24 x25 x26 x28}
Debug: Closing V11 debug range.
							Live vars after [000498]: {V02 V03 V04 V05 V06 V08 V10 V11 V13 V119 V120 V121 V122} -{V11} => {V02 V03 V04 V05 V06 V08 V10 V13 V119 V120 V121 V122}
IN002b:             smull   x4, w0, w3
IN002c:             asr     x4, x4, #32
                                                                        /--*  t1741  int
Generating: N145 (???,???) [001744] DA---------                         *  STORE_LCL_VAR int    V150 rat0         x4 REG x4
							V150 in reg x4 is becoming live  [001744]
							Live regs: 0000000017F80000 {x19 x20 x21 x22 x23 x24 x25 x26 x28} + {x4} => 0000000017F80010 {x4 x19 x20 x21 x22 x23 x24 x25 x26 x28}
							Live vars after [001744]: {V02 V03 V04 V05 V06 V08 V10 V13 V119 V120 V121 V122} +{V150} => {V02 V03 V04 V05 V06 V08 V10 V13 V119 V120 V121 V122 V150}
Generating: N147 (???,???) [001745] -----------                 t1745 =    LCL_VAR   int    V150 rat0         x4 (last use) REG x4
Generating: N149 (???,???) [001742] -c---------                 t1742 =    CNS_INT   int    31 REG NA
                                                                        /--*  t1745  int
                                                                        +--*  t1742  int
Generating: N151 (???,???) [001743] -c---------                 t1743 = *  RSZ       int    REG NA
Generating: N153 (???,???) [001746] -----------                 t1746 =    LCL_VAR   int    V150 rat0         x4 REG x4
                                                                        /--*  t1746  int
                                                                        +--*  t1743  int
Generating: N155 ( 22,  6) [000500] -----------                  t500 = *  ADD       int    REG x0
							V150 in reg x4 is becoming dead  [001745]
							Live regs: 0000000017F80010 {x4 x19 x20 x21 x22 x23 x24 x25 x26 x28} - {x4} => 0000000017F80000 {x19 x20 x21 x22 x23 x24 x25 x26 x28}
							Live vars after [001745]: {V02 V03 V04 V05 V06 V08 V10 V13 V119 V120 V121 V122 V150} -{V150} => {V02 V03 V04 V05 V06 V08 V10 V13 V119 V120 V121 V122}
IN002d:             add     w0, w4, w4,  LSR #31
Generating: N157 (  1,  2) [000501] -c---------                  t501 =    CNS_INT   int    2 REG NA $40
                                                                        /--*  t500   int
                                                                        +--*  t501   int
Generating: N159 ( 24,  9) [000502] -----------                  t502 = *  LSH       int    REG x5 $189
IN002e:             lsl     w5, w0, #2
                                                                        /--*  t502   int
Generating: N161 ( 24,  9) [000503] DA---------                         *  STORE_LCL_VAR int    V12 loc6         d:2 x5 REG x5 $VN.Void
							V12 in reg x5 is becoming live  [000503]
							Live regs: 0000000017F80000 {x19 x20 x21 x22 x23 x24 x25 x26 x28} + {x5} => 0000000017F80020 {x5 x19 x20 x21 x22 x23 x24 x25 x26 x28}
Debug: New V12 debug range: not adjacent
							Live vars after [000503]: {V02 V03 V04 V05 V06 V08 V10 V13 V119 V120 V121 V122} +{V12} => {V02 V03 V04 V05 V06 V08 V10 V12 V13 V119 V120 V121 V122}
Generating: N001 (  1,  1) [001919] ----------Z                 u1919 =    LCL_VAR   int    V12 loc6          x5 REG x5
IN002f:             str     w5, [fp, #0x30C]	// [V12 loc6]
							V12 in reg x5 is becoming dead  [001919]
							Live regs: 0000000017F80020 {x5 x19 x20 x21 x22 x23 x24 x25 x26 x28} - {x5} => 0000000017F80000 {x19 x20 x21 x22 x23 x24 x25 x26 x28}
Debug: Closing V12 debug range.
Debug: New V12 debug range: not adjacent

Variable Live Range History Dump for BB06
V02 arg2: x20 [(G_M30837_IG05,ins#7,ofs#28), ...]
V03 arg3: x21 [(G_M30837_IG05,ins#7,ofs#28), ...]
V04 arg4: x23 [(G_M30837_IG05,ins#7,ofs#28), ...]
V05 arg5: x26 [(G_M30837_IG05,ins#7,ofs#28), ...]
V06 loc0: x28 [(G_M30837_IG05,ins#7,ofs#28), ...]
V08 loc2: fp[800] (1 slot) [(G_M30837_IG05,ins#7,ofs#28), ...]
V10 loc4: fp[788] (1 slot) [(G_M30837_IG05,ins#7,ofs#28), ...]
V11 loc5: fp[784] (1 slot) [(G_M30837_IG06,ins#6,ofs#24), (G_M30837_IG06,ins#15,ofs#64)]
V12 loc6: fp[780] (1 slot) [(G_M30837_IG06,ins#1,ofs#4), (G_M30837_IG06,ins#8,ofs#36)]; x5 [(G_M30837_IG06,ins#19,ofs#80), (G_M30837_IG06,ins#20,ofs#84)]; fp[780] (1 slot) [(G_M30837_IG06,ins#20,ofs#84), ...]
V13 loc7: fp[776] (1 slot) [(G_M30837_IG06,ins#5,ofs#20), ...]

=============== Generating BB07 [0004] [057..074) -> BB20(0.5),BB08(0.5) (cond), preds={BB05,BB06} succs={BB08,BB20} flags=0x00000000.00008011: i LIR label
BB07 IN (13)={        V06 V122 V12 V08 V02 V03 V120     V04     V119 V121 V05 V10 V13} + ByrefExposed + GcHeap
     OUT(17)={V14 V15 V06 V122 V12 V08 V02 V03 V120 V17 V04 V16 V119 V121 V05 V10 V13} + ByrefExposed + GcHeap

Recording Var Locations at start of BB07
  V06(x28)  V122(x19)  V02(x20)  V03(x21)  V120(x22)  V04(x23)  V119(x24)  V121(x25)  V05(x26)
Liveness not changing: 00000000000000000000000080F5CF00 {V02 V03 V04 V05 V06 V08 V10 V12 V13 V119 V120 V121 V122}
							Live regs: 0000000000000000 {} + {x19 x20 x21 x22 x23 x24 x25 x26 x28} => 0000000017F80000 {x19 x20 x21 x22 x23 x24 x25 x26 x28}
							GC regs: (unchanged) 0000 {}
							Byref regs: 0000 {} => 3300000 {x20 x21 x24 x25}

      L_M30837_BB07:
Saved:
      G_M30837_IG06:        ; offs=0x000074, size=0x0054, bbWeight=0.50, gcrefRegs=0000 {}, byrefRegs=3300000 {x20 x21 x24 x25}, BB05 [0068], BB06 [0003], byref
Created:
      G_M30837_IG07:        ; offs=0x0000C8, size=0x0000, bbWeight=0.50, gcrefRegs=0000 {}
Label: G_M30837_IG07, GCvars=00000000000000000000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=3300000 {x20 x21 x24 x25}

Scope info: begin block BB07, IL range [057..074)
Added IP mapping: 0x0057 STACK_EMPTY (G_M30837_IG07,ins#0,ofs#0) label
Generating: N165 (???,???) [001585] -----------                            IL_OFFSET void   INLRT @ 0x057[E-] REG NA
Generating: N167 (  1,  1) [000042] -----------                   t42 =    LCL_VAR   long   V06 loc0         u:1 x28 REG x28 $1c0
                                                                        /--*  t42    long
Generating: N169 (  1,  3) [000043] DA---------                         *  STORE_LCL_VAR long   V14 loc8         d:1 NA REG NA $VN.Void
Mapped BB07 to G_M30837_IG07
IN0030:             str     x28, [fp, #0x300]	// [V14 loc8]
Debug: New V14 debug range: first
							Live vars after [000043]: {V02 V03 V04 V05 V06 V08 V10 V12 V13 V119 V120 V121 V122} +{V14} => {V02 V03 V04 V05 V06 V08 V10 V12 V13 V14 V119 V120 V121 V122}
Added IP mapping: 0x005A STACK_EMPTY (G_M30837_IG07,ins#1,ofs#4)
Generating: N171 (???,???) [001586] -----------                            IL_OFFSET void   INLRT @ 0x05A[E-] REG NA
Generating: N173 (  1,  1) [000044] ----------z                   t44 =    LCL_VAR   long   V08 loc2         u:1 x2 REG x2 $1c1
                                                                        /--*  t44    long
Generating: N175 (  1,  3) [000045] DA---------                         *  STORE_LCL_VAR long   V15 loc9         d:1 NA REG NA $VN.Void
IN0031:             ldr     x2, [fp, #0x320]	// [V08 loc2]
Debug: Closing V08 debug range.
Debug: New V08 debug range: not adjacent
							V08 in reg x2 is becoming live  [000044]
							Live regs: 0000000017F80000 {x19 x20 x21 x22 x23 x24 x25 x26 x28} + {x2} => 0000000017F80004 {x2 x19 x20 x21 x22 x23 x24 x25 x26 x28}
IN0032:             str     x2, [fp, #0x2F8]	// [V15 loc9]
Debug: New V15 debug range: first
							Live vars after [000045]: {V02 V03 V04 V05 V06 V08 V10 V12 V13 V14 V119 V120 V121 V122} +{V15} => {V02 V03 V04 V05 V06 V08 V10 V12 V13 V14 V15 V119 V120 V121 V122}
Added IP mapping: 0x005D STACK_EMPTY (G_M30837_IG07,ins#3,ofs#12)
Generating: N177 (???,???) [001587] -----------                            IL_OFFSET void   INLRT @ 0x05D[E-] REG NA
Generating: N179 (  1,  1) [000046] -----------                   t46 =    LCL_VAR   long   V06 loc0         u:1 x28 REG x28 $1c0
Generating: N181 (  1,  1) [000047] ----------#                   t47 =    LCL_VAR   int    V10 loc4         u:1 x3 REG x3 $181
                                                                        /--*  t47    int
Generating: N183 (  2,  3) [000048] -c-------U-                   t48 = *  CAST      long <- ulong <- uint REG NA $1c2
                                                                        /--*  t46    long
                                                                        +--*  t48    long
Generating: N185 (  4,  5) [000049] -----------                   t49 = *  ADD       long   REG x9 $1c3
IN0033:             ldr     w3, [fp, #0x314]	// [V10 loc4]
IN0034:             add     x9, x28, w3, UXTW
                                                                        /--*  t49    long
Generating: N187 (  4,  5) [000050] DA---------                         *  STORE_LCL_VAR long   V16 loc10        d:1 NA REG NA $VN.Void
IN0035:             str     x9, [fp, #0x2F0]	// [V16 loc10]
Debug: New V16 debug range: first
							Live vars after [000050]: {V02 V03 V04 V05 V06 V08 V10 V12 V13 V14 V15 V119 V120 V121 V122} +{V16} => {V02 V03 V04 V05 V06 V08 V10 V12 V13 V14 V15 V16 V119 V120 V121 V122}
Added IP mapping: 0x0064 STACK_EMPTY (G_M30837_IG07,ins#6,ofs#24)
Generating: N189 (???,???) [001588] -----------                            IL_OFFSET void   INLRT @ 0x064[E-] REG NA
Generating: N191 (  1,  1) [000051] -----------                   t51 =    LCL_VAR   long   V06 loc0         u:1 x28 REG x28 $1c0
Generating: N193 (  1,  1) [000052] ----------z                   t52 =    LCL_VAR   int    V12 loc6         u:3 x5 REG x5 $300
                                                                        /--*  t52    int
Generating: N195 (  2,  3) [000053] -c-------U-                   t53 = *  CAST      long <- ulong <- uint REG NA $1c4
                                                                        /--*  t51    long
                                                                        +--*  t53    long
Generating: N197 (  4,  5) [000054] -----------                   t54 = *  ADD       long   REG x10 $1c5
IN0036:             ldr     w5, [fp, #0x30C]	// [V12 loc6]
Debug: Closing V12 debug range.
Debug: New V12 debug range: not adjacent
							V12 in reg x5 is becoming live  [000052]
							Live regs: 0000000017F80004 {x2 x19 x20 x21 x22 x23 x24 x25 x26 x28} + {x5} => 0000000017F80024 {x2 x5 x19 x20 x21 x22 x23 x24 x25 x26 x28}
IN0037:             add     x10, x28, w5, UXTW
                                                                        /--*  t54    long
Generating: N199 (  4,  5) [000055] DA---------                         *  STORE_LCL_VAR long   V17 loc11        d:1 x10 REG x10 $VN.Void
							V17 in reg x10 is becoming live  [000055]
							Live regs: 0000000017F80024 {x2 x5 x19 x20 x21 x22 x23 x24 x25 x26 x28} + {x10} => 0000000017F80424 {x2 x5 x10 x19 x20 x21 x22 x23 x24 x25 x26 x28}
Debug: New V17 debug range: first
							Live vars after [000055]: {V02 V03 V04 V05 V06 V08 V10 V12 V13 V14 V15 V16 V119 V120 V121 V122} +{V17} => {V02 V03 V04 V05 V06 V08 V10 V12 V13 V14 V15 V16 V17 V119 V120 V121 V122}
Added IP mapping: 0x006B STACK_EMPTY (G_M30837_IG07,ins#8,ofs#32)
Generating: N201 (???,???) [001589] -----------                            IL_OFFSET void   INLRT @ 0x06B[E-] REG NA
Generating: N203 (  1,  1) [000056] -----------                   t56 =    LCL_VAR   int    V12 loc6         u:3 x5 REG x5 $300
Generating: N205 (  1,  2) [000057] -c---------                   t57 =    CNS_INT   int    24 REG NA $4f
                                                                        /--*  t56    int
                                                                        +--*  t57    int
Generating: N207 (  3,  4) [000058] -------N---                         *  CMP       void   REG NA
IN0038:             cmp     w5, #24
Generating: N209 (  5,  6) [000059] -----------                            JCC       void   cond=SLT REG NA
IN0039:             blt     (LARGEJMP)L_M30837_BB20

Variable Live Range History Dump for BB07
V02 arg2: x20 [(G_M30837_IG05,ins#7,ofs#28), ...]
V03 arg3: x21 [(G_M30837_IG05,ins#7,ofs#28), ...]
V04 arg4: x23 [(G_M30837_IG05,ins#7,ofs#28), ...]
V05 arg5: x26 [(G_M30837_IG05,ins#7,ofs#28), ...]
V06 loc0: x28 [(G_M30837_IG05,ins#7,ofs#28), ...]
V08 loc2: fp[800] (1 slot) [(G_M30837_IG05,ins#7,ofs#28), (G_M30837_IG07,ins#2,ofs#8)]; x2 [(G_M30837_IG07,ins#2,ofs#8), ...]
V10 loc4: fp[788] (1 slot) [(G_M30837_IG05,ins#7,ofs#28), ...]
V12 loc6: fp[780] (1 slot) [(G_M30837_IG06,ins#20,ofs#84), (G_M30837_IG07,ins#7,ofs#28)]; x5 [(G_M30837_IG07,ins#7,ofs#28), ...]
V13 loc7: fp[776] (1 slot) [(G_M30837_IG06,ins#5,ofs#20), ...]
V14 loc8: fp[768] (1 slot) [(G_M30837_IG07,ins#1,ofs#4), ...]
V15 loc9: fp[760] (1 slot) [(G_M30837_IG07,ins#3,ofs#12), ...]
V16 loc10: fp[752] (1 slot) [(G_M30837_IG07,ins#6,ofs#24), ...]
V17 loc11: x10 [(G_M30837_IG07,ins#8,ofs#32), ...]

=============== Generating BB08 [0005] [074..09C) -> BB25(0.5),BB09(0.5) (cond), preds={BB07} succs={BB09,BB25} flags=0x00000000.00000011: i LIR
BB08 IN (17)={V14 V15 V06 V122 V12 V08     V02 V03 V120 V17 V04 V16 V119 V121 V05 V10 V13} + ByrefExposed + GcHeap
     OUT(18)={V14 V15 V06 V122 V12 V08 V27 V02 V03 V120 V17 V04 V16 V119 V121 V05 V10 V13} + ByrefExposed + GcHeap

Recording Var Locations at start of BB08
  V06(x28)  V122(x19)  V12(x5)  V08(x2)  V02(x20)  V03(x21)  V120(x22)  V17(x10)  V04(x23)  V119(x24)  V121(x25)  V05(x26)
Liveness not changing: 00000000000000000000000080FFCF03 {V02 V03 V04 V05 V06 V08 V10 V12 V13 V14 V15 V16 V17 V119 V120 V121 V122}
							Live regs: 0000000000000000 {} + {x2 x5 x10 x19 x20 x21 x22 x23 x24 x25 x26 x28} => 0000000017F80424 {x2 x5 x10 x19 x20 x21 x22 x23 x24 x25 x26 x28}
							GC regs: (unchanged) 0000 {}
							Byref regs: 0000 {} => 3300000 {x20 x21 x24 x25}

      L_M30837_BB08:

Scope info: begin block BB08, IL range [074..09C)
Added IP mapping: 0x0088 STACK_EMPTY (G_M30837_IG07,ins#10,ofs#44) label
Generating: N213 (???,???) [001590] -----------                            IL_OFFSET void   INLRT @ 0x088[E-] REG NA
Generating: N215 (  1,  1) [000448] ----------Z                  t448 =    LCL_VAR   long   V17 loc11        u:1 x10 REG x10 $1c5
Generating: N217 (  1,  2) [000450] -c---------                  t450 =    CNS_INT   long   -66 REG NA $381
                                                                        /--*  t448   long
                                                                        +--*  t450   long
Generating: N219 (  3,  4) [000451] -----------                  t451 = *  ADD       long   REG x11 $1c6
Mapped BB08 to G_M30837_IG07
IN003a:             str     x10, [fp, #0x2E8]	// [V17 loc11]
							V17 in reg x10 is becoming dead  [000448]
							Live regs: 0000000017F80424 {x2 x5 x10 x19 x20 x21 x22 x23 x24 x25 x26 x28} - {x10} => 0000000017F80024 {x2 x5 x19 x20 x21 x22 x23 x24 x25 x26 x28}
Debug: Closing V17 debug range.
Debug: New V17 debug range: not adjacent
IN003b:             sub     x11, x10, #66
                                                                        /--*  t451   long
Generating: N221 (  3,  4) [000452] DA---------                         *  STORE_LCL_VAR long   V27 loc21        d:1 x11 REG x11 $VN.Void
							V27 in reg x11 is becoming live  [000452]
							Live regs: 0000000017F80024 {x2 x5 x19 x20 x21 x22 x23 x24 x25 x26 x28} + {x11} => 0000000017F80824 {x2 x5 x11 x19 x20 x21 x22 x23 x24 x25 x26 x28}
Debug: New V27 debug range: first
							Live vars after [000452]: {V02 V03 V04 V05 V06 V08 V10 V12 V13 V14 V15 V16 V17 V119 V120 V121 V122} +{V27} => {V02 V03 V04 V05 V06 V08 V10 V12 V13 V14 V15 V16 V17 V27 V119 V120 V121 V122}
Added IP mapping: 0x0096 STACK_EMPTY (G_M30837_IG07,ins#12,ofs#52)
Generating: N223 (???,???) [001591] -----------                            IL_OFFSET void   INLRT @ 0x096[E-] REG NA
Generating: N225 (  1,  1) [000456] ----------Z                  t456 =    LCL_VAR   long   V27 loc21        u:1 x11 REG x11 $1c6
Generating: N227 (  1,  1) [000457] -----------                  t457 =    LCL_VAR   long   V06 loc0         u:1 x28 REG x28 $1c0
                                                                        /--*  t456   long
                                                                        +--*  t457   long
Generating: N229 (  3,  3) [000458] -------N-U-                         *  CMP       void   REG NA
IN003c:             str     x11, [fp, #0x2C0]	// [V27 loc21]
							V27 in reg x11 is becoming dead  [000456]
							Live regs: 0000000017F80824 {x2 x5 x11 x19 x20 x21 x22 x23 x24 x25 x26 x28} - {x11} => 0000000017F80024 {x2 x5 x19 x20 x21 x22 x23 x24 x25 x26 x28}
Debug: Closing V27 debug range.
Debug: New V27 debug range: not adjacent
IN003d:             cmp     x11, x28
Generating: N231 (  5,  5) [000459] -----------                            JCC       void   cond=ULT REG NA
IN003e:             blo     (LARGEJMP)L_M30837_BB25

Variable Live Range History Dump for BB08
V02 arg2: x20 [(G_M30837_IG05,ins#7,ofs#28), ...]
V03 arg3: x21 [(G_M30837_IG05,ins#7,ofs#28), ...]
V04 arg4: x23 [(G_M30837_IG05,ins#7,ofs#28), ...]
V05 arg5: x26 [(G_M30837_IG05,ins#7,ofs#28), ...]
V06 loc0: x28 [(G_M30837_IG05,ins#7,ofs#28), ...]
V08 loc2: x2 [(G_M30837_IG07,ins#2,ofs#8), ...]
V10 loc4: fp[788] (1 slot) [(G_M30837_IG05,ins#7,ofs#28), ...]
V12 loc6: x5 [(G_M30837_IG07,ins#7,ofs#28), ...]
V13 loc7: fp[776] (1 slot) [(G_M30837_IG06,ins#5,ofs#20), ...]
V14 loc8: fp[768] (1 slot) [(G_M30837_IG07,ins#1,ofs#4), ...]
V15 loc9: fp[760] (1 slot) [(G_M30837_IG07,ins#3,ofs#12), ...]
V16 loc10: fp[752] (1 slot) [(G_M30837_IG07,ins#6,ofs#24), ...]
V17 loc11: x10 [(G_M30837_IG07,ins#8,ofs#32), (G_M30837_IG07,ins#11,ofs#48)]; fp[744] (1 slot) [(G_M30837_IG07,ins#11,ofs#48), ...]
V27 loc21: x11 [(G_M30837_IG07,ins#12,ofs#52), (G_M30837_IG07,ins#13,ofs#56)]; fp[704] (1 slot) [(G_M30837_IG07,ins#13,ofs#56), ...]

=============== Generating BB09 [0009] [09C..0AD) -> BB10(1) (always), preds={BB08} succs={BB10} flags=0x00000000.00000011: i LIR
BB09 IN (16)={        V06 V122 V12 V08 V27 V02 V03 V120 V17 V04 V16 V119 V121 V05 V10 V13                            } + ByrefExposed + GcHeap
     OUT(25)={V45 V46 V06 V122 V12 V08 V27 V02 V03 V120 V17 V04 V16 V119 V121 V05 V10 V13 V47 V131 V132 V133 V134 V135 V136} + ByrefExposed + GcHeap

Recording Var Locations at start of BB09
  V06(x28)  V122(x19)  V12(x5)  V08(x2)  V02(x20)  V03(x21)  V120(x22)  V04(x23)  V119(x24)  V121(x25)  V05(x26)
Change life 00000000000000000000000080FFDF03 {V02 V03 V04 V05 V06 V08 V10 V12 V13 V14 V15 V16 V17 V27 V119 V120 V121 V122} -> 00000000000000000000000080FFDF00 {V02 V03 V04 V05 V06 V08 V10 V12 V13 V16 V17 V27 V119 V120 V121 V122}
Debug: Closing V14 debug range.
Debug: Closing V15 debug range.
							Live regs: 0000000000000000 {} + {x2 x5 x19 x20 x21 x22 x23 x24 x25 x26 x28} => 0000000017F80024 {x2 x5 x19 x20 x21 x22 x23 x24 x25 x26 x28}
							GC regs: (unchanged) 0000 {}
							Byref regs: 0000 {} => 3300000 {x20 x21 x24 x25}

      L_M30837_BB09:

Scope info: begin block BB09, IL range [09C..0AD)
Added IP mapping: 0x009C STACK_EMPTY (G_M30837_IG07,ins#15,ofs#68) label
Generating: N235 (???,???) [001592] -----------                            IL_OFFSET void   INL05 @ 0x000[E-] <- INLRT @ 0x09C[E-] REG NA
genIPmappingAdd: ignoring duplicate IL offset 0x9c
Generating: N237 (???,???) [001593] -----------                            IL_OFFSET void   INL05 @ 0x00F[E-] <- INLRT @ 0x09C[E-] REG NA
genIPmappingAdd: ignoring duplicate IL offset 0x9c
Generating: N239 (???,???) [001594] -----------                            IL_OFFSET void   INL05 @ 0x01E[E-] <- INLRT @ 0x09C[E-] REG NA
genIPmappingAdd: ignoring duplicate IL offset 0x9c
Generating: N241 (???,???) [001595] -----------                            IL_OFFSET void   INL05 @ 0x035[E-] <- INLRT @ 0x09C[E-] REG NA
genIPmappingAdd: ignoring duplicate IL offset 0x9c
Generating: N243 (???,???) [001596] -----------                            IL_OFFSET void   INL05 @ 0x050[E-] <- INLRT @ 0x09C[E-] REG NA
genIPmappingAdd: ignoring duplicate IL offset 0x9c
Generating: N245 (???,???) [001597] -----------                            IL_OFFSET void   INL05 @ 0x070[E-] <- INLRT @ 0x09C[E-] REG NA
genIPmappingAdd: ignoring duplicate IL offset 0x9c
Generating: N247 (???,???) [001598] -----------                            IL_OFFSET void   INL05 @ 0x08C[E-] <- INLRT @ 0x09C[E-] REG NA
genIPmappingAdd: ignoring duplicate IL offset 0x9c
Generating: N249 (???,???) [001599] -----------                            IL_OFFSET void   INL05 @ 0x0AC[E-] <- INLRT @ 0x09C[E-] REG NA
genIPmappingAdd: ignoring duplicate IL offset 0x9c
Generating: N251 (???,???) [001600] -----------                            IL_OFFSET void   INL05 @ 0x0C8[E-] <- INLRT @ 0x09C[E-] REG NA
Generating: N253 (  1,  1) [000644] -----------                  t644 =    LCL_VAR   long   V06 loc0         u:1 x28 REG x28 $1c0
                                                                        /--*  t644   long
Generating: N255 (  1,  3) [000645] DA--G------                         *  STORE_LCL_VAR long   V45 tmp13        d:1 x13 REG x13 $VN.Void
Mapped BB09 to G_M30837_IG07
IN003f:             mov     x13, x28
							V45 in reg x13 is becoming live  [000645]
							Live regs: 0000000017F80024 {x2 x5 x19 x20 x21 x22 x23 x24 x25 x26 x28} + {x13} => 0000000017F82024 {x2 x5 x13 x19 x20 x21 x22 x23 x24 x25 x26 x28}
							Live vars after [000645]: {V02 V03 V04 V05 V06 V08 V10 V12 V13 V16 V17 V27 V119 V120 V121 V122} +{V45} => {V02 V03 V04 V05 V06 V08 V10 V12 V13 V16 V17 V27 V45 V119 V120 V121 V122}
genIPmappingAdd: ignoring duplicate IL offset 0x9c
Generating: N257 (???,???) [001601] -----------                            IL_OFFSET void   INL05 @ 0x0CC[E-] <- INLRT @ 0x09C[E-] REG NA
Generating: N259 (  1,  1) [000647] ----------Z                  t647 =    LCL_VAR   long   V08 loc2         u:1 x2 REG x2 $1c1
                                                                        /--*  t647   long
Generating: N261 (  1,  3) [000648] DA--G------                         *  STORE_LCL_VAR long   V46 tmp14        d:1 NA REG NA $VN.Void
							V08 in reg x2 is becoming dead  [000647]
							Live regs: 0000000017F82024 {x2 x5 x13 x19 x20 x21 x22 x23 x24 x25 x26 x28} - {x2} => 0000000017F82020 {x5 x13 x19 x20 x21 x22 x23 x24 x25 x26 x28}
Debug: Closing V08 debug range.
Debug: New V08 debug range: not adjacent
IN0040:             str     x2, [fp, #0x2A8]	// [V46 tmp14]
							Live vars after [000648]: {V02 V03 V04 V05 V06 V08 V10 V12 V13 V16 V17 V27 V45 V119 V120 V121 V122} +{V46} => {V02 V03 V04 V05 V06 V08 V10 V12 V13 V16 V17 V27 V45 V46 V119 V120 V121 V122}
genIPmappingAdd: ignoring duplicate IL offset 0x9c
Generating: N263 (???,???) [001602] -----------                            IL_OFFSET void   INL05 @ 0x0D0[E-] <- INLRT @ 0x09C[E-] REG NA
Generating: N265 (  1,  2) [000649] -c---------                  t649 =    CNS_INT   int    63 REG NA $50
                                                                        /--*  t649   int
Generating: N267 (  2,  3) [000650] -----------                  t650 = *  HWINTRINSIC simd16 ubyte DuplicateToVector128 REG d8 $400
IN0041:             movi    v8.16b, #0x3F
                                                                        /--*  t650   simd16
Generating: N269 (  2,  3) [000651] DA---------                         *  STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V47 tmp15        d:1 NA REG NA $VN.Void
IN0042:             str     q8, [fp, #0x290]	// [V47 tmp15]
							Live vars after [000651]: {V02 V03 V04 V05 V06 V08 V10 V12 V13 V16 V17 V27 V45 V46 V119 V120 V121 V122} +{V47} => {V02 V03 V04 V05 V06 V08 V10 V12 V13 V16 V17 V27 V45 V46 V47 V119 V120 V121 V122}
genIPmappingAdd: ignoring duplicate IL offset 0x9c
Generating: N271 (???,???) [001603] -----------                            IL_OFFSET void   INL06 @ 0x000[E-] <- INL05 @ 0x0D9[E-] <- INLRT @ 0x09C[E-] REG NA
genIPmappingAdd: ignoring duplicate IL offset 0x9c
Generating: N273 (???,???) [001604] -----------                            IL_OFFSET void   INL06 @ 0x007[E-] <- INL05 @ 0x0D9[E-] <- INLRT @ 0x09C[E-] REG NA
genIPmappingAdd: ignoring duplicate IL offset 0x9c
Generating: N275 (???,???) [001605] -----------                            IL_OFFSET void   INL06 @ 0x00E[E-] <- INL05 @ 0x0D9[E-] <- INLRT @ 0x09C[E-] REG NA
Generating: N277 (  3,  2) [001509] -----------                 t1509 =    CNS_VEC   simd16<0xffffffff, 0xffffffff, 0x3effffff, 0x3fffffff> REG d9 $3c1
Increasing data section alignment from 4 to 16 for type simd16
IN0043:             ldr     q9, (LARGELDC)[@RWD00]
                                                                        /--*  t1509  simd16
Generating: N279 (  3,  3) [000885] DA--------#                         *  STORE_LCL_VAR simd16 V131 tmp99       d:1 d9 REG d9 $VN.Void
IN0044:             str     q9, [fp, #0xE0]	// [V131 tmp99]
							V131 in reg d9 is becoming live  [000885]
							Live regs: 0000000017F82020 {x5 x13 x19 x20 x21 x22 x23 x24 x25 x26 x28} + {d9} => 0000020017F82020 {x5 x13 x19 x20 x21 x22 x23 x24 x25 x26 x28 d9}
							Live vars after [000885]: {V02 V03 V04 V05 V06 V08 V10 V12 V13 V16 V17 V27 V45 V46 V47 V119 V120 V121 V122} +{V131} => {V02 V03 V04 V05 V06 V08 V10 V12 V13 V16 V17 V27 V45 V46 V47 V119 V120 V121 V122 V131}
genIPmappingAdd: ignoring duplicate IL offset 0x9c
Generating: N281 (???,???) [001606] -----------                            IL_OFFSET void   INL06 @ 0x015[E-] <- INL05 @ 0x0D9[E-] <- INLRT @ 0x09C[E-] REG NA
Generating: N283 (  3,  2) [001510] -----------                 t1510 =    CNS_VEC   simd16<0x37363534, 0x3b3a3938, 0xffff3d3c, 0xffffffff> REG d10 $3c2
IN0045:             ldr     q10, (LARGELDC)[@RWD16]
                                                                        /--*  t1510  simd16
Generating: N285 (  3,  3) [000888] DA--------#                         *  STORE_LCL_VAR simd16 V132 tmp100      d:1 d10 REG d10 $VN.Void
IN0046:             str     q10, [fp, #0xD0]	// [V132 tmp100]
							V132 in reg d10 is becoming live  [000888]
							Live regs: 0000020017F82020 {x5 x13 x19 x20 x21 x22 x23 x24 x25 x26 x28 d9} + {d10} => 0000060017F82020 {x5 x13 x19 x20 x21 x22 x23 x24 x25 x26 x28 d9 d10}
							Live vars after [000888]: {V02 V03 V04 V05 V06 V08 V10 V12 V13 V16 V17 V27 V45 V46 V47 V119 V120 V121 V122 V131} +{V132} => {V02 V03 V04 V05 V06 V08 V10 V12 V13 V16 V17 V27 V45 V46 V47 V119 V120 V121 V122 V131 V132}
genIPmappingAdd: ignoring duplicate IL offset 0x9c
Generating: N287 (???,???) [001607] -----------                            IL_OFFSET void   INL07 @ 0x000[E-] <- INL05 @ 0x0E4[E-] <- INLRT @ 0x09C[E-] REG NA
Generating: N289 (  3,  2) [001511] -----------                 t1511 =    CNS_VEC   simd16<0x0100ff00, 0x05040302, 0x09080706, 0x0d0c0b0a> REG d11 $3c3
IN0047:             ldr     q11, (LARGELDC)[@RWD32]
                                                                        /--*  t1511  simd16
Generating: N291 (  3,  3) [000892] DA---------                         *  STORE_LCL_VAR simd16 V133 tmp101      d:1 NA REG NA $VN.Void
IN0048:             str     q11, [fp, #0xC0]	// [V133 tmp101]
							Live vars after [000892]: {V02 V03 V04 V05 V06 V08 V10 V12 V13 V16 V17 V27 V45 V46 V47 V119 V120 V121 V122 V131 V132} +{V133} => {V02 V03 V04 V05 V06 V08 V10 V12 V13 V16 V17 V27 V45 V46 V47 V119 V120 V121 V122 V131 V132 V133}
genIPmappingAdd: ignoring duplicate IL offset 0x9c
Generating: N293 (???,???) [001608] -----------                            IL_OFFSET void   INL07 @ 0x007[E-] <- INL05 @ 0x0E4[E-] <- INLRT @ 0x09C[E-] REG NA
Generating: N295 (  3,  2) [001512] -----------                 t1512 =    CNS_VEC   simd16<0x11100f0e, 0x15141312, 0x19181716, 0xffffffff> REG d12 $3c4
IN0049:             ldr     q12, (LARGELDC)[@RWD48]
                                                                        /--*  t1512  simd16
Generating: N297 (  3,  3) [000895] DA---------                         *  STORE_LCL_VAR simd16 V134 tmp102      d:1 NA REG NA $VN.Void
IN004a:             str     q12, [fp, #0xB0]	// [V134 tmp102]
							Live vars after [000895]: {V02 V03 V04 V05 V06 V08 V10 V12 V13 V16 V17 V27 V45 V46 V47 V119 V120 V121 V122 V131 V132 V133} +{V134} => {V02 V03 V04 V05 V06 V08 V10 V12 V13 V16 V17 V27 V45 V46 V47 V119 V120 V121 V122 V131 V132 V133 V134}
genIPmappingAdd: ignoring duplicate IL offset 0x9c
Generating: N299 (???,???) [001609] -----------                            IL_OFFSET void   INL07 @ 0x00E[E-] <- INL05 @ 0x0E4[E-] <- INLRT @ 0x09C[E-] REG NA
Generating: N301 (  3,  2) [001513] -----------                 t1513 =    CNS_VEC   simd16<0x1b1affff, 0x1f1e1d1c, 0x23222120, 0x27262524> REG d13 $3c5
IN004b:             ldr     q13, (LARGELDC)[@RWD64]
                                                                        /--*  t1513  simd16
Generating: N303 (  3,  3) [000898] DA---------                         *  STORE_LCL_VAR simd16 V135 tmp103      d:1 NA REG NA $VN.Void
IN004c:             str     q13, [fp, #0xA0]	// [V135 tmp103]
							Live vars after [000898]: {V02 V03 V04 V05 V06 V08 V10 V12 V13 V16 V17 V27 V45 V46 V47 V119 V120 V121 V122 V131 V132 V133 V134} +{V135} => {V02 V03 V04 V05 V06 V08 V10 V12 V13 V16 V17 V27 V45 V46 V47 V119 V120 V121 V122 V131 V132 V133 V134 V135}
genIPmappingAdd: ignoring duplicate IL offset 0x9c
Generating: N305 (???,???) [001610] -----------                            IL_OFFSET void   INL07 @ 0x015[E-] <- INL05 @ 0x0E4[E-] <- INLRT @ 0x09C[E-] REG NA
Generating: N307 (  3,  2) [001514] -----------                 t1514 =    CNS_VEC   simd16<0x2b2a2928, 0x2f2e2d2c, 0x33323130, 0xffffffff> REG d14 $3c6
IN004d:             ldr     q14, (LARGELDC)[@RWD80]
                                                                        /--*  t1514  simd16
Generating: N309 (  3,  3) [000901] DA---------                         *  STORE_LCL_VAR simd16 V136 tmp104      d:1 NA REG NA $VN.Void
IN004e:             str     q14, [fp, #0x90]	// [V136 tmp104]
							Live vars after [000901]: {V02 V03 V04 V05 V06 V08 V10 V12 V13 V16 V17 V27 V45 V46 V47 V119 V120 V121 V122 V131 V132 V133 V134 V135} +{V136} => {V02 V03 V04 V05 V06 V08 V10 V12 V13 V16 V17 V27 V45 V46 V47 V119 V120 V121 V122 V131 V132 V133 V134 V135 V136}

Variable Live Range History Dump for BB09
V02 arg2: x20 [(G_M30837_IG05,ins#7,ofs#28), ...]
V03 arg3: x21 [(G_M30837_IG05,ins#7,ofs#28), ...]
V04 arg4: x23 [(G_M30837_IG05,ins#7,ofs#28), ...]
V05 arg5: x26 [(G_M30837_IG05,ins#7,ofs#28), ...]
V06 loc0: x28 [(G_M30837_IG05,ins#7,ofs#28), ...]
V08 loc2: x2 [(G_M30837_IG07,ins#2,ofs#8), (G_M30837_IG07,ins#16,ofs#72)]; fp[800] (1 slot) [(G_M30837_IG07,ins#16,ofs#72), ...]
V10 loc4: fp[788] (1 slot) [(G_M30837_IG05,ins#7,ofs#28), ...]
V12 loc6: x5 [(G_M30837_IG07,ins#7,ofs#28), ...]
V13 loc7: fp[776] (1 slot) [(G_M30837_IG06,ins#5,ofs#20), ...]
V14 loc8: fp[768] (1 slot) [(G_M30837_IG07,ins#1,ofs#4), (G_M30837_IG07,ins#15,ofs#68)]
V15 loc9: fp[760] (1 slot) [(G_M30837_IG07,ins#3,ofs#12), (G_M30837_IG07,ins#15,ofs#68)]
V16 loc10: fp[752] (1 slot) [(G_M30837_IG07,ins#6,ofs#24), ...]
V17 loc11: fp[744] (1 slot) [(G_M30837_IG07,ins#11,ofs#48), ...]
V27 loc21: fp[704] (1 slot) [(G_M30837_IG07,ins#13,ofs#56), ...]

=============== Generating BB10 [0071] [09C..09D) -> BB12(0.5),BB11(0.5) (cond), preds={BB09,BB72} succs={BB11,BB12} flags=0x00000001.5008c011: i LIR loophead label hascall gcsafe bwd bwd-target
BB10 IN (25)={V45 V46 V06 V122 V12 V08 V27 V02 V03 V120 V17 V04 V16 V119 V121 V05 V10 V13 V47 V131 V132 V133 V134 V135 V136                } + ByrefExposed + GcHeap
     OUT(29)={V45 V46 V06 V122 V12 V08 V27 V02 V03 V120 V17 V04 V16 V119 V121 V05 V10 V13 V47 V131 V132 V133 V134 V135 V136 V52 V53 V51 V54} + ByrefExposed + GcHeap

Recording Var Locations at start of BB10
  V45(x13)  V06(x28)  V122(x19)  V12(x5)  V02(x20)  V03(x21)  V120(x22)  V04(x23)  V119(x24)  V121(x25)  V05(x26)  V131(d9)  V132(d10)
Liveness not changing: 00000000000000000007E04080FFDF44 {V02 V03 V04 V05 V06 V08 V10 V12 V13 V16 V17 V27 V45 V46 V47 V119 V120 V121 V122 V131 V132 V133 V134 V135 V136}
							Live regs: 0000000000000000 {} + {x5 x13 x19 x20 x21 x22 x23 x24 x25 x26 x28 d9 d10} => 0000060017F82020 {x5 x13 x19 x20 x21 x22 x23 x24 x25 x26 x28 d9 d10}
							GC regs: (unchanged) 0000 {}
							Byref regs: 0000 {} => 3300000 {x20 x21 x24 x25}

      L_M30837_BB10:
Saved:
      G_M30837_IG07:        ; offs=0x0000C8, size=0x00B4, bbWeight=0.50, gcrefRegs=0000 {}, byrefRegs=3300000 {x20 x21 x24 x25}, BB07 [0004], BB08 [0005], BB09 [0009], byref
Created:
      G_M30837_IG08:        ; offs=0x00017C, size=0x0000, bbWeight=4, gcrefRegs=0000 {}
Label: G_M30837_IG08, GCvars=00000000000000000000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=3300000 {x20 x21 x24 x25}

Scope info: begin block BB10, IL range [09C..09D)
genIPmappingAdd: ignoring duplicate IL offset 0x9c
Generating: N313 (???,???) [001611] -----------                            IL_OFFSET void   INL05 @ 0x0F3[E-] <- INLRT @ 0x09C[E-] REG NA
Generating: N315 (  1,  1) [000664] ----------Z                  t664 =    LCL_VAR   long   V45 tmp13        u:2 x13 REG x13 $441
                                                                        /--*  t664   long
Generating: N317 (???,???) [001747] -----------                 t1747 = *  PUTARG_REG long   REG x0
Mapped BB10 to G_M30837_IG08
IN004f:             str     x13, [fp, #0x2B0]	// [V45 tmp13]
							V45 in reg x13 is becoming dead  [000664]
							Live regs: 0000060017F82020 {x5 x13 x19 x20 x21 x22 x23 x24 x25 x26 x28 d9 d10} - {x13} => 0000060017F80020 {x5 x19 x20 x21 x22 x23 x24 x25 x26 x28 d9 d10}
IN0050:             mov     x0, x13
Generating: N319 (  1,  1) [000491] -----------                  t491 =    LCL_VAR   long   V06 loc0         u:1 x28 REG x28 $1c0
                                                                        /--*  t491   long
Generating: N321 (???,???) [001748] -----------                 t1748 = *  PUTARG_REG long   REG x1
IN0051:             mov     x1, x28
Generating: N323 (  1,  1) [000489] ----------Z                  t489 =    LCL_VAR   int    V12 loc6         u:3 x5 REG x5 $300
                                                                        /--*  t489   int
Generating: N325 (???,???) [001749] -----------                 t1749 = *  PUTARG_REG int    REG x2
IN0052:             str     w5, [fp, #0x30C]	// [V12 loc6]
							V12 in reg x5 is becoming dead  [000489]
							Live regs: 0000060017F80020 {x5 x19 x20 x21 x22 x23 x24 x25 x26 x28 d9 d10} - {x5} => 0000060017F80000 {x19 x20 x21 x22 x23 x24 x25 x26 x28 d9 d10}
Debug: Closing V12 debug range.
Debug: New V12 debug range: not adjacent
IN0053:             mov     w2, w5
Generating: N327 (  3, 12) [001750] H----------                 t1750 =    CNS_INT(h) long   0xffff65585a88 ftn REG x12
IN0054:             movz    x12, #0x5A88      // code for System.Buffers.Text.Base64:AssertRead[System.Runtime.Intrinsics.Vector128`1[ubyte]](ulong,ulong,int)
IN0055:             movk    x12, #0x6558 LSL #16
IN0056:             movk    x12, #0xFFFF LSL #32
                                                                        /--*  t1750  long
Generating: N329 (  6, 14) [001751] n---G------                 t1751 = *  IND       long   REG x12
IN0057:             ldr     x12, [x12]
Generating: N001 (  1,  1) [001837] -----------                 t1837 =    LCL_VAR   simd16 V131 tmp99        d9 REG d9
                                                                        /--*  t1837  simd16
Generating: N002 (  2,  2) [001838] -----------                 t1838 = *  INTRINSIC double simdUpperSave REG d8
IN0058:             mov     v8.d[0], v9.d[1]
Generating: N001 (  1,  1) [001839] -----------                 t1839 =    LCL_VAR   simd16 V132 tmp100       d10 REG d10
                                                                        /--*  t1839  simd16
Generating: N002 (  2,  2) [001840] -----------                 t1840 = *  INTRINSIC double simdUpperSave REG d11
IN0059:             mov     v11.d[0], v10.d[1]
                                                                        /--*  t1747  long   arg0 in x0
                                                                        +--*  t1748  long   arg1 in x1
                                                                        +--*  t1749  int    arg2 in x2
                                                                        +--*  t1751  long   control expr
Generating: N331 ( 17,  8) [000665] --CXG------                         *  CALL      void   System.Buffers.Text.Base64:AssertRead[System.Runtime.Intrinsics.Vector128`1[ubyte]](ulong,ulong,int) REG NA $VN.Void
Call: GCvars=00000000000000000000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=3300000 {x20 x21 x24 x25}
[90] Rec call GC vars = 00000000000000000000000000000000
IN005a:             blr     x12
genIPmappingAdd: ignoring duplicate IL offset 0x9c
Generating: N333 (???,???) [001612] -----------                            IL_OFFSET void   INL05 @ 0x0FD[E-] <- INLRT @ 0x09C[E-] REG NA
Generating: N335 (  1,  1) [000666] ----------#                  t666 =    LCL_VAR   long   V45 tmp13        u:2 x7 REG x7 $441
                                                                        /--*  t666   long
Generating: N337 (  2,  2) [000667] ---XG------                  t667 = *  HWINTRINSIC struct ubyte LoadVector128x4AndUnzip REG d16,d17,d18,d19 <l:$482, c:$483>
IN005b:             ldr     x7, [fp, #0x2B0]	// [V45 tmp13]
IN005c:             ld4     {v16.16b, v17.16b, v18.16b, v19.16b}, [x7]
                                                                        /--*  t667   struct
Generating: N339 ( 12,  9) [000668] MA-XG------                         *  STORE_LCL_VAR struct<System.ValueTuple`4, 64>(P) V50 tmp18         d16
                                                            *    simd16 field V50.Item1 (fldOffset=0x0) -> V137 tmp105      d:1
                                                            *    simd16 field V50.Item2 (fldOffset=0x10) -> V138 tmp106      d:1
                                                            *    simd16 field V50.Item3 (fldOffset=0x20) -> V139 tmp107      d:1
                                                            *    simd16 field V50.Item4 (fldOffset=0x30) -> V140 tmp108      d:1 REG d16,d17,d18,d19 $2c4
							V137 in reg d16 is becoming live  [000668]
							Live regs: 0000060017F80000 {x19 x20 x21 x22 x23 x24 x25 x26 x28 d9 d10} + {d16} => 0001060017F80000 {x19 x20 x21 x22 x23 x24 x25 x26 x28 d9 d10 d16}
							V138 in reg d17 is becoming live  [000668]
							Live regs: 0001060017F80000 {x19 x20 x21 x22 x23 x24 x25 x26 x28 d9 d10 d16} + {d17} => 0003060017F80000 {x19 x20 x21 x22 x23 x24 x25 x26 x28 d9 d10 d16 d17}
							V139 in reg d18 is becoming live  [000668]
							Live regs: 0003060017F80000 {x19 x20 x21 x22 x23 x24 x25 x26 x28 d9 d10 d16 d17} + {d18} => 0007060017F80000 {x19 x20 x21 x22 x23 x24 x25 x26 x28 d9 d10 d16 d17 d18}
							V140 in reg d19 is becoming live  [000668]
							Live regs: 0007060017F80000 {x19 x20 x21 x22 x23 x24 x25 x26 x28 d9 d10 d16 d17 d18} + {d19} => 000F060017F80000 {x19 x20 x21 x22 x23 x24 x25 x26 x28 d9 d10 d16 d17 d18 d19}
							Live vars after [000668]: {V02 V03 V04 V05 V06 V08 V10 V12 V13 V16 V17 V27 V45 V46 V47 V119 V120 V121 V122 V131 V132 V133 V134 V135 V136} +{V137 V138 V139 V140} => {V02 V03 V04 V05 V06 V08 V10 V12 V13 V16 V17 V27 V45 V46 V47 V119 V120 V121 V122 V131 V132 V133 V134 V135 V136 V137 V138 V139 V140}
genIPmappingAdd: ignoring duplicate IL offset 0x9c
Generating: N347 (???,???) [001613] -----------                            IL_OFFSET void   INL05 @ 0x123[E-] <- INLRT @ 0x09C[E-] REG NA
Generating: N349 (  1,  1) [000689] -----------                  t689 =    LCL_VAR   simd16 V137 tmp105      u:1 d16 REG d16 <l:$401, c:$402>
Generating: N351 (  1,  1) [000690] ----------z                  t690 =    LCL_VAR   simd16<System.Runtime.Intrinsics.Vector128`1> V47 tmp15        u:1 d20 REG d20 $400
                                                                        /--*  t689   simd16
                                                                        +--*  t690   simd16
Generating: N353 (  3,  3) [000691] -----------                  t691 = *  HWINTRINSIC simd16 ubyte SubtractSaturate REG d21 <l:$4c0, c:$4c1>
IN005d:             ldr     q20, [fp, #0x290]	// [V47 tmp15]
							V47 in reg d20 is becoming live  [000690]
							Live regs: 000F060017F80000 {x19 x20 x21 x22 x23 x24 x25 x26 x28 d9 d10 d16 d17 d18 d19} + {d20} => 001F060017F80000 {x19 x20 x21 x22 x23 x24 x25 x26 x28 d9 d10 d16 d17 d18 d19 d20}
IN005e:             uqsub   v21.16b, v16.16b, v20.16b
                                                                        /--*  t691   simd16
Generating: N355 (  3,  3) [000692] DA---------                         *  STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V55 tmp23        d:1 d21 REG d21 $VN.Void
							V55 in reg d21 is becoming live  [000692]
							Live regs: 001F060017F80000 {x19 x20 x21 x22 x23 x24 x25 x26 x28 d9 d10 d16 d17 d18 d19 d20} + {d21} => 003F060017F80000 {x19 x20 x21 x22 x23 x24 x25 x26 x28 d9 d10 d16 d17 d18 d19 d20 d21}
							Live vars after [000692]: {V02 V03 V04 V05 V06 V08 V10 V12 V13 V16 V17 V27 V45 V46 V47 V119 V120 V121 V122 V131 V132 V133 V134 V135 V136 V137 V138 V139 V140} +{V55} => {V02 V03 V04 V05 V06 V08 V10 V12 V13 V16 V17 V27 V45 V46 V47 V55 V119 V120 V121 V122 V131 V132 V133 V134 V135 V136 V137 V138 V139 V140}
genIPmappingAdd: ignoring duplicate IL offset 0x9c
Generating: N357 (???,???) [001614] -----------                            IL_OFFSET void   INL05 @ 0x12E[E-] <- INLRT @ 0x09C[E-] REG NA
Generating: N359 (  1,  1) [000693] -----------                  t693 =    LCL_VAR   simd16 V138 tmp106      u:1 d17 REG d17 <l:$403, c:$404>
Generating: N361 (  1,  1) [000694] -----------                  t694 =    LCL_VAR   simd16<System.Runtime.Intrinsics.Vector128`1> V47 tmp15        u:1 d20 REG d20 $400
                                                                        /--*  t693   simd16
                                                                        +--*  t694   simd16
Generating: N363 (  3,  3) [000695] -----------                  t695 = *  HWINTRINSIC simd16 ubyte SubtractSaturate REG d22 <l:$4c2, c:$4c3>
IN005f:             uqsub   v22.16b, v17.16b, v20.16b
                                                                        /--*  t695   simd16
Generating: N365 (  3,  3) [000696] DA---------                         *  STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V56 tmp24        d:1 d22 REG d22 $VN.Void
							V56 in reg d22 is becoming live  [000696]
							Live regs: 003F060017F80000 {x19 x20 x21 x22 x23 x24 x25 x26 x28 d9 d10 d16 d17 d18 d19 d20 d21} + {d22} => 007F060017F80000 {x19 x20 x21 x22 x23 x24 x25 x26 x28 d9 d10 d16 d17 d18 d19 d20 d21 d22}
							Live vars after [000696]: {V02 V03 V04 V05 V06 V08 V10 V12 V13 V16 V17 V27 V45 V46 V47 V55 V119 V120 V121 V122 V131 V132 V133 V134 V135 V136 V137 V138 V139 V140} +{V56} => {V02 V03 V04 V05 V06 V08 V10 V12 V13 V16 V17 V27 V45 V46 V47 V55 V56 V119 V120 V121 V122 V131 V132 V133 V134 V135 V136 V137 V138 V139 V140}
genIPmappingAdd: ignoring duplicate IL offset 0x9c
Generating: N367 (???,???) [001615] -----------                            IL_OFFSET void   INL05 @ 0x139[E-] <- INLRT @ 0x09C[E-] REG NA
Generating: N369 (  1,  1) [000697] -----------                  t697 =    LCL_VAR   simd16 V139 tmp107      u:1 d18 REG d18 <l:$405, c:$406>
Generating: N371 (  1,  1) [000698] -----------                  t698 =    LCL_VAR   simd16<System.Runtime.Intrinsics.Vector128`1> V47 tmp15        u:1 d20 REG d20 $400
                                                                        /--*  t697   simd16
                                                                        +--*  t698   simd16
Generating: N373 (  3,  3) [000699] -----------                  t699 = *  HWINTRINSIC simd16 ubyte SubtractSaturate REG d23 <l:$4c4, c:$4c5>
IN0060:             uqsub   v23.16b, v18.16b, v20.16b
                                                                        /--*  t699   simd16
Generating: N375 (  3,  3) [000700] DA---------                         *  STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V57 tmp25        d:1 d23 REG d23 $VN.Void
							V57 in reg d23 is becoming live  [000700]
							Live regs: 007F060017F80000 {x19 x20 x21 x22 x23 x24 x25 x26 x28 d9 d10 d16 d17 d18 d19 d20 d21 d22} + {d23} => 00FF060017F80000 {x19 x20 x21 x22 x23 x24 x25 x26 x28 d9 d10 d16 d17 d18 d19 d20 d21 d22 d23}
							Live vars after [000700]: {V02 V03 V04 V05 V06 V08 V10 V12 V13 V16 V17 V27 V45 V46 V47 V55 V56 V119 V120 V121 V122 V131 V132 V133 V134 V135 V136 V137 V138 V139 V140} +{V57} => {V02 V03 V04 V05 V06 V08 V10 V12 V13 V16 V17 V27 V45 V46 V47 V55 V56 V57 V119 V120 V121 V122 V131 V132 V133 V134 V135 V136 V137 V138 V139 V140}
genIPmappingAdd: ignoring duplicate IL offset 0x9c
Generating: N377 (???,???) [001616] -----------                            IL_OFFSET void   INL05 @ 0x144[E-] <- INLRT @ 0x09C[E-] REG NA
Generating: N379 (  1,  1) [000701] -----------                  t701 =    LCL_VAR   simd16 V140 tmp108      u:1 d19 REG d19 <l:$407, c:$408>
Generating: N381 (  1,  1) [000702] -----------                  t702 =    LCL_VAR   simd16<System.Runtime.Intrinsics.Vector128`1> V47 tmp15        u:1 d20 REG d20 $400
                                                                        /--*  t701   simd16
                                                                        +--*  t702   simd16
Generating: N383 (  3,  3) [000703] -----------                  t703 = *  HWINTRINSIC simd16 ubyte SubtractSaturate REG d24 <l:$4c6, c:$4c7>
IN0061:             uqsub   v24.16b, v19.16b, v20.16b
                                                                        /--*  t703   simd16
Generating: N385 (  3,  3) [000704] DA---------                         *  STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V58 tmp26        d:1 d24 REG d24 $VN.Void
							V58 in reg d24 is becoming live  [000704]
							Live regs: 00FF060017F80000 {x19 x20 x21 x22 x23 x24 x25 x26 x28 d9 d10 d16 d17 d18 d19 d20 d21 d22 d23} + {d24} => 01FF060017F80000 {x19 x20 x21 x22 x23 x24 x25 x26 x28 d9 d10 d16 d17 d18 d19 d20 d21 d22 d23 d24}
							Live vars after [000704]: {V02 V03 V04 V05 V06 V08 V10 V12 V13 V16 V17 V27 V45 V46 V47 V55 V56 V57 V119 V120 V121 V122 V131 V132 V133 V134 V135 V136 V137 V138 V139 V140} +{V58} => {V02 V03 V04 V05 V06 V08 V10 V12 V13 V16 V17 V27 V45 V46 V47 V55 V56 V57 V58 V119 V120 V121 V122 V131 V132 V133 V134 V135 V136 V137 V138 V139 V140}
genIPmappingAdd: ignoring duplicate IL offset 0x9c
Generating: N387 (???,???) [001617] -----------                            IL_OFFSET void   INL05 @ 0x14F[E-] <- INLRT @ 0x09C[E-] REG NA
Generating: N389 (  1,  2) [001515] -----------                 t1515 =    CNS_VEC   simd16<0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff> REG d25 $3c0
IN0062:             mvni    v25.4s, #0
Generating: N391 (  1,  2) [001516] -----------                 t1516 =    CNS_VEC   simd16<0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff> REG d26 $3c0
IN0063:             mvni    v26.4s, #0
Generating: N393 (  1,  1) [000710] -----------                  t710 =    LCL_VAR   simd16 V131 tmp99       u:1 d9 REG d9 $3c1
                                                                        /--*  t710   simd16
Generating:                [001843] -----------                 t1843 = *  COPY      simd16 REG d27
Generating: N395 (  1,  1) [000711] -----------                  t711 =    LCL_VAR   simd16 V132 tmp100      u:1 d10 REG d10 $3c2
                                                                        /--*  t711   simd16
Generating:                [001846] -----------                 t1846 = *  COPY      simd16 REG d28
                                                                        /--*  t1515  simd16
                                                                        +--*  t1516  simd16
                                                                        +--*  t1843  simd16
                                                                        +--*  t1846  simd16
Generating: N397 (  4,  6) [000707] -c---------                  t707 = *  FIELD_LIST struct REG NA $500
Generating: N399 (  1,  1) [000706] -----------                  t706 =    LCL_VAR   simd16 V137 tmp105      u:1 d16 (last use) REG d16 <l:$401, c:$402>
Generating: N001 (  1,  1) [001841] -----------                 t1841 =    LCL_VAR   simd16 V131 tmp99        d9 REG d9
                                                                        /--*  t1841  simd16
Generating: N002 (  2,  2) [001842] -----------                 t1842 = *  INTRINSIC simd16 simdUpperRestore REG d8
IN0064:             mov     v9.d[1], v8.d[0]
Generating: N001 (  1,  1) [001844] -----------                 t1844 =    LCL_VAR   simd16 V132 tmp100       d10 REG d10
                                                                        /--*  t1844  simd16
Generating: N002 (  2,  2) [001845] -----------                 t1845 = *  INTRINSIC simd16 simdUpperRestore REG d11
IN0065:             mov     v10.d[1], v11.d[0]
                                                                        /--*  t707   struct
                                                                        +--*  t706   simd16
Generating: N401 (  6,  8) [000712] -----------                  t712 = *  HWINTRINSIC simd16 ubyte VectorTableLookup REG d25 <l:$4c8, c:$4c9>
IN0066:             mov     v27.16b, v9.16b
IN0067:             mov     v28.16b, v10.16b
							V137 in reg d16 is becoming dead  [000706]
							Live regs: 01FF060017F80000 {x19 x20 x21 x22 x23 x24 x25 x26 x28 d9 d10 d16 d17 d18 d19 d20 d21 d22 d23 d24} - {d16} => 01FE060017F80000 {x19 x20 x21 x22 x23 x24 x25 x26 x28 d9 d10 d17 d18 d19 d20 d21 d22 d23 d24}
							Live vars after [000706]: {V02 V03 V04 V05 V06 V08 V10 V12 V13 V16 V17 V27 V45 V46 V47 V55 V56 V57 V58 V119 V120 V121 V122 V131 V132 V133 V134 V135 V136 V137 V138 V139 V140} -{V137} => {V02 V03 V04 V05 V06 V08 V10 V12 V13 V16 V17 V27 V45 V46 V47 V55 V56 V57 V58 V119 V120 V121 V122 V131 V132 V133 V134 V135 V136 V138 V139 V140}
IN0068:             tbl     v25.16b, {v25.16b, v26.16b, v27.16b, v28.16b}, v16.16b
                                                                        /--*  t712   simd16
Generating: N403 (  6,  8) [000713] DA---------                         *  STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V59 tmp27        d:1 d25 REG d25 $VN.Void
							V59 in reg d25 is becoming live  [000713]
							Live regs: 01FE060017F80000 {x19 x20 x21 x22 x23 x24 x25 x26 x28 d9 d10 d17 d18 d19 d20 d21 d22 d23 d24} + {d25} => 03FE060017F80000 {x19 x20 x21 x22 x23 x24 x25 x26 x28 d9 d10 d17 d18 d19 d20 d21 d22 d23 d24 d25}
							Live vars after [000713]: {V02 V03 V04 V05 V06 V08 V10 V12 V13 V16 V17 V27 V45 V46 V47 V55 V56 V57 V58 V119 V120 V121 V122 V131 V132 V133 V134 V135 V136 V138 V139 V140} +{V59} => {V02 V03 V04 V05 V06 V08 V10 V12 V13 V16 V17 V27 V45 V46 V47 V55 V56 V57 V58 V59 V119 V120 V121 V122 V131 V132 V133 V134 V135 V136 V138 V139 V140}
genIPmappingAdd: ignoring duplicate IL offset 0x9c
Generating: N405 (???,???) [001618] -----------                            IL_OFFSET void   INL05 @ 0x15A[E-] <- INLRT @ 0x09C[E-] REG NA
Generating: N407 (  1,  2) [001519] -----------                 t1519 =    CNS_VEC   simd16<0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff> REG d26 $3c0
IN0069:             mvni    v26.4s, #0
                                                                        /--*  t1519  simd16
Generating:                [001847] -----------                 t1847 = *  COPY      simd16 REG d28
Generating: N409 (  1,  2) [001520] -----------                 t1520 =    CNS_VEC   simd16<0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff> REG d27 $3c0
IN006a:             mvni    v27.4s, #0
                                                                        /--*  t1520  simd16
Generating:                [001848] -----------                 t1848 = *  COPY      simd16 REG d29
Generating: N411 (  1,  1) [000719] -----------                  t719 =    LCL_VAR   simd16 V131 tmp99       u:1 d9 REG d9 $3c1
                                                                        /--*  t719   simd16
Generating:                [001849] -----------                 t1849 = *  COPY      simd16 REG d30
Generating: N413 (  1,  1) [000720] -----------                  t720 =    LCL_VAR   simd16 V132 tmp100      u:1 d10 REG d10 $3c2
                                                                        /--*  t720   simd16
Generating:                [001850] -----------                 t1850 = *  COPY      simd16 REG d31
                                                                        /--*  t1847  simd16
                                                                        +--*  t1848  simd16
                                                                        +--*  t1849  simd16
                                                                        +--*  t1850  simd16
Generating: N415 (  4,  6) [000716] -c---------                  t716 = *  FIELD_LIST struct REG NA $501
Generating: N417 (  1,  1) [000715] -----------                  t715 =    LCL_VAR   simd16 V138 tmp106      u:1 d17 (last use) REG d17 <l:$403, c:$404>
                                                                        /--*  t716   struct
                                                                        +--*  t715   simd16
Generating: N419 (  6,  8) [000721] -----------                  t721 = *  HWINTRINSIC simd16 ubyte VectorTableLookup REG d26 <l:$4ca, c:$4cb>
IN006b:             mov     v28.16b, v26.16b
IN006c:             mov     v29.16b, v27.16b
IN006d:             mov     v30.16b, v9.16b
IN006e:             mov     v31.16b, v10.16b
							V138 in reg d17 is becoming dead  [000715]
							Live regs: 03FE060017F80000 {x19 x20 x21 x22 x23 x24 x25 x26 x28 d9 d10 d17 d18 d19 d20 d21 d22 d23 d24 d25} - {d17} => 03FC060017F80000 {x19 x20 x21 x22 x23 x24 x25 x26 x28 d9 d10 d18 d19 d20 d21 d22 d23 d24 d25}
							Live vars after [000715]: {V02 V03 V04 V05 V06 V08 V10 V12 V13 V16 V17 V27 V45 V46 V47 V55 V56 V57 V58 V59 V119 V120 V121 V122 V131 V132 V133 V134 V135 V136 V138 V139 V140} -{V138} => {V02 V03 V04 V05 V06 V08 V10 V12 V13 V16 V17 V27 V45 V46 V47 V55 V56 V57 V58 V59 V119 V120 V121 V122 V131 V132 V133 V134 V135 V136 V139 V140}
IN006f:             tbl     v26.16b, {v28.16b, v29.16b, v30.16b, v31.16b}, v17.16b
                                                                        /--*  t721   simd16
Generating: N421 (  6,  8) [000722] DA---------                         *  STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V60 tmp28        d:1 d26 REG d26 $VN.Void
							V60 in reg d26 is becoming live  [000722]
							Live regs: 03FC060017F80000 {x19 x20 x21 x22 x23 x24 x25 x26 x28 d9 d10 d18 d19 d20 d21 d22 d23 d24 d25} + {d26} => 07FC060017F80000 {x19 x20 x21 x22 x23 x24 x25 x26 x28 d9 d10 d18 d19 d20 d21 d22 d23 d24 d25 d26}
							Live vars after [000722]: {V02 V03 V04 V05 V06 V08 V10 V12 V13 V16 V17 V27 V45 V46 V47 V55 V56 V57 V58 V59 V119 V120 V121 V122 V131 V132 V133 V134 V135 V136 V139 V140} +{V60} => {V02 V03 V04 V05 V06 V08 V10 V12 V13 V16 V17 V27 V45 V46 V47 V55 V56 V57 V58 V59 V60 V119 V120 V121 V122 V131 V132 V133 V134 V135 V136 V139 V140}
genIPmappingAdd: ignoring duplicate IL offset 0x9c
Generating: N423 (???,???) [001619] -----------                            IL_OFFSET void   INL05 @ 0x165[E-] <- INLRT @ 0x09C[E-] REG NA
Generating: N425 (  1,  2) [001523] -----------                 t1523 =    CNS_VEC   simd16<0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff> REG d27 $3c0
IN0070:             mvni    v27.4s, #0
                                                                        /--*  t1523  simd16
Generating:                [001851] -----------                 t1851 = *  COPY      simd16 REG d29
Generating: N427 (  1,  2) [001524] -----------                 t1524 =    CNS_VEC   simd16<0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff> REG d28 $3c0
IN0071:             mvni    v28.4s, #0
                                                                        /--*  t1524  simd16
Generating:                [001852] -----------                 t1852 = *  COPY      simd16 REG d30
Generating: N429 (  1,  1) [000728] -----------                  t728 =    LCL_VAR   simd16 V131 tmp99       u:1 d9 REG d9 $3c1
                                                                        /--*  t728   simd16
Generating:                [001853] -----------                 t1853 = *  COPY      simd16 REG d31
Generating: N431 (  1,  1) [000729] -----------                  t729 =    LCL_VAR   simd16 V132 tmp100      u:1 d10 REG d10 $3c2
                                                                        /--*  t729   simd16
Generating:                [001854] -----------                 t1854 = *  COPY      simd16 REG d0
                                                                        /--*  t1851  simd16
                                                                        +--*  t1852  simd16
                                                                        +--*  t1853  simd16
                                                                        +--*  t1854  simd16
Generating: N433 (  4,  6) [000725] -c---------                  t725 = *  FIELD_LIST struct REG NA $502
Generating: N435 (  1,  1) [000724] -----------                  t724 =    LCL_VAR   simd16 V139 tmp107      u:1 d18 (last use) REG d18 <l:$405, c:$406>
                                                                        /--*  t725   struct
                                                                        +--*  t724   simd16
Generating: N437 (  6,  8) [000730] -----------                  t730 = *  HWINTRINSIC simd16 ubyte VectorTableLookup REG d27 <l:$4cc, c:$4cd>
IN0072:             mov     v29.16b, v27.16b
IN0073:             mov     v30.16b, v28.16b
IN0074:             mov     v31.16b, v9.16b
IN0075:             mov     v0.16b, v10.16b
							V139 in reg d18 is becoming dead  [000724]
							Live regs: 07FC060017F80000 {x19 x20 x21 x22 x23 x24 x25 x26 x28 d9 d10 d18 d19 d20 d21 d22 d23 d24 d25 d26} - {d18} => 07F8060017F80000 {x19 x20 x21 x22 x23 x24 x25 x26 x28 d9 d10 d19 d20 d21 d22 d23 d24 d25 d26}
							Live vars after [000724]: {V02 V03 V04 V05 V06 V08 V10 V12 V13 V16 V17 V27 V45 V46 V47 V55 V56 V57 V58 V59 V60 V119 V120 V121 V122 V131 V132 V133 V134 V135 V136 V139 V140} -{V139} => {V02 V03 V04 V05 V06 V08 V10 V12 V13 V16 V17 V27 V45 V46 V47 V55 V56 V57 V58 V59 V60 V119 V120 V121 V122 V131 V132 V133 V134 V135 V136 V140}
ISSUE: <ASSERT> #355881 /home/user/dotnet/main/src/coreclr/jit/hwintrinsiccodegenarm64.cpp (1188) - Assertion failed 'argReg == argNode->GetRegNum()' in 'System.Buffers.Text.Base64:DecodeFromUtf8(System.ReadOnlySpan`1[ubyte],System.Span`1[ubyte],byref,byref,ubyte,ubyte):int' during 'Generate code' (IL size 811; hash 0x080d878a; Instrumented Tier1)

kunalspathak · 2024-04-24T15:07:06Z

Thanks @SwapnilGaikwad . I see it now:

            mvni    v26.4s, #0
            mvni    v27.4s, #0
            mov     v28.16b, v26.16b
            mov     v29.16b, v27.16b
            mov     v30.16b, v9.16b
            mov     v31.16b, v10.16b
            tbl     v26.16b, {v28.16b, v29.16b, v30.16b, v31.16b}, v17.16b
            mvni    v27.4s, #0
            mvni    v28.4s, #0
            mov     v29.16b, v27.16b
            mov     v30.16b, v28.16b
            mov     v31.16b, v9.16b
            mov     v0.16b, v10.16b
            tbl     v27.16b, {v29.16b, v30.16b, v31.16b, v0.16b}, v18.16b
            mvni    v28.4s, #0
            mvni    v29.4s, #0
            mov     v30.16b, v28.16b
            mov     v31.16b, v29.16b
            mov     v0.16b, v9.16b
            mov     v1.16b, v10.16b
            tbl     v28.16b, {v30.16b, v31.16b, v0.16b, v1.16b}, v19.16b

a74nh · 2024-04-24T16:27:43Z

Thanks @SwapnilGaikwad . I see it now:

            mov     v28.16b, v26.16b
            mov     v29.16b, v27.16b
            mov     v30.16b, v9.16b
            mov     v31.16b, v10.16b

All those movs are not ideal. It's also badly reusing registers - first sequence starts at v28, second sequence at v29, third at v30. There might be a good reason for this (ie after the first call, v28 is still in use, but v29 onwards are free).

Not sure if this is tiered compilation or not - if lower tier then doesn't really matter.

kunalspathak · 2024-04-24T17:40:17Z

Yes, this is with JitStressRegs=0x80 where we limit the number of available registers.

SwapnilGaikwad · 2024-04-25T09:02:30Z

tbl     v28.16b, {v30.16b, v31.16b, v0.16b, v1.16b}, v19.16b

How can I get such assembly dump without hitting the asserts? With DOTNET_JitDisasm flag, it stumbled upon the asserts both in checked and debug mode.

kunalspathak · 2024-04-25T13:51:07Z

How can I get such assembly dump without hitting the asserts? With DOTNET_JitDisasm flag, it stumbled upon the asserts both in checked and debug mode.

I ported your fix and tried to get disassembly just to see the instruction sequence.

…et#101430) Fixes issue dotnet#101070

Fix checks to accommodate register wraparounds in multi-reg ops

b606d04

Fixes issue dotnet#101070

ghost added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label Apr 23, 2024

dotnet-policy-service Bot added the community-contribution Indicates that the PR has been added by a community member label Apr 23, 2024

SwapnilGaikwad mentioned this pull request Apr 23, 2024

SPMI for Arm64 failing asserting for argReg == argNode->GetRegNum() #101070

Closed

SwapnilGaikwad marked this pull request as ready for review April 23, 2024 14:19

a74nh approved these changes Apr 23, 2024

View reviewed changes

amanasifkhalid approved these changes Apr 23, 2024

View reviewed changes

kunalspathak approved these changes Apr 23, 2024

View reviewed changes

kunalspathak merged commit 5fe1a56 into dotnet:main Apr 24, 2024

SwapnilGaikwad deleted the github-fix-101070 branch April 25, 2024 08:50

matouskozak pushed a commit to matouskozak/runtime that referenced this pull request Apr 30, 2024

Fix checks to accommodate register wraparounds in multi-reg ops (dotn…

616723c

…et#101430) Fixes issue dotnet#101070

michaelgsharp pushed a commit to michaelgsharp/runtime that referenced this pull request May 9, 2024

Fix checks to accommodate register wraparounds in multi-reg ops (dotn…

46843b6

…et#101430) Fixes issue dotnet#101070

github-actions Bot locked and limited conversation to collaborators May 27, 2024

Navigation Menu

Repository navigation

Fix checks to accommodate register wraparounds in multi-reg ops - #101430

Fix checks to accommodate register wraparounds in multi-reg ops#101430
kunalspathak merged 1 commit into
dotnet:mainfrom
SwapnilGaikwad:github-fix-101070

SwapnilGaikwad commented Apr 23, 2024

Uh oh!

dotnet-policy-service Bot commented Apr 23, 2024

Uh oh!

SwapnilGaikwad commented Apr 23, 2024

Uh oh!

a74nh left a comment

Uh oh!

amanasifkhalid left a comment

Uh oh!

kunalspathak left a comment

Uh oh!

kunalspathak commented Apr 23, 2024

Uh oh!

SwapnilGaikwad commented Apr 24, 2024

Uh oh!

kunalspathak commented Apr 24, 2024

Uh oh!

a74nh commented Apr 24, 2024

Uh oh!

kunalspathak commented Apr 24, 2024

Uh oh!

SwapnilGaikwad commented Apr 25, 2024

Uh oh!

kunalspathak commented Apr 25, 2024

Uh oh!

Reviewers

Assignees

Labels

Projects

Milestone

Development

Uh oh!

4 participants

Conversation

SwapnilGaikwad commented Apr 23, 2024

Uh oh!

dotnet-policy-service Bot commented Apr 23, 2024

Uh oh!

SwapnilGaikwad commented Apr 23, 2024

Uh oh!

a74nh left a comment

Choose a reason for hiding this comment

Uh oh!

amanasifkhalid left a comment

Choose a reason for hiding this comment

Uh oh!

kunalspathak left a comment

Choose a reason for hiding this comment

Uh oh!

kunalspathak commented Apr 23, 2024

Uh oh!

SwapnilGaikwad commented Apr 24, 2024

Uh oh!

kunalspathak commented Apr 24, 2024

Uh oh!

a74nh commented Apr 24, 2024

Uh oh!

kunalspathak commented Apr 24, 2024

Uh oh!

SwapnilGaikwad commented Apr 25, 2024

Uh oh!

kunalspathak commented Apr 25, 2024

Uh oh!

Reviewers

Assignees

Labels

Projects

Milestone

Development

Uh oh!

4 participants