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RyuJIT x86: improve localloc codegen in some cases #6546

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@BruceForstall

And reduce #ifdefs.

Address the following TODO in genStackPointerConstantAdjustment():

#ifdef TARGET_X86
    if (regTmp != REG_NA)
    {
        // For x86, some cases don't want to use "sub ESP" because we don't want the emitter to track the adjustment
        // to ESP. So do the work in the count register.
        // TODO-CQ: manipulate ESP directly, to share code, reduce #ifdefs, and improve CQ. This would require
        // creating a way to temporarily turn off the emitter's tracking of ESP, maybe marking instrDescs as "don't
        // track".
        inst_Mov(TYP_I_IMPL, regTmp, REG_SPBASE, /* canSkip */ false);
        inst_RV_IV(INS_sub, regTmp, (target_ssize_t)-spDelta, EA_PTRSIZE);
        inst_Mov(TYP_I_IMPL, REG_SPBASE, regTmp, /* canSkip */ false);
    }
    else
#endif // TARGET_X86

category:cq
theme:stack-allocation
skill-level:expert
cost:small

Activity

  1. transferred this issue fromdotnet/coreclron Jan 31, 2020
  2. added this to the Future milestone on Jan 31, 2020
  3. TIHan commented on Oct 4, 2022

    @TIHan
    Contributor

    This comment and code have been moved to: genStackPointerConstantAdjustment

  4. self-assigned this
    on Oct 11, 2022
  5. ghost added
    in-prThere is an active PR which will close this issue when it is merged
    on Oct 11, 2022
  6. ghost removed
    in-prThere is an active PR which will close this issue when it is merged
    on Nov 1, 2022
  7. ghost locked as resolved and limited conversation to collaborators on Dec 1, 2022
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JitUntriagedCLR JIT issues needing additional triagearch-x86area-CodeGen-coreclrCLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMIenhancementProduct code improvement that does NOT require public API changes/additionsoptimizationtenet-performancePerformance related issue

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