[Fix][CUDA] Preserve NaNs in floating-point min and max

[LngelKyo]

Bug: on main, the CUDA codegen prints bare min()/max() for T.min/T.max on float32/float16/bfloat16, so a NaN operand is dropped

With #20054's test data, the CUDA target gives 4/8 bitwise matches: the NaN lanes are discarded and the ±0 ties disagree with the C host.

Fix

Same semantics as #20054: emit (((a > b) || (a != a)) ? a : b) for max (and the < form for min), so a NaN on either side is preserved and ties take b. Scalar form binds each operand once via SSA and references the temporaries; the vector form expands the same expression per lane. Covers float16/bfloat16/float32/float64. Integer and other non-float min/max keep the existing base-CodeGenC path, including the per-lane vector expansion. Only the CUDA codegen is touched; the host side is #20054's.

Generated source (scalar and per-lane vector), from the branch:

[float32/scalar] C_ptr[((int)threadIdx.x)] = (((v_ > v__1) || (v_ != v_)) ? v_ : v__1);
[float32/vec4]   __1.x = ((v_.x > v__1.x) || (v_.x != v_.x)) ? v_.x : v__1.x;

Tests

Folded into tests/python/codegen/test_target_codegen_cuda.py: 4 dtypes (float32/float64/float16/bfloat16) × 2 ops × {scalar, vec4}, a composite case (C[i] = max(A[i], B[i]) + 1.0 — catches the ternary being parsed as (x + cond) ? va : vb; NaN lanes assert NaN, finite lanes bitwise), and an int32 vec4 regression against numpy. Both compile paths (nvcc, nvrtc) are covered by the autouse fixture. Also test_min_max_float_imm_operand_cuda (constant NaN / non-NaN × lhs / rhs × min / max × scalar / vec4, once per compile path), with source assertions: the scalar constant fast path contains no ||; a NaN lhs is the constant itself; a NaN rhs leaves only (a != a); a non-NaN constant leaves a single ordered compare (reversed non-strict when the constant is on the right); the vec4 form takes the general per-lane path. A nested case, max(0.0, B[i]) + 1.0, is added too. The constant has to be written inline as T.float32(c): a c = T.float32(...) statement in the prim_func body is a local buffer, and the earlier CI segfault was in the test prologue, not in the codegen.

A further defect surfaced in CI: the scalar path's SSA bindings stayed alive across statements. SSAGetID caches by printed text within the live scope and the base-codegen BufferStore dispatch does not invalidate it, so warp allreduce — which emits red_buf[0] = max(red_buf[0], shuffle_down(...)) repeatedly — read the pre-write value from the second statement on: the first CI run had 92 failures in test_gpu_codegen_allreduce, all finite values with max systematically too small. The scalar bindings are now scoped to the statement (BeginScope/EndScope, the same shape the vector path already had). A chained-statements test (C[v] = max(C[v], A[v]); C[v] = max(C[v], B[v]), C pre-filled) fails on the pre-fix code and passes with the fix.

Constant-operand fast paths (in response to tqchen's review on #20054): four cases — a constant NaN lhs is the result; a constant NaN rhs needs only the (a != a) test; a constant non-NaN lhs keeps the ordered compare; a constant non-NaN rhs reverses it to a non-strict one (< → >=, > → <=). A vector constant takes the general per-lane path.

The tests are written as plain TIRx (@T.prim_func with T.constexpr selections) for the transpiler parser (#20423 / #20437); the earlier S-TIR forms no longer parse on main.

Verification

RTX A6000 (earlier rounds) and L40 (sm_89), CUDA 13.0.88:

• -k min_max: 74 passed (nvcc + nvrtc);
• full test_target_codegen_cuda.py: 440 passed, 6 skipped;
• allreduce suite: 328 passed, 330 skipped;
• negative control (predicate forced to return false): 68 failed / 6 passed — the 6 are the 4 int-vector and 2 chained cases, the latter green by construction since the control bypasses the new path;
• restored: 74/74.
• ruff@0.12.3 check/format and clang-format 20.1.8 --dry-run --Werror clean (per the run recorded in this thread).

NaN constants and NaN results are only guaranteed to be NaN, not a particular payload (on sm_89 nvcc normalizes some forms to 0x7FFFFFFF); the tests assert isnan on the NaN lanes and bitwise equality on the finite lanes.

Re-verified 2026-10-02 on an RTX A6000 (sm_86, CUDA 13.0.88, nvcc and NVRTC paths): -k min_max 74 passed; the whole codegen file 440 passed / 6 skipped; test_gpu_codegen_allreduce.py 328 passed / 330 skipped; with the NaN-preserving predicate forced off, 68 of the 74 fail (negative control).

Partially addresses #19579 (CUDA side); host side is #20054.

cc @tlopex @yongwww @swjng — CI will likely need approval as before.

[LngelKyo]

@tvm-bot rerun