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Thanks for reporting this issue. It would be helpful to narrow the case down, for example, try to compose a single layer Prelu and see if the error still occurs, this will help to give evidence to other developers.
Likely this problem is due to LLVM or low-level lowering type check issues. cc @masahi @grwlf @ZihengJiang @denis0x0Dwho might be familiar with this part of the code
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[-]Failed to export mxnet models with PRelu operator on arm devices.[/-][+][CODEGEN] LLVM PReLU Error[/+]tqchen commentedon Jan 4, 2019
Thanks for reporting this issue. It would be helpful to narrow the case down, for example, try to compose a single layer Prelu and see if the error still occurs, this will help to give evidence to other developers.
Likely this problem is due to LLVM or low-level lowering type check issues. cc @masahi @grwlf @ZihengJiang @denis0x0Dwho might be familiar with this part of the code
denis0x0D commentedon Jan 6, 2019
@nttstar can you please add simple test case, which fails. In this case it would be easy to reduce problem in llvm codegen part.
Thanks.
FrozenGene commentedon Jan 7, 2019
I can reproduce this issue after 100 trials auto tvm tunning on ARM CPU, but can not reproduce without auto tvm tunning.
The issue is that when we apply schedule of conv2d combined prelu we emit wrong LLVM IR. For example, we would emit this kind of LLVM IR:
However,
brinstruction can not accept<N x i1>type, which only accepti1type. Please see this link: https://llvm.org/docs/LangRef.html#br-instructionSo, we can add condition type check of
UnsafeSelectRewriterto avoid this issue. i.e. to make sure condition type is justi1, not other things else.I can help make a PR to resolve this issue soon.
denis0x0D commentedon Jan 7, 2019
@FrozenGene, thanks for the answer, good to know you've resolved the issue.