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[CODEGEN] LLVM PReLU Error #2364

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@nttstar

Related discussion: https://discuss.tvm.ai/t/debug-failed-to-export-library-with-llvm-on-arm-cpu-when-using-prelu/1006.

It is ok on arm mali gpu and x86 cpu. Only failed on arm cpu. It could be critical as lots of CNN models using prelu.

Activity

  1. changed the title [-]Failed to export mxnet models with PRelu operator on arm devices.[/-] [+][CODEGEN] LLVM PReLU Error[/+] on Jan 4, 2019
  2. tqchen commented on Jan 4, 2019

    @tqchen
    Member

    Thanks for reporting this issue. It would be helpful to narrow the case down, for example, try to compose a single layer Prelu and see if the error still occurs, this will help to give evidence to other developers.

    Likely this problem is due to LLVM or low-level lowering type check issues. cc @masahi @grwlf @ZihengJiang @denis0x0Dwho might be familiar with this part of the code

  3. denis0x0D commented on Jan 6, 2019

    @denis0x0D
    Contributor

    @nttstar can you please add simple test case, which fails. In this case it would be easy to reduce problem in llvm codegen part.
    Thanks.

  4. FrozenGene commented on Jan 7, 2019

    @FrozenGene
    Member

    I can reproduce this issue after 100 trials auto tvm tunning on ARM CPU, but can not reproduce without auto tvm tunning.

    input_sym = nnvm.sym.Variable('data')
    alpha = nnvm.sym.Variable('alpha')
    net = nnvm.sym.conv2d(input_sym, channels=3, kernel_size=(1,1), padding=(0,0), strides=(1, 1), use_bias=False)
    net = nnvm.sym.prelu(data=net, alpha=alpha, axis=1)
    params = {'alpha': tvm.nd.array(np.ones((3,), dtype=dtype))}

    The issue is that when we apply schedule of conv2d combined prelu we emit wrong LLVM IR. For example, we would emit this kind of LLVM IR:

    %72 = fcmp ogt <16 x float> %68, zeroinitializer
    br <16 x i1> %72, label %if_end, label %if_else

    However, br instruction can not accept <N x i1> type, which only accept i1 type. Please see this link: https://llvm.org/docs/LangRef.html#br-instruction

    So, we can add condition type check of UnsafeSelectRewriter to avoid this issue. i.e. to make sure condition type is just i1, not other things else.

    I can help make a PR to resolve this issue soon.

  5. denis0x0D commented on Jan 7, 2019

    @denis0x0D
    Contributor

    @FrozenGene, thanks for the answer, good to know you've resolved the issue.

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