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  1. StanleyCWestII.github.io StanleyCWestII.github.io Public

  2. riscv-pipelined-core riscv-pipelined-core Public

    5-stage pipelined RV32I-subset core in SystemVerilog, running on a Nexys A7. 64-entry 2-bit branch predictor, 2-way set-associative D-cache, UART echo and VGA pattern generator over MMIO.

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  3. cuda-tiled-sgemm cuda-tiled-sgemm Public

    Single-precision dense matrix multiplication written from scratch in CUDA, reaching 80% of cuBLAS on an RTX 4090 through 128x128 block tiles, 8x8 register tiles, and double-buffered shared memory.

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  4. flashattention-cuda flashattention-cuda Public

    FlashAttention forward pass written from scratch in CUDA: tiled keys and values, online softmax, and no materialized T x T attention matrix.

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