[Question]: Enhancement/Architecture: Mapping Asymmetric Heaps Across Heterogeneous Multi-Vendor Elements Without Host-Side Sync Overhead #140

Question

Following up on the discussion during the live stream deep-dive regarding bare-metal Rust and NVSHMEM bindings. I am engineering a fully localized, zero-cloud private inference cluster running on a bare-metal Debian environment. The cluster utilizes a heterogeneous hardware configuration consisting of mismatched, multi-vendor processing elements.
To maximize throughput and avoid falling back to heavy CPU orchestration loops, I am looking to implement one-sided RDMA/PCIe peer-to-peer data transfers. Because the processing units possess non-uniform VRAM capacities and architectures, mapping standard symmetric allocations is impossible.
Technical Query:
How can we best configure the underlying NVSHMEM heap initialization to map asymmetric, non-mirrored memory strides across mismatched processing elements while completely isolating the transport layer from host-side CPU synchronization overhead? Are there specific architectural boundaries within current NCCL/NVSHMEM memory registration hooks we can leverage to maintain pure device-level execution continuity for localized LLM inference tasks?