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[None][fix] Order all math warps' TMEM loads before the dealloc in the GLM-5.2 indexer MQA-logits kernels - #21844
All five GLM-5.2 FP8 paged MQA-logits kernels now use a named barrier for the math threads. Each thread fences its asynchronous TMEM loads and joins the barrier before the allocator warp releases its permit and frees TMEM. This orders the other math warps’ loads before deallocation. The change does not alter public APIs or test-list configuration.
QA Engineer Review
No test changes.
Per-File QA Perspective
.../glm_5_2_nvfp4__sm_103__tp8/kernels/indexer_layer_front/fp8_paged_mqa_logits_cp.py: Verify context-parallel kernel behavior and confirm no math warp has a TMEM load in flight when warp 0 frees TMEM.
.../glm_5_2_nvfp4__sm_103__tp8/kernels/indexer_topk/fp8_paged_mqa_logits_cross_rank.py: Verify cross-rank kernel behavior and synchronization before TMEM deallocation.
.../glm_5_2_nvfp4__sm_103__tp8/kernels/indexer_topk/fp8_paged_mqa_logits_rows.py: Verify rows-kernel behavior and synchronization before TMEM deallocation.
.../glm_5_2_nvfp4__sm_103__tp8/kernels/indexer_topk/fp8_paged_mqa_logits_rowsplit.py: Verify rowsplit kernel behavior and synchronization before TMEM deallocation.
.../glm_5_2_nvfp4__sm_107__low_latency/ops/dsa/_fp8_paged_mqa_logits_kernel.py: Verify low-latency kernel behavior and synchronization before TMEM deallocation. Hardware test status is not available.
Description
The five GLM-5.2 copies of the FP8 paged MQA-logits kernel free their accumulator TMEM without ordering the other math warps' reads before the free:
sm_107 low-latency kernel, both the split_n and the default epilogue end in the shared tail
They carry the math-warp tail of tensorrt_llm/_torch/attention/kernels/blackwell/paged_mqa_logits/fp8_paged_mqa_logits.py, which gets the same fix in a separate PR.
What happens. The math warps (warps 0-7, two warp groups; in rowsplit 4 x num_math_wg warps) read the UMMA accumulators with tcgen05.ld. Math warp 0 is the allocator (TmemAllocator(allocator_warp_id=0, barrier_for_retrieve=NamedBarrier(1, ...))) and, at the end of its own work loop, runs tmem.relinquish_alloc_permit() and tmem.free(tmem_ptr), i.e. tcgen05.relinquish_alloc_permit and tcgen05.dealloc from warp 0 alone (TmemAllocator.free has no CTA barrier for a 1-CTA kernel). Nothing orders the last tcgen05.ld of the other math warps before that dealloc:
each thread's fence_view_async_tmem_load() (tcgen05.wait::ld) completes only its own loads;
the UMMA pipeline's consumer_release arrivals are waited on by the UMMA warp(s), never by math warp 0;
the retrieve barrier after tcgen05.alloc is the only barrier the TMEM participants share. Between it and the free there is no bar.sync, named barrier or mbarrier wait in the math-warp branch of any of the five kernels.
In the four two-warp-group kernels the warp groups run independent work queues (own KV and UMMA pipelines), so their schedules can drift by up to a whole task. In rowsplit every math warp loads its own column slice of every task at its own pace. The comment at the free ("math warps are allocator + last consumer") states the intended invariant, nothing enforces it.
Why it is an ordering bug. The PTX ISA (Tensor Core 5th Generation Family Instructions, "Tensor Memory Allocation and Management Instructions", tcgen05.dealloc) requires that there be no concurrent Tensor Memory accesses when the deallocation is attempted. A tcgen05.ld is asynchronous and is complete only after tcgen05.wait::ld in the issuing thread; that completion becomes visible to another warp only through a thread synchronisation (tcgen05.fence::before_thread_sync, barrier, tcgen05.fence::after_thread_sync). The CuTe DSL's own examples/blackwell/dense_gemm.py does a barrier right before dealloc_tmem for this reason.
Why it is latent today.tcgen05.dealloc does not clear TMEM, so a late load still returns the right data as long as nothing re-allocates the columns in between. With the shipped launch (384 threads, 240 registers for the math warps plus 24 for the producers) one CTA of this kernel fits per SM, so the output is correct as long as the warp groups stay in step (a small kernel from another stream can still co-reside and allocate TMEM, which is how the hardware run below makes the race visible). Two things make reuse realistic: relinquish_alloc_permit right before the free lets the next CTA on the SM allocate as soon as the columns are gone, and fp8_paged_mqa_logits_cross_rank.py and fp8_paged_mqa_logits_cp.py execute griddepcontrol.launch_dependents at kernel entry, so a PDL dependent grid can be resident on the SM for the whole kernel and its first tcgen05.alloc receives exactly the freed columns.
Evidence. The base kernel's SGLang descendant (cutedsl_fp8_paged_mqa_logits.py, identical math-warp tail) was run on a B200 (CUDA 13.0): with warps 4-7 held back by a nanosleep before their tcgen05.ld, globaltimer probes show warp group 1 issuing its loads after warp 0's tcgen05.dealloc in 148/148 CTAs; when the freed columns are re-allocated inside the CTA's lifetime, 20/20 launches produce wrong logits, with the barrier 0/20. Four of the five kernels of this PR were run the same way on a B300 with the same result (hardware verification below). The same fix is proposed for the FlashInfer copies in flashinfer-ai/flashinfer#8855 and for the SGLang original in sgl-project/sglang#48728. Same class of TMEM-release ordering as flashinfer-ai/flashinfer#6786 / #7443.
Change. In each of the five kernels, one named barrier (id 2, num_threads=self.num_math_threads: 256 in the two-warp-group kernels, 128 x num_math_wg in rowsplit; none of the five uses id 2 today) reached after fence_view_async_tmem_load() and before relinquish_alloc_permit() / free(). The launch_dependents placements are unchanged. Cost: one bar.sync over the math threads at the end of the kernel. All five kernels compile with the change (sm_103a for the tp8 kernels, sm_107a for the low-latency kernel, both split_n settings); the pre-LLVM IR differs from the original only by the added tcgen05.wait::ld and the named barrier (nvvm.barrier id = 2, 256 threads).
Hardware verification
A static review found the gap; four of the five kernels (rows, cross_rank, cp, rowsplit) were then run on a B300 PCIe (compute capability 10.3, 80 SMs, grid = 80 CTAs) with the shipped tp8 configuration (page 64, compute block 128, 32 heads, head_dim 128, next_n 6, one 256-token unit per CTA) and torch tensors, 20 launches per row, every logit checked against an fp32 torch reference (122,880 logits per launch). Method: a nanosleep stall of warps 4-7 (warp group 1) right before their tcgen05.ld, globaltimer probes at warp 0's free and before each math warp's loads, and a one-warp kernel on a second stream that allocates the 512 TMEM columns as soon as they are free, writes a marker into them and frees them (300 x 1024 CTAs per launch).
Unpatched, no stall: 0/1600 CTAs with the free before warp group 1's loads (the loads complete 0.5-1.5 us before the free); 100 plain launches correct for every kernel.
Unpatched, stall of 10 us or 100 us + the second-stream kernel: all four kernels, 19/20 launches wrong, 1,167,360 wrong logits per run (every warp-group-1 logit of every CTA in every wrong launch; warp group 0 is never wrong), free before the load in 1600/1600 CTAs; the one correct launch is the one in which the second stream did not overlap. Stall without the second kernel: 1600/1600 early frees and a correct output. 1 us stall: rows 2/20 launches wrong (288 logits, 21/1600 CTAs early), cross_rank 69/1600 CTAs early and 0 wrong.
Patched: 0/1600 CTAs with the free before the loads and 0/20 wrong launches at 10 us and 100 us with the second-stream kernel, in all four kernels; 100 plain launches per kernel correct and bitwise identical to the unpatched kernel.
The sm_107 low-latency kernel was not run (no sm_107 device was available); its math-warp tail is the code of attention/kernels/blackwell/paged_mqa_logits/fp8_paged_mqa_logits.py, which showed the same failure and the same fix result on a B200 (148/148 CTAs free before the loads under a stall, 20/20 launches wrong once the freed columns are re-allocated, 0/20 patched).
Test Coverage
The sm_107 kernel is exercised by tests/unittest/_torch/modeling_v2/models/glm_moe_dsa/glm_5_2_nvfp4__sm_107__low_latency/dsa/test_modeling_v2_fp8_paged_mqa_logits.py. The glm_5_2_nvfp4__sm_103__tp8 kernels have no unit test under tests/unittest (only the tep4 tree has one); they are covered end to end by the model accuracy tests tests/integration/defs/accuracy/modeling_v2/test_glm_moe_dsa.py and tests/integration/defs/accuracy/test_glm52.py.
No new test: as the hardware run above shows, the race needs an injected stall of one warp group plus a re-allocation of the freed columns inside the CTA's lifetime to become observable; without the stall the output is correct.
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…e GLM-5.2 indexer MQA-logits kernels
The five GLM-5.2 copies of the FP8 paged MQA-logits kernel
(indexer_topk/fp8_paged_mqa_logits_rows.py, _cross_rank.py, _rowsplit.py,
indexer_layer_front/fp8_paged_mqa_logits_cp.py and the sm_107 low-latency
_fp8_paged_mqa_logits_kernel.py) share the base kernel's tail: the math warps
read the UMMA accumulators from TMEM with tcgen05.ld, and math warp 0 alone
runs tcgen05.relinquish_alloc_permit and tcgen05.dealloc as soon as its own
work loop ends. Nothing ordered the other math warps' last loads before that
dealloc: each warp's fence_view_async_tmem_load (tcgen05.wait::ld) covers only
its own loads, and the UMMA pipeline releases are waited on by the UMMA warp,
not by warp 0.
Add a named barrier (id 2, all math threads) in each copy, reached after each
thread's fence_view_async_tmem_load and before relinquish_alloc_permit/free.
The output is unaffected today because tcgen05.dealloc does not clear TMEM
and one CTA fits per SM, so the freed columns are not reused before the late
loads complete; the ordering is still required by the PTX ISA, and the
cross-rank and cp variants trigger PDL dependents at kernel entry, so a
dependent grid resident on the SM can allocate the freed columns. Same fix as
the base kernel and as flashinfer-ai/flashinfer#8855 / sgl-project/sglang#48728.
Signed-off-by: Bastian Hagedorn <bhagedorn@nvidia.com>
Five FP8 paged-MQA kernels now fence asynchronous TMEM loads and synchronize their math threads at a named barrier before the allocator releases its permit and frees TMEM.
Changes
TMEM Deallocation Synchronization
Layer / File(s)
Summary
Math-thread fence and barrier before deallocation tensorrt_llm/_torch/_experimental/modeling_v2/models/glm_moe_dsa/glm_5_2_nvfp4__sm_103__tp8/kernels/indexer_layer_front/fp8_paged_mqa_logits_cp.py, .../kernels/indexer_topk/fp8_paged_mqa_logits_cross_rank.py, .../kernels/indexer_topk/fp8_paged_mqa_logits_rows.py, .../kernels/indexer_topk/fp8_paged_mqa_logits_rowsplit.py, tensorrt_llm/_torch/_experimental/modeling_v2/models/glm_moe_dsa/glm_5_2_nvfp4__sm_107__low_latency/ops/dsa/_fp8_paged_mqa_logits_kernel.py
Each kernel adds a named barrier for its math threads. Before TMEM deallocation, each math thread fences asynchronous TMEM loads and joins the barrier. The allocator then releases its permit and frees TMEM.
The fix appears ready for normal validation, but its race condition lacks a targeted regression test. Add one before relying on the change to remain protected.
Security architecture risk: Low · up to 25d8f
The change strengthens memory-release ordering without expanding exposed interfaces or privileges. Remaining uncertainty concerns synchronization behavior under concurrent execution, rather than a demonstrated new security issue.
Retained concerns
No architecture-level concerns identified.
Security review details
Security Blast Radius
inferred — The directly affected scope is execution of the five existing kernel variants and their accumulator-memory lifetime. The inspected delta adds no attacker-controlled input, new caller, credential authority or cross-service dependency. It does not establish whether the surrounding production deployment shares devices or serves multiple tenants.
Resilience and Maintainability Implications
inferred — Source control flow supports convergence at the final barrier even when work loops are skipped; both low-latency epilogues share that tail. No newly introduced skipped-participant path was identified. The UMMA producer warps are not final-barrier participants: producer completion continues to rely on the existing consumer-wait/release protocol, so this is a source-level ordering assessment rather than proof of interruption recovery or hardware-level isolation.
Pre-merge checks: 4 · 1
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Title check
The title names the main change: adding TMEM load ordering across math warps before the TMEM dealloc in the GLM-5.2 indexer MQA-logits kernels. It follows the [None][fix] template format and matches t…
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The pull request description follows the required structure. It clearly explains the TMEM ordering bug, the five affected kernels, the synchronization fix, hardware verification results, existing test…
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Explanation
The title names the main change: adding TMEM load ordering across math warps before the TMEM dealloc in the GLM-5.2 indexer MQA-logits kernels. It follows the [None][fix] template format and matches the changeset, which adds a named barrier before relinquish_alloc_permit and tmem.free in five kernels. It is somewhat long at 105 characters, but it is specific and accurate.
Full details: Description check
Explanation
The pull request description follows the required structure. It clearly explains the TMEM ordering bug, the five affected kernels, the synchronization fix, hardware verification results, existing test coverage, and checklist status. No new test was added, but the description documents the available unit, integration, and hardware coverage.
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Write docstrings for the functions missing them to satisfy the coverage threshold.
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Autofix · Keep fixing CodeRabbit findings and required CI, and resolving merge conflicts
1845-1851: Trivial · Maintainability & Code Quality · Low value
Add a regression test for the TMEM dealloc barrier.
The barrier changes TMEM free ordering in this kernel. No unit test under tests/unittest covers the sm_103 tp8 kernels. Only the end-to-end accuracy tests cover them. A race between warp 0's tcgen05.dealloc and other math warps' tcgen05.ld can corrupt logits only under stall plus concurrent TMEM reallocation. The end-to-end tests are unlikely to catch this race.
Add a unit test that runs this kernel with a stall injected into a non-zero math warp before the final load. Run it with a concurrent kernel that reallocates TMEM. Compare the logits to a reference. Place the test near the sm_107 test test_modeling_v2_fp8_paged_mqa_logits.py, in a sm_103 tp8 directory.
As per path instructions: "A bug fix without a practical regression test that would have failed before the fix."
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Review comment at
@tensorrt_llm/_torch/_experimental/modeling_v2/models/glm_moe_dsa/glm_5_2_nvfp4__sm_103__tp8/kernels/indexer_layer_front/fp8_paged_mqa_logits_cp.py
around lines 1845 - 1851:
Add a regression test for the sm_103 tp8 kernel that exercises the TMEM
deallocation ordering guarded by tmem_dealloc_barrier: stall a non-zero math
warp before its final load while a concurrent kernel reallocates TMEM, then
compare the resulting logits with a reference. Place the test alongside the
existing sm_107 FP8 paged-MQA logits test in the sm_103 tp8 test area.
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only still-valid issues, skip the rest with a brief reason, keep changes
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Review comments at
@tensorrt_llm/_torch/_experimental/modeling_v2/models/glm_moe_dsa/glm_5_2_nvfp4__sm_103__tp8/kernels/indexer_layer_front/fp8_paged_mqa_logits_cp.py:
- Around line 1845-1851: Add a regression test for the sm_103 tp8 kernel that
exercises the TMEM deallocation ordering guarded by tmem_dealloc_barrier: stall
a non-zero math warp before its final load while a concurrent kernel reallocates
TMEM, then compare the resulting logits with a reference. Place the test
alongside the existing sm_107 FP8 paged-MQA logits test in the sm_103 tp8 test
area.
---
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Now verified on Rubin as well (a pre-production board). I ran this kernel unpatched and patched with the certified test's shapes and data: the c1 shard (33,152 keys, 8 rows x 32 heads) with the early-KV and the default kernel, the 200,000-key whole-context cell, the four-request batch, and the TP4 six-row shape.
Accuracy: 20 launches per configuration, 0 wrong logits, the output equals the fp64 reference bit for bit on the integer-data cells, and the patched kernel's output is bitwise identical to the unpatched one everywhere.
Perf: interleaved A/B timing of 30 rounds x 100 launches on the c1 shard gives 12.79 us (patched) vs 12.80 us (unpatched) with early KV and 12.89 vs 12.84 us for the default kernel; across all configurations the ratio is 0.99 to 1.01, i.e. within noise, as expected for one bar.sync over the math warps per CTA at kernel end.
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Dev Engineer Review
All five GLM-5.2 FP8 paged MQA-logits kernels now use a named barrier for the math threads. Each thread fences its asynchronous TMEM loads and joins the barrier before the allocator warp releases its permit and frees TMEM. This orders the other math warps’ loads before deallocation. The change does not alter public APIs or test-list configuration.
QA Engineer Review
No test changes.
Per-File QA Perspective
.../glm_5_2_nvfp4__sm_103__tp8/kernels/indexer_layer_front/fp8_paged_mqa_logits_cp.py: Verify context-parallel kernel behavior and confirm no math warp has a TMEM load in flight when warp 0 frees TMEM..../glm_5_2_nvfp4__sm_103__tp8/kernels/indexer_topk/fp8_paged_mqa_logits_cross_rank.py: Verify cross-rank kernel behavior and synchronization before TMEM deallocation..../glm_5_2_nvfp4__sm_103__tp8/kernels/indexer_topk/fp8_paged_mqa_logits_rows.py: Verify rows-kernel behavior and synchronization before TMEM deallocation..../glm_5_2_nvfp4__sm_103__tp8/kernels/indexer_topk/fp8_paged_mqa_logits_rowsplit.py: Verify rowsplit kernel behavior and synchronization before TMEM deallocation..../glm_5_2_nvfp4__sm_107__low_latency/ops/dsa/_fp8_paged_mqa_logits_kernel.py: Verify low-latency kernel behavior and synchronization before TMEM deallocation. Hardware test status is not available.Description
The five GLM-5.2 copies of the FP8 paged MQA-logits kernel free their accumulator TMEM without ordering the other math warps' reads before the free:
tmem.freetensorrt_llm/_torch/_experimental/modeling_v2/models/glm_moe_dsa/glm_5_2_nvfp4__sm_103__tp8/kernels/indexer_topk/fp8_paged_mqa_logits_rows.pyFP8MQALogitsKernel(variant="rows").../glm_5_2_nvfp4__sm_103__tp8/kernels/indexer_topk/fp8_paged_mqa_logits_cross_rank.py.../glm_5_2_nvfp4__sm_103__tp8/kernels/indexer_topk/fp8_paged_mqa_logits_rowsplit.pyFP8MQALogitsRowSplitKernel(2 or 3 math warp groups, one UMMA warp).../glm_5_2_nvfp4__sm_103__tp8/kernels/indexer_layer_front/fp8_paged_mqa_logits_cp.py.../glm_5_2_nvfp4__sm_107__low_latency/ops/dsa/_fp8_paged_mqa_logits_kernel.pysplit_nand the default epilogue end in the shared tailThey carry the math-warp tail of
tensorrt_llm/_torch/attention/kernels/blackwell/paged_mqa_logits/fp8_paged_mqa_logits.py, which gets the same fix in a separate PR.What happens. The math warps (warps 0-7, two warp groups; in
rowsplit4 xnum_math_wgwarps) read the UMMA accumulators withtcgen05.ld. Math warp 0 is the allocator (TmemAllocator(allocator_warp_id=0, barrier_for_retrieve=NamedBarrier(1, ...))) and, at the end of its own work loop, runstmem.relinquish_alloc_permit()andtmem.free(tmem_ptr), i.e.tcgen05.relinquish_alloc_permitandtcgen05.deallocfrom warp 0 alone (TmemAllocator.freehas no CTA barrier for a 1-CTA kernel). Nothing orders the lasttcgen05.ldof the other math warps before that dealloc:fence_view_async_tmem_load()(tcgen05.wait::ld) completes only its own loads;consumer_releasearrivals are waited on by the UMMA warp(s), never by math warp 0;tcgen05.allocis the only barrier the TMEM participants share. Between it and the free there is nobar.sync, named barrier or mbarrier wait in the math-warp branch of any of the five kernels.In the four two-warp-group kernels the warp groups run independent work queues (own KV and UMMA pipelines), so their schedules can drift by up to a whole task. In
rowsplitevery math warp loads its own column slice of every task at its own pace. The comment at the free ("math warps are allocator + last consumer") states the intended invariant, nothing enforces it.Why it is an ordering bug. The PTX ISA (Tensor Core 5th Generation Family Instructions, "Tensor Memory Allocation and Management Instructions",
tcgen05.dealloc) requires that there be no concurrent Tensor Memory accesses when the deallocation is attempted. Atcgen05.ldis asynchronous and is complete only aftertcgen05.wait::ldin the issuing thread; that completion becomes visible to another warp only through a thread synchronisation (tcgen05.fence::before_thread_sync, barrier,tcgen05.fence::after_thread_sync). The CuTe DSL's ownexamples/blackwell/dense_gemm.pydoes a barrier right beforedealloc_tmemfor this reason.Why it is latent today.
tcgen05.deallocdoes not clear TMEM, so a late load still returns the right data as long as nothing re-allocates the columns in between. With the shipped launch (384 threads, 240 registers for the math warps plus 24 for the producers) one CTA of this kernel fits per SM, so the output is correct as long as the warp groups stay in step (a small kernel from another stream can still co-reside and allocate TMEM, which is how the hardware run below makes the race visible). Two things make reuse realistic:relinquish_alloc_permitright before the free lets the next CTA on the SM allocate as soon as the columns are gone, andfp8_paged_mqa_logits_cross_rank.pyandfp8_paged_mqa_logits_cp.pyexecutegriddepcontrol.launch_dependentsat kernel entry, so a PDL dependent grid can be resident on the SM for the whole kernel and its firsttcgen05.allocreceives exactly the freed columns.Evidence. The base kernel's SGLang descendant (
cutedsl_fp8_paged_mqa_logits.py, identical math-warp tail) was run on a B200 (CUDA 13.0): with warps 4-7 held back by ananosleepbefore theirtcgen05.ld,globaltimerprobes show warp group 1 issuing its loads after warp 0'stcgen05.deallocin 148/148 CTAs; when the freed columns are re-allocated inside the CTA's lifetime, 20/20 launches produce wrong logits, with the barrier 0/20. Four of the five kernels of this PR were run the same way on a B300 with the same result (hardware verification below). The same fix is proposed for the FlashInfer copies in flashinfer-ai/flashinfer#8855 and for the SGLang original in sgl-project/sglang#48728. Same class of TMEM-release ordering as flashinfer-ai/flashinfer#6786 / #7443.Change. In each of the five kernels, one named barrier (id 2,
num_threads=self.num_math_threads: 256 in the two-warp-group kernels, 128 xnum_math_wginrowsplit; none of the five uses id 2 today) reached afterfence_view_async_tmem_load()and beforerelinquish_alloc_permit()/free(). Thelaunch_dependentsplacements are unchanged. Cost: onebar.syncover the math threads at the end of the kernel. All five kernels compile with the change (sm_103a for the tp8 kernels, sm_107a for the low-latency kernel, bothsplit_nsettings); the pre-LLVM IR differs from the original only by the addedtcgen05.wait::ldand the named barrier (nvvm.barrier id = 2, 256 threads).Hardware verification
A static review found the gap; four of the five kernels (
rows,cross_rank,cp,rowsplit) were then run on a B300 PCIe (compute capability 10.3, 80 SMs, grid = 80 CTAs) with the shipped tp8 configuration (page 64, compute block 128, 32 heads, head_dim 128, next_n 6, one 256-token unit per CTA) and torch tensors, 20 launches per row, every logit checked against an fp32 torch reference (122,880 logits per launch). Method: ananosleepstall of warps 4-7 (warp group 1) right before theirtcgen05.ld,globaltimerprobes at warp 0's free and before each math warp's loads, and a one-warp kernel on a second stream that allocates the 512 TMEM columns as soon as they are free, writes a marker into them and frees them (300 x 1024 CTAs per launch).rows2/20 launches wrong (288 logits, 21/1600 CTAs early),cross_rank69/1600 CTAs early and 0 wrong.The sm_107 low-latency kernel was not run (no sm_107 device was available); its math-warp tail is the code of
attention/kernels/blackwell/paged_mqa_logits/fp8_paged_mqa_logits.py, which showed the same failure and the same fix result on a B200 (148/148 CTAs free before the loads under a stall, 20/20 launches wrong once the freed columns are re-allocated, 0/20 patched).Test Coverage
The sm_107 kernel is exercised by
tests/unittest/_torch/modeling_v2/models/glm_moe_dsa/glm_5_2_nvfp4__sm_107__low_latency/dsa/test_modeling_v2_fp8_paged_mqa_logits.py. Theglm_5_2_nvfp4__sm_103__tp8kernels have no unit test undertests/unittest(only thetep4tree has one); they are covered end to end by the model accuracy teststests/integration/defs/accuracy/modeling_v2/test_glm_moe_dsa.pyandtests/integration/defs/accuracy/test_glm52.py.No new test: as the hardware run above shows, the race needs an injected stall of one warp group plus a re-allocation of the freed columns inside the CTA's lifetime to become observable; without the stall the output is correct.
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