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[None][feat] Rubin merge back: MLA, DSpark, DWDP, Helix - #21067

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longlee0622 merged 31 commits into
NVIDIA:mainfrom
mingyangHao:port/rubin-advance-main-20261023
Nov 10, 2026
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[None][feat] Rubin merge back: MLA, DSpark, DWDP, Helix#21067
longlee0622 merged 31 commits into
NVIDIA:mainfrom
mingyangHao:port/rubin-advance-main-20261023

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@mingyangHao mingyangHao commented Oct 27, 2026 •
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Dev Engineer Review

  • Standalone draft-cache support spans cache managers, speculative workers, executor state, and disaggregated transfer. Verify draft-history lifecycle, slot reuse, position limits, cache sizing, and compatibility between draft-enabled and draft-disabled peers.
  • DSpark replaces worker-owned rolling windows with manager-owned pages and adds paged attention and FP8 projection paths. Verify page-table mapping, capacity checks, scale layouts, supported geometry, and legacy fallback behavior.
  • FP4 MLA adds packed-query execution, chunked prefill, and wave-based task planning. Verify split bounds, task ordering, synchronization, and output and statistics merging.
  • Helix changes V-projection placement and communication behavior. Verify rank agreement, collective selection, shared-memory synchronization, and CUDA-graph behavior.
  • FP8 block-scale all-reduce adds fusion operations and quantization paths. Verify enum consistency, scale packing, padding, and launch constraints.
  • The cache-domain API changes C++ declarations, bindings, Python exports, and type stubs. Verify that defaults and enum values agree across those interfaces.
  • MoE event ordering and autotuner tactic distribution also change. Verify that waits precede dependent work and that ranks receive the intended tactic set.
  • No test execution results or current review-finding counts were supplied.

QA Engineer Review

  • Tests changed in the C++ cache-manager configuration test and Python tests for Helix MLA, FP4 MLA planning, cache estimation, autotuning, DFlash, DSpark, Kimi K3 DSpark semantics, and disaggregated auxiliary history. The DSpark CUDA-graph test change is comments-only.
  • Coverage includes cache-domain grouping, wave-planner behavior, managed-page writes, draft-history round trips, FP8/BF16 behavior, and Helix collectives. Test results were not supplied.
  • The test-list search found unittest/disaggregated/test_extractor.py in both l0_a10.yml and l0_h100.yml. It found no exact matching entries for the other searched changed tests. l0_dgx_b200.yml lists a different autotuner test, test_autotuner_distributed_strategy. No matching manual-QA entries were found.
  • Coverage verdict: needs follow-up. Confirm scheduling for changed tests in the appropriate CI or manual-QA lists, then run the relevant suites.

Per-File QA Perspective

Source files

  • cpp/tensorrt_llm/batch_manager/kv_cache_manager_v2/common.h — Verify CacheDomain values and the documented storage order.
  • cpp/tensorrt_llm/batch_manager/kv_cache_manager_v2/config.h — Verify that AttentionLayerConfig defaults to the target cache domain.
  • cpp/tensorrt_llm/batch_manager/kv_cache_manager_v2/lifeCycleRegistry.cpp — Verify lifecycle construction forwards the configured cache domain.
  • cpp/tensorrt_llm/batch_manager/kv_cache_manager_v2/lifeCycleRegistry.h — Verify domain-aware comparison and scratch-range behavior.
  • cpp/tensorrt_llm/batch_manager/kv_cache_manager_v2/storage/config.cpp — Verify pool grouping separates cache domains while preserving intended reuse.
  • cpp/tensorrt_llm/kernels/communicationKernels/allReduceFusionKernels.h — Verify the new fusion and quantization enum values match dispatch consumers.
  • cpp/tensorrt_llm/kernels/communicationKernels/mnnvlAllreduceKernels.cu — Verify FP8 block quantization, scale packing, padding, and launch validation.
  • cpp/tensorrt_llm/kernels/communicationKernels/mnnvlAllreduceKernels.h — Verify callers set sfLeadingDim correctly.
  • cpp/tensorrt_llm/kernels/customAllReduceKernels.h — Verify the fusion operation name and value match kernel and Python dispatch.
  • cpp/tensorrt_llm/kernels/helixAllToAll.cu — Verify the asynchronous shared-memory fence protects FIFO data before reuse.
  • cpp/tensorrt_llm/nanobind/batch_manager/kvCacheManagerV2.cpp — Verify binding defaults and properties match the C++ API.
  • cpp/tensorrt_llm/thop/allreduceOp.cpp — Verify output padding and the returned scale-view shape.
  • tensorrt_llm/_torch/attention/backends/dspark.py — Verify captured-context writes respect masks, capacities, and page-table bounds.
  • tensorrt_llm/_torch/attention/backends/fp4_mla/cache_manager.py — Verify draft-layer dtype and cache-size accounting across Helix and non-Helix configurations.
  • tensorrt_llm/_torch/attention/backends/fp4_mla/config.py — Verify the wave-plan environment setting and default.
  • tensorrt_llm/_torch/attention/backends/fp4_mla/fp4_mla_cutedsl_mufu16.py — Verify packed-task bounds, split-output merging, and pipeline synchronization.
  • tensorrt_llm/_torch/attention/backends/fp4_mla/fp4_mla_packed_reduce.py — Verify candidate limits, makespan selection, tie-breaking, and disabled-planner behavior.
  • tensorrt_llm/_torch/attention/backends/fp4_mla/packed_plan.py — Verify environment settings reach the planner launch.
  • tensorrt_llm/_torch/attention/backends/sparse/deepseek_v4/cache_manager.py — Verify draft-cache quota and fixed-reservation calculations.
  • tensorrt_llm/_torch/attention/backends/sparse/dsa/cache_manager.py — Verify local-layer pool sizing and draft-cache accounting.
  • tensorrt_llm/_torch/attention/kernels/blackwell/dspark/attention.py — Verify paged-attention arguments and supported geometry match callers.
  • tensorrt_llm/_torch/attention/kernels/blackwell/dspark/attention_kernel.py — Verify history-page masking, capacity handling, and FP8 output scales.
  • tensorrt_llm/_torch/attention/kernels/blackwell/dspark_rmsnorm_rope.py — Verify quantization scales and bounds checks on managed page writes.
  • tensorrt_llm/_torch/attention/mla.py — Verify chunked-prefill dispatch and Helix V-projection behavior against fallback paths.
  • tensorrt_llm/_torch/autotuner.py — Verify the full tactic list is used when it is shorter than the tuning group.
  • tensorrt_llm/_torch/custom_ops/dspark_attention_custom_op.py — Verify custom-op validation, kernel caching, and the removed cache/slot interface.
  • tensorrt_llm/_torch/custom_ops/dspark_rmsnorm_rope_custom_op.py — Verify device-specific compilation, page-write validation, and FP8 precompile gating.
  • tensorrt_llm/_torch/disaggregation/native/auxiliary.py — Verify draft-history serialization and recycled-slot clearing.
  • tensorrt_llm/_torch/disaggregation/native/bounce/impl.py — Verify byte accounting for cp_as_tp paged groups.
  • tensorrt_llm/_torch/disaggregation/native/mixers/attention/peer.py — Verify peer checks reject incompatible overlapping attention groups.
  • tensorrt_llm/_torch/disaggregation/native/peer.py — Verify draft-layer compatibility and rank mapping for cp_as_tp.
  • tensorrt_llm/_torch/disaggregation/native/rank_info.py — Verify the draft-layer count reflects the active cache manager.
  • tensorrt_llm/_torch/disaggregation/native/transfer.py — Verify auxiliary-slot requirements and draft-history transfer behavior.
  • tensorrt_llm/_torch/disaggregation/resource/cache_reuse.py — Verify block-ordinal conversion for shared cp_as_tp pages.
  • tensorrt_llm/_torch/disaggregation/resource/kv_extractor.py — Verify draft-page expansion and pool separation in extracted page tables.
  • tensorrt_llm/_torch/disaggregation/resource/page.py — Verify deserialization remains compatible when the new group fields are absent.
  • tensorrt_llm/_torch/disaggregation/transceiver.py — Verify draft-history validation and restoration.
  • tensorrt_llm/_torch/distributed/ops.py — Verify the new fusion operation reaches supported MNNVL dispatch.
  • tensorrt_llm/_torch/models/modeling_dflash.py — Verify FP8 page writes and block-query layout conversion.
  • tensorrt_llm/_torch/models/modeling_dspark.py — Verify managed-page and legacy paths, projection fallback, and required paged metadata.
  • tensorrt_llm/_torch/models/modeling_kimi_linear.py — Verify the Helix V-projection weight path when enabled.
  • tensorrt_llm/_torch/moe/fused_moe/cutedsl/fused_fc12.py — Verify the input-ready event is joined before fused execution.
  • tensorrt_llm/_torch/moe/fused_moe/fused_moe_cute_dsl_b12x.py — Verify event ordering before either execution path.
  • tensorrt_llm/_torch/pyexecutor/_util.py — Verify unified draft-cache selection and rejection of unsupported manager combinations.
  • tensorrt_llm/_torch/pyexecutor/engine/runners/decoder/runner.py — Verify draft-cache preparation and history snapshots occur only in applicable decode steps.
  • tensorrt_llm/_torch/pyexecutor/kv_cache/kv_cache_manager_v2.py — Verify draft allocation, sizing, history lifecycle, and target/draft pool ratios.
  • tensorrt_llm/_torch/pyexecutor/kv_cache/mamba_cache_manager/common.py — Verify draft storage is included in hybrid-cache cost estimates.
  • tensorrt_llm/_torch/pyexecutor/kv_cache/mamba_cache_manager/mamba_cache_manager_v2.py — Verify draft pools use base-manager roles and free-block counts.
  • tensorrt_llm/_torch/pyexecutor/py_executor.py — Verify pending history updates publish after sampler updates and handle absent state.
  • tensorrt_llm/_torch/pyexecutor/sampler/sampler.py — Verify the optional update field remains compatible with sample-state consumers.
  • tensorrt_llm/_torch/pyexecutor/standalone_draft_cache.py — Verify history validation and stale-cache protection during publication.
  • tensorrt_llm/_torch/speculative/dflash.py — Verify unified-cache preparation, page-table fallback, and overflow handling.
  • tensorrt_llm/_torch/speculative/dspark.py — Verify managed-page allocation, context seeding, and progress-slot handling.
  • tensorrt_llm/_torch/speculative/interface.py — Verify managed-cache hooks and padding-slot validation across worker implementations.
  • tensorrt_llm/functional.py — Verify residual-input validation permits only the intended new fusion.
  • tensorrt_llm/runtime/kv_cache_manager_v2/__init__.py — Verify the public CacheDomain export.
  • tensorrt_llm/runtime/kv_cache_manager_v2/__init__.pyi — Verify stub signatures and defaults match the bound API.

Test files

  • cpp/tests/unit_tests/batch_manager/kvCacheManagerV2ConfigTest.cpp — Covers cache-domain defaults, lifecycle comparison, and pool grouping. No test-list entry was established.
  • tests/unittest/_torch/attention/multi_gpu/test_mla_helix.py — Covers V-up projection placement and Helix all-to-all behavior in CUDA graphs. No matching test-list entry was found.
  • tests/unittest/_torch/attention/test_fp4_mla_packed.py — Covers planner wave simulation, ordering, and disabled-planning behavior. No matching test-list entry was found.
  • tests/unittest/_torch/executor/kv_cache/test_kv_cache_estimation.py — Covers standalone draft-cache sizing and dtype selection. No matching test-list entry was found.
  • tests/unittest/_torch/misc/test_autotuner.py — Covers short tactic lists across Helix CP ranks. The list search found a different autotuner test, not this test by name.
  • tests/unittest/_torch/speculative/hw_agnostic/test_dflash_worker.py — Covers managed-cache block-table decoding and FP8 context-page writes. No matching test-list entry was found.
  • tests/unittest/_torch/speculative/hw_agnostic/test_dspark_attention.py — Covers projection paths, backend selection, and page writes. No matching test-list entry was found.
  • tests/unittest/_torch/speculative/hw_agnostic/test_dspark_cuda_graph.py — The reported change removes comments only; test behavior is unchanged. No matching test-list entry was found.
  • tests/unittest/_torch/speculative/hw_agnostic/test_dspark_worker.py — Covers managed draft pages, request slots, context seeding, and generation progress. No matching test-list entry was found.
  • tests/unittest/_torch/speculative/hw_agnostic/test_kimi_k3_dspark_semantics.py — Covers paged decode parity for BF16 and FP8 histories. No matching test-list entry was found.
  • tests/unittest/disaggregated/region/test_aux.py — Covers draft-history serialization round trips. No matching test-list entry was found.
  • tests/unittest/disaggregated/test_extractor.py — Updates the fake-manager fixture. Listed in l0_a10.yml and l0_h100.yml.

Description

Test Coverage

PR Checklist

Please review the following before submitting your PR:

  • PR description clearly explains what and why. If using CodeRabbit's summary, please make sure it makes sense.

  • PR Follows TRT-LLM CODING GUIDELINES to the best of your knowledge.

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  • If PR introduces API changes, an appropriate PR label is added - either api-compatible or api-breaking. For api-breaking, include BREAKING in the PR title.

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  • CODEOWNERS updated if ownership changes

  • Documentation updated as needed

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  • The reviewers assigned automatically/manually are appropriate for the PR.

  • Please check this after reviewing the above items as appropriate for this PR.

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@mingyangHao
mingyangHao requested review from a team as code owners October 27, 2026 02:52
@mingyangHao
Merge main into Rubin port and preserve FC12 input synchronization
a6bee45 
Keep the input-ready event handoff alongside main's routing sort-table
reuse. Join the event before the fused kernel for both the cached-table
and fallback paths, retaining all existing port commits.

Extend the CPU event regression to cover cached and tuning dispatches,
matching and mismatching sort tiles, empty input, and provided output.
Initialize the SM reserve introduced on main in the test fixture.

Validation: pre-commit and syntax checks passed; 48 FC12 and 32 prior
DFlash/DSpark regressions passed with exact source ASTs and mocked native
dependencies on CPU. Full-package/GPU and L0 validation remain pending.

Signed-off-by: Mingyang Hao <mingyangh@nvidia.com>
dc3671 added a commit to dc3671/TensorRT-LLM that referenced this pull request Nov 7, 2026
@dc3671
Merge main into the Kimi K3 merge-back
05a1a68 
Merge origin/main ecf1fef (124 commits over 745c1ce). NVIDIA#21399,
NVIDIA#21400, NVIDIA#20486 and NVIDIA#20664 are now in main: their files take main's
reviewed version with this branch's later commits re-applied (fused FC12
reserved_sms + die_major, DFlash slot base pages + helix shard, DSpark
shift_label, prequantized MXFP8 over the whole low-M GEMM range).
NVIDIA#21067 and NVIDIA#20535 stay as [DEPS] merges.

Schemas and the llm_args golden manifest are merged by hand.

Signed-off-by: Zhenhuan Chen <zhenhuanc@nvidia.com>
dc3671 added a commit to dc3671/TensorRT-LLM that referenced this pull request Nov 8, 2026
@dc3671
[DEPS] merge NVIDIA#21067 (Rubin merge back: MLA, DSpark, DWDP, Helix)
8b0000f 
# Conflicts:
#	tensorrt_llm/_torch/moe/fused_moe/cutedsl/fused_fc12.py

Signed-off-by: Zhenhuan Chen <zhenhuanc@nvidia.com>
dc3671 pushed a commit to dc3671/TensorRT-LLM that referenced this pull request Nov 8, 2026
@longlee0622 @dc3671
[None][perf] CUTEDSL_FC12: small-batch NVFP4 routed-experts kernel
4ba05cf 
Calls of a SiTU TrtllmCutedslFusedFc12Nvfp4Impl layer with at most 32
tokens and no all-to-all run a new small-batch kernel
(trtllm::cute_dsl_nvfp4_small_batch_moe_rubin) instead of the fused FC12
kernel: FC1, SiTU, NVFP4 requantization, FC2 and the combine in one
persistent, dynamically scheduled grid, on the same weights (Rubin
[gate16, up16] FC1 layout) and the same tile-128 moe_sort tables. The
condition is declared once on the impl (small_batch_max_tokens, from the
activation and the per-rank expert shape); the kernel writes every output
element, so no memset precedes it.

- Layout: on MoE-TP ranks (moe_tp_size > 1, each rank holds a slice of
  every expert's intermediate) the FC1 output is token-indexed and FC2
  sums per token in registers; expert-parallel ranks keep the permuted
  layout. Both give the same bits with the deterministic combine.
- Combine: BF16 vector reds into the output the kernel zeroes first (the
  add order is unspecified, as in FC12's finalize). The deterministic
  slice combine is kept as a kernel option and serves as the bitwise
  reference of the tests (schedule independence, token-indexed vs
  permuted); the impl never selects it.
- Persistent CTAs per token tile from a per-arch table (SM107: 204 / 196
  / 180 at 8 / 16 / 32 tokens, leaving SMs to the concurrent shared
  expert); dependents are released right after the grid wait.

The reference's in-kernel push into the latent all-reduce workspace is
left out: its consumer (the latent all-reduce row kernel) is not on main.

Measured on Rubin (tekit 48d0e52fdd): helix16 n1 nsys, routed experts
19.2 -> 12.5 us per KDA layer on the critical path, -0.62 ms per step
(hecate 841335); GSM8K 95.91 (EP16, hecate 841334), 96.74 (TP4xEP4 with
die-major weights, hecate 843209).

Platform R (SM107 only; FC12 is not selected on SM100/SM103).
GB300 test exemption: effective only on SM107; Rubin evidence: hecate
841335 / 841334 / 843209 as above. The kernel itself runs on the SM100
family, so its unit tests also run on GB300.

Tests: tests/unittest/_torch/moe/kernels/parallel/test_small_batch_moe.py
(float64 reference, schedule independence, token-indexed vs permuted
bits, CUDA graph replays, no local expert); test_kimi_k3_situ_moe.py
test_cutedsl_fc12_small_batch_matches_fc12_kernel (SM107: small-batch vs
FC12 kernel on the same layer). test_cutedsl_fc12_survives_autotune_warmup
now uses 64 tokens so it still reaches the FC12 kernel.

Port onto NVIDIA#21067 / NVIDIA#21400: the small-batch path joins x_ready_event before its launch and reuses the routing's 128-row sort tables.
(cherry picked from commit ae9e7a2f28)

Signed-off-by: Jonas Li <6110159+longlee0622@users.noreply.github.com>
Signed-off-by: Zhenhuan Chen <zhenhuanc@nvidia.com>
dc3671 added a commit to dc3671/TensorRT-LLM that referenced this pull request Nov 8, 2026
@dc3671
[DEPS] merge NVIDIA#21067 (update to ba5a32d)
26cdd4c 
Brings in the Rubin merge-back review fixes (cf8309c), the DSpark FP8
scratch-load ordering fix (ba5a32d) and main up to 5865809.

Conflicts:
- MNNVL all-reduce fusion: drop RMS_NORM_QUANT_FP8_BLOCKSCALE as the PR
  does (nothing calls it) and keep our RMS_NORM_QUANT_MXFP8, renumbered
  into the freed slot (AllReduceFusionOp 10, kARRMSNormMXFP8 7, kMXFP8 3)
  in customAllReduceKernels.h, allReduceFusionKernels.h, functional.py,
  mnnvlAllreduceKernels.cu, allreduceOp.cpp and distributed/ops.py.
- modeling_dspark.py: keep _helix_post_process; write_dspark_context now
  comes from attention/kernels/dspark.py (moved by the PR).
- dflash.py: keep HelixDraftShard; DFLASH_CONTEXT_LOWERING is gone.
- test_fp4_mla_packed.py: keep both sides' plan cases and tests.

Signed-off-by: Zhenhuan Chen <zhenhuanc@nvidia.com>
dc3671 added a commit to dc3671/TensorRT-LLM that referenced this pull request Nov 8, 2026
@dc3671
Merge main
e9493af 
Merge origin/main 745c1ce. The 50 main commits up to 5865809 came in
through the NVIDIA#21400 and NVIDIA#21067 updates; the last 8 merge without conflicts.

Signed-off-by: Zhenhuan Chen <zhenhuanc@nvidia.com>
dc3671 added a commit to dc3671/TensorRT-LLM that referenced this pull request Nov 8, 2026
@dc3671
Merge main into the Kimi K3 merge-back
aea961b 
Merge origin/main ecf1fef (124 commits over 745c1ce). NVIDIA#21399,
NVIDIA#21400, NVIDIA#20486 and NVIDIA#20664 are now in main: their files take main's
reviewed version with this branch's later commits re-applied (fused FC12
reserved_sms + die_major, DFlash slot base pages + helix shard, DSpark
shift_label, prequantized MXFP8 over the whole low-M GEMM range).
NVIDIA#21067 and NVIDIA#20535 stay as [DEPS] merges.

Schemas and the llm_args golden manifest are merged by hand.

Signed-off-by: Zhenhuan Chen <zhenhuanc@nvidia.com>
@mingyangHao

mingyangHao commented Nov 9, 2026

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/bot run --disable-fail-fast

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PR_Github #83311 [ run ] triggered by Bot. Commit: a6bee45 Link to invocation

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PR_Github #83311 [ run ] completed with state SUCCESS. Commit: a6bee45
/LLM/main/L0_MergeRequest_PR pipeline #68851 completed with status: 'FAILURE'

CI Report

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  • Please check the failed tests and fix your PR
  • If you cannot view the failures, ask the CI triggerer to share details
  • Once fixed, request an NVIDIA team member to trigger CI again

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@mingyangHao
Fix autotuner merge integration and DSpark test fixture
81db78e 
Main now distributes runner/tactic pairs across the entire tuning group
and lets ranks assigned no pairs consume the merged winner. Remove the
older per-runner fallback that duplicates profiling under that scheme.
Cover nonzero offsets, balanced unique allocation, and idle-rank winner
selection without warnings for groups of 2, 4, and 16.

Initialize the DSpark confidence-loader test fixture's backend flag and
exercise both flag values without changing production precision policy.

Validation: reproduced the two autotuner CI assertions and three DSpark
fixture failures before the fix. Source-isolated CPU validation passes
34 autotuner and 8 DSv4 confidence-loader cases; V4.1 cases deselected.
Changed-file pre-commit checks pass. Full package/GPU L0 remains required.

Signed-off-by: Mingyang Hao <mingyangh@nvidia.com>
@mingyangHao

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/bot run --disable-fail-fast

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PR_Github #83384 [ run ] triggered by Bot. Commit: 81db78e Link to invocation

pengbowang-nv
pengbowang-nv approved these changes Nov 9, 2026
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LGTM from attention part.

weiminwang-nv
weiminwang-nv approved these changes Nov 9, 2026
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The new GR100 tests aren't included in the default PR CI run. Please validate them before merging with:

/bot run --stage-list "GR100-PyTorch-Post-Merge-1"

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PR_Github #83384 [ run ] completed with state SUCCESS. Commit: 81db78e
/LLM/main/L0_MergeRequest_PR pipeline #68919 completed with status: 'SUCCESS'
Pipeline passed with automatic retried tests. Check the rerun report for details.

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@longlee0622
longlee0622 enabled auto-merge (squash) November 10, 2026 00:54
zhaoyangwang-nvidia
zhaoyangwang-nvidia reviewed Nov 10, 2026
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Comment thread tensorrt_llm/_torch/models/modeling_dspark.py Resolved
Comment thread tensorrt_llm/_torch/models/modeling_dflash.py Resolved
Comment thread tensorrt_llm/_torch/models/modeling_dflash.py Resolved
Comment thread tensorrt_llm/_torch/speculative/dflash.py Resolved
Wanli-Jiang
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will approve after @zhaoyangwang-nvidia's, @dc3671's, @sunnyqgg's and @pengbowang-nv's open comments are addressed.

Comment thread tests/unittest/_torch/attention/multi_gpu/test_mla_helix.py Resolved
@longlee0622
longlee0622 merged commit 87e8679 into NVIDIA:main Nov 10, 2026
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Reviewers

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@sunnyqgg sunnyqgg sunnyqgg approved these changes
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@dc3671 dc3671 dc3671 approved these changes
@arysef arysef arysef approved these changes
@Wanli-Jiang Wanli-Jiang Wanli-Jiang approved these changes
@Barry-Delaney Barry-Delaney Barry-Delaney approved these changes
@nvpohanh nvpohanh nvpohanh approved these changes
@JunyiXu-nv JunyiXu-nv JunyiXu-nv approved these changes
@pengbowang-nv pengbowang-nv pengbowang-nv approved these changes
@rosong11 rosong11 rosong11 approved these changes
@weiminwang-nv weiminwang-nv weiminwang-nv approved these changes
@tongyuantongyu tongyuantongyu Awaiting requested review from tongyuantongyu tongyuantongyu is a code owner automatically assigned from NVIDIA/trt-llm-runtime-devs
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