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[https://nvbugs/6562942][fix] Load Qwen3.5 packed INT4 checkpoints - #19815
pranav-nvidia merged 6 commits into
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Share rank-ordered projection concatenation with Qwen4Exp. Fuse INT4 weights and their logical-row scales directly into the per-rank layout, retaining packed storage and validating shard alignment. Signed-off-by: Pranav Shrestha <254760092+pranav-nvidia@users.noreply.github.com>
Blockwise INT4 checkpoints can omit activation pre-scales. Load them only when present, keeping the identity path allocation-free. Cover absent and nonidentity scales with ROW/COLUMN TP2 GEMM tests. Signed-off-by: Pranav Shrestha <254760092+pranav-nvidia@users.noreply.github.com>
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Included review availability: This review used your included allowance. Your plan provides up to 12 included reviews per hour; 11 remain after this review. WalkthroughThe changes add shared tensor-parallel rank concatenation for Qwen mappers, dense-layout INT4 packing for Qwen3.5 projections, and optional ChangesQwen checkpoint packing and AWQ loading
Priority: ⬆️ High Estimated code review effort: 3 (Moderate) | ~25 minutes Change: Bug fix Merge Risk: ⚪ Minimal · up to No concrete new issue blocks merging after normal checks. Quantized BA loading is not covered by the added GPU test. 🚥 Pre-merge checks | ✅ 4 | ❌ 1❌ Failed checks (1 warning)
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tests/unittest/_torch/modules/test_linear_uneven_tp.py (1)
1160-1162: 📐 Maintainability & Code Quality | 🔵 Trivial | ⚡ Quick winConfirm CI coverage for
test_optional_pre_quant_scale.The only parent-directory selector is
l0_cpu.yml:77. This test class is gated to Ampere-or-newer GPUs and uses CUDA. No suitable GPU list selects this test file.Confirm that the test is intentionally QA-only or local-only. If it should protect the loader change in CI, add
unittest/_torch/modules/test_linear_uneven_tp.pyto an applicable GPU list undertests/integration/test_lists/test-db/.Coverage summary: four parameterized cases cover scale presence or absence in COLUMN and ROW modes. CI coverage needs follow-up.
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Review comments at
@tensorrt_llm/_torch/models/checkpoints/hf/qwen3_5_weight_mapper.py:
- Line 543: Replace the packed QKVZ and BA dtype and even-dimension assertions
in the weight-fusion validation with explicit ValueError checks. Preserve the
existing validation conditions and error messages so invalid storage dtypes,
mismatched projection dtypes, and odd logical dimensions are rejected even when
Python runs with optimization enabled.
Review comments at @tensorrt_llm/_torch/modules/linear.py:
- Around line 2961-2962: Update the `pre_quant_scale` handling so loading
weights without that scale clears any value retained from a previous load,
preventing `W4A16_AWQ_LinearMethod.apply` from scaling inputs with stale data.
Add a two-load regression case beside `test_optional_pre_quant_scale` that
verifies the scale is cleared on the second load.
---
Nitpick comments:
Review comments at @tests/unittest/_torch/modules/test_linear_uneven_tp.py:
- Around line 1160-1162: Check whether test_optional_pre_quant_scale is intended
to run in CI or remain QA/local-only; if it should protect the loader change in
CI, add its test file to an applicable GPU list under test-db, ensuring the
selected GPU supports its Ampere-or-newer CUDA requirements.
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tensorrt_llm/_torch/models/checkpoints/hf/qwen3_5_weight_mapper.pytensorrt_llm/_torch/models/checkpoints/hf/qwen4_exp_weight_mapper.pytensorrt_llm/_torch/models/modeling_utils.pytensorrt_llm/_torch/modules/linear.pytests/unittest/_torch/modeling/test_qwen4_exp_support.pytests/unittest/_torch/models/checkpoints/hf/test_qwen3_5_weight_mapper.pytests/unittest/_torch/modules/test_linear_uneven_tp.py
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Reject incompatible projection storage and odd dimensions under Python optimization. Clear absent activation scales during full AWQ weight reloads. Cover reloads and invalid layouts; select the GPU regression in B200 CI. Signed-off-by: Pranav Shrestha <254760092+pranav-nvidia@users.noreply.github.com>
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Use representative layouts, gate formats, storage dtypes, and TP boundaries. Exercise the 27B projection dimensions in the numerical regression matrix. Signed-off-by: Pranav Shrestha <254760092+pranav-nvidia@users.noreply.github.com>
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Stamp on behalf of runtime devs, delegating proper review to @NVIDIA/trt-llm-models-devs; please ping me if you think this is not accurate
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The packed-row fix matches the reported TP1 failure, and the mapper tests check values (per-rank dequantized matmul against the split projections), which is the right level of check. My main concern is the TP>1 claim. All of the TP2/TP8 evidence comes from the mapper tests, which split the fused tensor themselves with chunk(tp_size). They never construct the Linear that consumes it, so they can't catch a disagreement between the mapper's layout and the module's own sharding (inline at [qwen3_5_weight_mapper.py:750](https://github.com/NVIDIA/TensorRT-LLM/pull/19815/files#diff-3ce814e42622145747071fb47353b9f06257e22fd4cb913dd85e4375a9ca4b5aR750)). Please either show a TP≥2 load of the affected checkpoint, or state in the description that only TP1 was verified end-to-end.
Smaller items:
- Real AWQ checkpoints are still unhandled.
_SPLIT_PROJ_PATTERNgroups every suffix, so a per-projectionin_proj_{q,k,v,z}.pre_quant_scale(shape[hidden]) lands in therow_q/row_vshape asserts and fails. The checkpoint in this bug happens to ship no activation scales. If true AWQ (with scales) Qwen3.5 checkpoints are out of scope, say so in the description so a follow-up issue can track them. - Release-branch scope. Moving
_rank_blockintomodeling_utilsis reasonable, but it touches the Qwen4 mapper onrelease/1.3only for reuse. Please confirm that the same change is landing onmain(or link the main PR), so the branches don't diverge. - Duplicated validation. The INT4 dtype/mixed/even-dimension block appears twice (qkvz and ba). A small
_check_packed_int4(tensors, keys, rows, prefix) -> rowshelper would keep the two paths from drifting.
Load packed QKVZ and excluded BF16 gates through deferred model initialization. Compare both ranks against independent projection outputs using exact-valued inputs. Select the single-GPU regression in B200 pre-merge CI. Signed-off-by: Pranav Shrestha <254760092+pranav-nvidia@users.noreply.github.com>
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Keep identical input scales once per fused projection and reject incompatible groups. Share packed INT4 validation between QKVZ and BA projections. Check scaled projection outputs on CPU and through TP2 GDN linears. Signed-off-by: Pranav Shrestha <254760092+pranav-nvidia@users.noreply.github.com>
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….3: Load Qwen3.5 packed INT4 checkpoints Forward-port of release/1.3 PR NVIDIA#19815 (release/1.3 commit 4450bbc) to main. Signed-off-by: Pranav Shrestha <254760092+pranav-nvidia@users.noreply.github.com> Co-authored-by: Pranav Shrestha <254760092+pranav-nvidia@users.noreply.github.com> Signed-off-by: Simeng Liu <simengl@nvidia.com>
….3: Load Qwen3.5 packed INT4 checkpoints Forward-port of release/1.3 PR NVIDIA#19815 (release/1.3 commit 4450bbc) to main. Signed-off-by: Pranav Shrestha <254760092+pranav-nvidia@users.noreply.github.com> Co-authored-by: Pranav Shrestha <254760092+pranav-nvidia@users.noreply.github.com> Signed-off-by: Simeng Liu <simengl@nvidia.com>
….3: Load Qwen3.5 packed INT4 checkpoints Forward-port of release/1.3 PR NVIDIA#19815 (release/1.3 commit 4450bbc) to main. Signed-off-by: Pranav Shrestha <254760092+pranav-nvidia@users.noreply.github.com> Co-authored-by: Pranav Shrestha <254760092+pranav-nvidia@users.noreply.github.com> Signed-off-by: Simeng Liu <simengl@nvidia.com>
….3: Load Qwen3.5 packed INT4 checkpoints Forward-port of release/1.3 PR NVIDIA#19815 (release/1.3 commit 4450bbc) to main. Signed-off-by: Pranav Shrestha <254760092+pranav-nvidia@users.noreply.github.com> Co-authored-by: Pranav Shrestha <254760092+pranav-nvidia@users.noreply.github.com> Signed-off-by: Simeng Liu <simengl@nvidia.com>
….3: Load Qwen3.5 packed INT4 checkpoints Forward-port of release/1.3 PR NVIDIA#19815 (release/1.3 commit 4450bbc) to main. Signed-off-by: Pranav Shrestha <254760092+pranav-nvidia@users.noreply.github.com> Co-authored-by: Pranav Shrestha <254760092+pranav-nvidia@users.noreply.github.com> Signed-off-by: Simeng Liu <simengl@nvidia.com>
….3: Load Qwen3.5 packed INT4 checkpoints Forward-port of release/1.3 PR NVIDIA#19815 (release/1.3 commit 4450bbc) to main. Signed-off-by: Pranav Shrestha <254760092+pranav-nvidia@users.noreply.github.com> Co-authored-by: Pranav Shrestha <254760092+pranav-nvidia@users.noreply.github.com> Signed-off-by: Simeng Liu <simengl@nvidia.com>
Dev Engineer Review
pre_quant_scalevectors only when the required projections provide identical vectors.concatenate_weights_by_tp_rankmoves rank-ordered concatenation intomodeling_utilsfor reuse by Qwen3.5 and Qwen4. The Qwen4 mapper removes its local helper.pre_quant_scaleand sets the module scale toNone. The stated limitation is that unfused per-projection activation pre-scales remain unsupported.QA Engineer Review
Changed tests cover packed INT4 mapping, Qwen4 rank concatenation, optional W4A16 AWQ pre-quant scales, and loading mapper output into GDN projections. Coverage includes TP sizes 1, 2, and 8; packed values and scales; BF16 exclusions; partial loading and MTP; invalid layouts; and row- and column-parallel scale handling.
The B200 test list includes
test_qwen3_5_int4_loading.pyandTestW4A16AWQMLP::test_optional_pre_quant_scale. The objectives report passing mapper and Qwen4 support tests, optional-scale GPU cases, TP2 GDN projection checks, and GB200 TP1 checkpoint loading and generation checks. These results were not independently verified here. Reported CI outcomes include aborted and failed runs. Coverage verdict: sufficient.Per-File QA Perspective
tensorrt_llm/_torch/models/checkpoints/hf/qwen3_5_weight_mapper.py— Verify AWQ fusion preserves packed rows and logical scale layout. Check rejection of incompatible scales and invalid packed layouts.tensorrt_llm/_torch/models/checkpoints/hf/qwen4_exp_weight_mapper.py— Verify the shared helper preserves Qwen4 convolution and GDN TP rank ordering.tensorrt_llm/_torch/models/modeling_utils.py— Verifyconcatenate_weights_by_tp_rankvalidation and rank-major output for TP1 and multi-rank inputs.tensorrt_llm/_torch/modules/linear.py— Verify W4A16 AWQ loading handles absentpre_quant_scaleand retains correct behavior when the scale is present.tests/unittest/_torch/modeling/test_qwen4_exp_support.py— Tests rank concatenation and the invalid-row-count error path. No integration test-list entry is indicated for this unit test.tests/unittest/_torch/models/checkpoints/hf/test_qwen3_5_weight_mapper.py— Tests packed INT4 layouts, scales, TP boundaries, error paths, BF16 exclusion, and partial-loading behavior. No integration test-list entry is indicated for this unit test.tests/unittest/_torch/modules/test_linear_uneven_tp.py— Tests optional pre-quant scale loading in row- and column-parallel modes.TestW4A16AWQMLP::test_optional_pre_quant_scaleis listed intests/integration/test_lists/test-db/l0_b200.yml.tests/unittest/_torch/models/test_qwen3_5_int4_loading.py— Tests mapper output loaded into GDN projections for both TP2 ranks. The test file is listed intests/integration/test_lists/test-db/l0_b200.yml.tests/integration/test_lists/test-db/l0_b200.yml— Adds the Qwen3.5 INT4 loading test and optional pre-quant scale selector to the B200 pre-merge CI list.Description
Qwen3.5 INT4 checkpoints pack two output channels into each byte, but projection fusion validates those physical rows against the unpacked dimensions. This causes Qwen3.5-27B loading to fail with an expected QKV dimension of 10240 versus 5120 stored rows.
Fuse INT4 projections directly in tensor-parallel rank order while preserving packed storage and the logical row layout of scales. Move the existing Qwen4 rank-concatenation helper into
modeling_utilsand reuse it in both mappers. Also allow the generic W4A16 loader to omit activation pre-scales, as blockwise weight-only checkpoints can legitimately contain none. Both changes are needed for the affected checkpoint to load and serve. Full-checkpoint end-to-end validation is limited to TP1. Retained activation pre-scales are supported when all components within each fused projection provide the same input-scale vector. Preserve that vector once, without concatenating or TP-sharding its input channels. Reject incomplete, incorrectly shaped, or unequal scale groups; differing scales require weight resmoothing and are outside this fix. Packed INT4 storage validation is shared by QKVZ and BA. A cherry-pick PR targetingmainwill follow after this release PR merges.Test Coverage
tests/unittest/_torch/modules/test_linear_uneven_tp.py::TestW4A16AWQMLP::test_optional_pre_quant_scale: six GPU cases passed, comparing absent and nonidentity scales and scaled-to-unscaled reloads under ROW/COLUMN TP2 against an independent matrix reference. The exact selector is included in the single-GPU B200 pre-merge list.tests/unittest/_torch/models/test_qwen3_5_int4_loading.py::test_int4_mapper_to_gdn_tp2: two GPU cases passed, with and without nonidentity activation pre-scales. Constructs a one-layer Qwen3.5 model through the normal deferred-initialization path, loads mapper output into its actual GDN QKVZ and BF16 BA projections, and checks both TP2 ranks against independent projection outputs. It uses the 27B projection row counts with a smaller hidden size; both ranks run sequentially on one GPU, with unused collective-workspace allocation stubbed. Included in B200 pre-merge CI. This is projection loading/GEMM coverage, not a full-model multi-GPU run.int4_blockwise_weight_onlycheckpoint. Applying these production changes completed full checkpoint loading, kernel warmup, and six HTTP generation checks with exact expected answers in sequential and concurrent requests. This validates startup and generation; benchmark accuracy was not measured.PR Checklist
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