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Included review availability: This review used your included allowance. Your plan provides up to 12 included reviews per hour; 11 remain after this review. WalkthroughThe cuDNN attention backend now checks the requested CUDA device, supports quantized attention on SM 107, and returns LSE in ChangescuDNN Attention
Priority: ➖ Normal Estimated code review effort: 3 (Moderate) | ~20 minutes Change: Bug fix Suggested reviewers: Merge Risk: ⚪ Minimal · up to The inspected compatibility and LSE paths are consistent with their consumers. No actionable issue remains from this review; merge after normal checks. 🚥 Pre-merge checks | ✅ 5✅ Passed checks (5 passed)
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CuDNNAttention.check_hardware_compatibility rejected quantized attention on any SM other than 100/103, so FP8/MXFP8 cuDNN attention raised at graph build on Rubin (SM107) even though cuDNN ships a native SM107 FP8 flash-attention kernel (cudnn_generated_fort_native_sdpa_sm107_flash_fprop_f8). Add SM107 to the allowed set, name Rubin in the error message, and add host-independent tests for the gate. Signed-off-by: Tin-Yin Lai <tinyinl@nvidia.com>
Ring and Attention2D sequence-parallel attention consume forward_with_lse output as [B, H, S], which FA4 and FlashInfer return, but CuDNNAttention transposed it to [B, S, H]. Under an Attention2D mesh with more than one rank per row, flash_attn_combine then weighted partial outputs with LSE from the wrong query/head positions. Return the cuDNN stats as [B, H, S], update the unit test, add an Attention2D test with the cuDNN inner backend, and drop the SM 107 code comment per review. Signed-off-by: Tin-Yin Lai <tinyinl@nvidia.com>
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Review comments at @tensorrt_llm/_torch/visual_gen/attention_backend/cudnn.py:
- Line 303: Update the SM-version check in `_get_or_build_graph()` to inspect
the properties of its `device` argument rather than using `get_sm_version()`,
which reads CUDA device 0. Preserve the quantization condition and supported SM
versions, and add a mixed-GPU regression test confirming the decision follows
the target device.
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tensorrt_llm/_torch/visual_gen/attention_backend/cudnn.pytests/unittest/_torch/visual_gen/multi_gpu/test_attn2d_attention.pytests/unittest/_torch/visual_gen/test_attention_cudnn.py
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check_hardware_compatibility read the SM version of CUDA device 0 instead of the device the tensors live on, so on a mixed-GPU host it could reject a supported GPU or admit quantized attention on an unsupported one. Query the given device, skip the check for unquantized attention, and add a mixed-device regression test. Signed-off-by: Tin-Yin Lai <tinyinl@nvidia.com>
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Approved from attention perspective, with one question (non-blocking).
RingAttention merges the inner backend's LSE as [B, H, S] too (parallel.py), but only the Attention2D test exercises the cuDNN inner backend, and test_ring_attention.py has no cuDNN case. Could we add a Ring case with the cuDNN inner backend, so the layout fix is covered on both consumers?
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Scope correction: This PR still requires attention review. The VisualGen path migration in #20214 incorrectly caused the earlier inactive status. That status is corrected; the previous review owner and review history are retained. Keeping @farazkh80 as the trt-llm-torch-attention-devs reviewer based on their existing review activity on this PR. This confirms existing ownership; it does not request another review or add review points. Why this reviewer is retainedEvidence: submitted review at 2026-10-07T00:35:15Z. The bot keeps the first eligible attention reviewer who started reviewing. Current target-branch CODEOWNERS includes attention-owned changes in this PR. |
…DIA#21275 NVIDIA#19738 NVIDIA#21485 NVIDIA#21483 NVIDIA#21484 One branch that is the MiniMax-H3 recipe for SM 107, so it can be checked out and built instead of composed from per-lever patches at job time. Base: NVIDIA/TensorRT-LLM main aea80a0 (2026-11-06). The PR branches are merged in this order, every original commit kept: NVIDIA#21089 feat/minimax-h3-static-nvfp4-load static NVFP4 / FP8 checkpoint loader NVIDIA#21275 feat/minimax-h3-fa4-2cta-default FA4 2-CTA default on SM 103 / SM 107 NVIDIA#19738 wu6u3tw:fix/cudnn-fp8-attn-sm107 cuDNN FP8 attention on SM 107, LSE layout NVIDIA#21485 feat/minimax-h3-cudnn-fp8-ulysses cuDNN padding mask, fused FP8 QK cast, prefix output in place, async-Ulysses FP8 pairing NVIDIA#21483 feat/minimax-h3-fused-nvfp4-quant producer quantize fusion, residual fold, attention-output quantize NVIDIA#21484 feat/minimax-h3-vae-decoder-fp8-tiles schedule, FP8 tiled VAE decoder This commit applies the pre-commit fixes on the merged tree (ruff import order in pipeline_minimax_h3.py, ruff-format of vae_decoder_fp8.py), drops a measured kernel share from the vae_decoder_fp8 docstring, and routes the fused FP8 QK attention path's output through _out_proj: NVIDIA#21485 added that return after NVIDIA#21483 was cut, so the merge left it calling to_out directly and the attention-output quantize of NVIDIA#21483 never ran on the cuDNN FP8 row. How to turn the recipe on (NVFP4 checkpoint, request flags --attention-backend CUDNN --qk-dtype fp8 --v-dtype fp8): # the composed arm, every layer on (U1 and U4; drop H3_CUDNN_PREFIX_INPLACE only if the shape divides by U) export H3_FUSED_QUANT=1 H3_FUSED_QUANT_WARPS=4 H3_LEVER10_FOLD=1 export H3_FP8_SCALE_FUSION=dynamic H3_FP8_FUSION_SPLIT=1 export H3_OUT_QUANT=1 H3_CUDNN_PREFIX_INPLACE=1 export H3_L14_SCHED=1 H3_L14_VAE_FP8=1 H3_L14_VAE_TILE=288x272x32 # cuDNN FP8 attention: apply PR NVIDIA#19738 (it allows FP8 on SM 107 and fixes the LSE layout) to backends/cudnn.py first; # the measurements carried it as a shim ahead on PYTHONPATH, switched by H3_UNGATE_CUDNN=1; that shim is not in this folder # do NOT set H3_FP8_FUSION_BLOCK_H / H3_FP8_FUSION_WARPS: the module default (4 / 2) is the tuned launch # attention selection on the request: --attention-backend CUDNN --qk-dtype fp8 --v-dtype fp8 # U8 at 104k tokens: static FP8 scales instead of dynamic (table of 12 held-out prompts, in this folder) # (H3_FP8_STATIC_MARGIN defaults to 1.0) export H3_FP8_SCALE_FUSION=static H3_FP8_STATIC_SCALES=patches/fp8-static-scales-heldout.json # U8 at 19k tokens: all ten patches applied, step fusions off export H3_FUSED_QUANT=0 H3_OUT_QUANT=0; unset H3_LEVER10_FOLD H3_FP8_SCALE_FUSION H3_FP8_FUSION_SPLIT # fallback row (BF16 FA4 2-CTA): skip the NVIDIA#19738 step, unset H3_FP8_SCALE_FUSION H3_FP8_FUSION_SPLIT H3_CUDNN_PREFIX_INPLACE, # request FA4 and let the 2-CTA default of patch 2 apply (section 6 for the worker spawn) # the FP8 option (section 2.2): point the model at the static FP8 export (composite over the BF16 checkpoint), # same ten patches and the NVIDIA#19738 step; the NVFP4 fusions off, the static scale table never export H3_FUSED_QUANT=0 H3_OUT_QUANT=0; unset H3_LEVER10_FOLD export H3_FP8_SCALE_FUSION=dynamic H3_FP8_FUSION_SPLIT=1 H3_CUDNN_PREFIX_INPLACE=1 export H3_L14_SCHED=1 H3_L14_VAE_FP8=1 H3_L14_VAE_TILE=288x272x32 # request: --attention-backend CUDNN --qk-dtype fp8 --v-dtype fp8 The block above is the recipe report's "how to turn it on" verbatim; on this branch three of its lines are already satisfied by the code: NVIDIA#19738 is merged (no shim, no H3_UNGATE_CUDNN), H3_LEVER10_FOLD has no switch (the residual fold is part of H3_FUSED_QUANT, which defaults to on, as does H3_OUT_QUANT), and "patch 2" is the FA4 2-CTA default of NVIDIA#21275. The package ships one static FP8 descale table (calibrated at 544x960x124) under tensorrt_llm/_torch/visual_gen/models/minimax_h3/fp8_scale_tables/; the held-out table the report names for the U8 104k row stays beside the report. Signed-off-by: Kanghwan Jang <kanghwanj@nvidia.com> Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Dev Engineer Review
The hardware compatibility gate now accepts quantized cuDNN attention on SM 107, alongside SM 100 and SM 103. Other architectures remain rejected for quantized attention. The error message identifies Blackwell- or Rubin-class GPUs and lists the supported SM versions.
QA Engineer Review
tests/unittest/_torch/visual_gen/test_attention_cudnn.pyadds host-independent checks for FP8 and MXFP8 on SM 100, 103, and 107. It also checks rejection of FP8 on SM 90 and 120, and confirms unquantized attention does not raise in those cases. Coverage verdict: sufficient for the hardware gate behavior. The available evidence does not establish whether the reported Rubin test run occurred. This test file was not found in the searched CI or manual-QA lists.Per-File QA Perspective
tensorrt_llm/_torch/visual_gen/attention_backend/cudnn.py: Verify that FP8 and MXFP8 attention can build on SM 107 and that unsupported architectures still produce the expected error.tests/unittest/_torch/visual_gen/test_attention_cudnn.py: Covers supported and unsupported SM versions using patched hardware detection. It is not listed in the searchedtest-db/CI orqa/manual-QA lists.Description
CuDNNAttention.check_hardware_compatibilityallows quantized (FP8 / MXFP8) attention only on SM 100 and 103, so theCUDNNbackend with aquant_attention_configraises on Rubin (SM 107).cudnn_generated_fort_native_sdpa_sm107_flash_fprop_f8.CuDNNAttention.forward_with_lsereturned LSE as[B, S, H], while Ring and Attention2D consume[B, H, S](the layout FA4 and FlashInfer return). With an Attention2D mesh of more than one rank per row,flash_attn_combineweighted partial outputs with LSE from the wrong positions.[B, H, S].Test Coverage
get_sm_versionpatched):test_cudnn_quantized_attention_allowed_on_supported_sm: fp8 / mxfp8 accepted on SM 100, 103, 107.test_cudnn_quantized_attention_rejected_on_unsupported_sm: SM 90 / 120 rejected; unquantized not gated.test_cudnn_hardware_gate_checks_target_device(mixed-GPU host: gate follows the target device).test_attn2d_attention.py::test_attn2d_cudnn_vs_standard_attention(cuDNN inner backend, 2x2 mesh, vs full SDPA). Fails before Fix 2, passes after.test_attention_cudnn.pyasserts the[B, H, S]LSE layout.test_attention_cudnn.py,multi_gpu/test_attn2d_attention.py,multi_gpu/test_ring_attention.py.PR Checklist
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