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Signed-off-by: Daisy Chu <daichu@nvidia.com>
Signed-off-by: Daisy Chu <daichu@nvidia.com>
Signed-off-by: Daisy Chu <daichu@nvidia.com>
Signed-off-by: Daisy Chu <daichu@nvidia.com>
Signed-off-by: Daisy Chu <daichu@nvidia.com>
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Heads-up: #20214 moved This PR merges cleanly, but the result breaks: your Could you rebase and move |
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Let me close this PR first. |
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Automatically pack eligible BF16 Q/K/V tensors directly into cuDNN's MXFP8 payload and scale layouts. The CuTe kernels remove intermediate layout copies while preserving the native quantization arithmetic. Dispatch selects the fast path on SM100 for supported shapes and strides; unsupported inputs keep the native implementation. No configuration flag is required.
The full-model comparison uses Wan2.2 A14B with the official static-NVFP4 checkpoint on one B200: 480×832, 33 frames, 40 steps, seed 42, three prompts, CUDNN MXFP8 attention, compilation on and CUDA graphs off. Both arms use TensorRT-LLM
1.3.0rc27.dev202609150000in the same process.Validation: byte-level payload/scale and cuDNN consumer checks passed; production GPU tests: 34 passed and one expected SM103 hardware skip. Worst-prompt LPIPS across all 33 frames: 0.0 (limit 0.25).