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[Bug Report] SuperV3 MTP regression on main introduced by #13566 (NVBUG 6221483) #14595

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Description

@greg-kwasniewski1

Summary

After PR #13566 ([fix][bug 6120981] Switch to cu_seqlens_to_chunk_indices_offsets_triton with total_seqlens/extra_chunks, squash-merged as 998f41855d), the NemotronSuperV3 MTP accuracy tests fail on main. Tracking issue for NVBUG 6221483.

The original suspect was PR #13478 (squash-merged as 92c5030ff4), because the bug only became visible at CUDA-graph-capture time after #13478's IR-canonical NemotronH model landed. Bisection (see comment below) showed #13478 only shifts the crash earlier: with #13478 the assert fires during compile_model/capture_graph for bs=8; without #13478 the same assert fires during the first MTP decode iteration. Reverting only #13478 does not make the test pass; reverting only #13566 does.

NVBUG

Failing tests

  • accuracy/test_llm_api_autodeploy.py::TestNemotronSuperV3::test_mtp[nvfp4_ws4_80gb-trtllm]
  • accuracy/test_llm_api_autodeploy.py::TestNemotronSuperV3::test_mtp[fp8_ws4_80gb-trtllm]

Reproduction (confirmed empirically)

git checkout main                              # FAIL (Indexing.cu:1515 indexSelectSmallIndex during cuda graph capture for bs=8)
git revert 998f41855d && retest                # PASS  -> #13566 IS the root cause
git revert 92c5030ff4 && retest                # still FAIL (shifted to first-decode crash) -> #13478 is NOT the root cause

Root cause

_mamba_ssm_prepare_metadata in tensorrt_llm/_torch/auto_deploy/custom_ops/mamba/mamba_backend_common.py (added by #13566) trusts CPU-side batch_info_host.get_num_tokens() and seq_len_host for three shortcut kwargs that avoid GPU->CPU sync:

  • cu_seqlens_to_chunk_indices_offsets_triton(..., total_seqlens=num_prefill_tokens, extra_chunks=_extra)
  • torch.repeat_interleave(..., output_size=num_prefill_tokens)

During CUDA-graph capture warmup the CPU host tensors carry dummy values that do not match GPU-side seq_len/cu_seqlen, so PyTorch's internal index_select inside repeat_interleave walks off the end of the source tensor and fires Indexing.cu:1515 indexSelectSmallIndex: srcIndex < srcSelectDimSize. #13478's IR-canonical model exposes the warmup path earlier, which is why the symptom moved from "first decode" to "capture time" when #13478 landed.

Why CI did not catch it

Both PRs (#13566 and #13478) were merged via /bot skip after their L0 stages reported unrelated failures. Each was defensible against its own L0 but neither L0 exercised the post-merge interaction:

A "stale-base gate" has now been added to the local pr-monitor skill to prevent a repeat.

Investigation plan (completed)

  1. Reproduce locally on main -> confirmed: Indexing.cu:1515 indexSelectSmallIndex during compile_model/capture_graph for bs=8.
  2. Bisect within [https://nvbugs/6120981][fix] Switch to cu_seqlens_to_chunk_indices_offsets_triton with total_seqlens/extra_ch #13566's diff -> see bisection comment below; only the full file revert of mamba_backend_common.py passes, even keeping just the seq_len_host signature re-triggers the bug.
  3. Apply the minimal fix: revert tensorrt_llm/_torch/auto_deploy/custom_ops/mamba/mamba_backend_common.py in full to its pre-[https://nvbugs/6120981][fix] Switch to cu_seqlens_to_chunk_indices_offsets_triton with total_seqlens/extra_ch #13566 state; leave mamba2_metadata.py and waives.txt parts of [https://nvbugs/6120981][fix] Switch to cu_seqlens_to_chunk_indices_offsets_triton with total_seqlens/extra_ch #13566 untouched.
  4. Local validation: full repro (world_size=4, real FP8 weights, full model, cuda_graph_batch_sizes=[1,2,4,8]) -> 10/10 prompts generated, 0 asserts.
  5. CI validation: DGX_H100-4_GPUs-AutoDeploy-1 (owns fp8_ws4_80gb) and DGX_B200-4_GPUs-AutoDeploy-1 (owns nvfp4_ws4_80gb) -- triggered on the fixing PR.

Scope

  • Surface: tensorrt_llm/_torch/auto_deploy/custom_ops/mamba/mamba_backend_common.py
  • Affected component: AutoDeploy SSM prepare-metadata custom op (NemotronH-family models with MoE EP)

Risk

library-visible. The fix re-introduces the GPU->CPU sync that #13566 was originally trying to remove for EP-deadlock prevention (NVBUG 6120981). A follow-up that restores that optimization safely (e.g. by gating on torch.cuda.is_current_stream_capturing()) is a separate task.

Links

Activity

  1. added
    feature requestNew feature or request. This includes new model, dtype, functionality support
    AutoDeploy<NV> AutoDeploy Backend
    on May 26, 2026
  2. added
    Customized kernels<NV>Specialized/modified CUDA kernels in TRTLLM for LLM ops, beyond standard TRT. Dev & perf.
    on May 26, 2026
  3. changed the title [-][Bug Report] SuperV3 MTP regression on main introduced by #13478 (NVBUG 6221483)[/-] [+][Bug Report] SuperV3 MTP regression on main introduced by #13566 (NVBUG 6221483)[/+] on May 27, 2026
  4. greg-kwasniewski1 commented on May 27, 2026

    @greg-kwasniewski1
    CollaboratorAuthor

    Bisection result -- root cause is #13566, not #13478

    Ran the full repro (world_size=4, real FP8 weights, full NemotronH layers, cuda_graph_batch_sizes=[1,2,4,8], mimicking test_mtp[fp8_ws4_80gb-trtllm]) on upstream/main (8cd28ed022 at the time of testing) against a systematic set of partial reverts.

    Test What's reverted on top of main ToT Indexing.cu PROMPTs Result
    B nothing (untouched main) hit 0 CRASH at capture bs=8
    C full git revert 998f41855d (all of #13566) 0 10 PASS
    D' only line 79 (output_size=num_prefill_tokens, from repeat_interleave) hit 0 CRASH shifts to first decode
    N line 79 + S1 args (total_seqlens=/extra_chunks= from cu_seqlens_to_chunk_indices_offsets_triton) 3 0 CRASH bs=8 (earlier, kernel falls back to GPU sync)
    O mamba_backend_common.py fully reverted to pre-#13566 0 10 PASS
    O2 same as O, but keep seq_len_host: torch.Tensor in both function signatures 3 0 CRASH bs=8 (signature alone is enough to re-trigger)

    Three findings worth flagging:

    1. The same Indexing.cu:1515 indexSelectSmallIndex error fires in both pre-[TRTLLM-13429][feat] Switch DeepSeek/NemotronH/Qwen3/Qwen3.5-MoE to sharding-IR canonical models #13478 and post-[TRTLLM-13429][feat] Switch DeepSeek/NemotronH/Qwen3/Qwen3.5-MoE to sharding-IR canonical models #13478 states -- pre-[TRTLLM-13429][feat] Switch DeepSeek/NemotronH/Qwen3/Qwen3.5-MoE to sharding-IR canonical models #13478 it shifts to the first MTP decode iteration, post-[TRTLLM-13429][feat] Switch DeepSeek/NemotronH/Qwen3/Qwen3.5-MoE to sharding-IR canonical models #13478 it shifts up to capture_graph for bs=8. So [TRTLLM-13429][feat] Switch DeepSeek/NemotronH/Qwen3/Qwen3.5-MoE to sharding-IR canonical models #13478 is not the root cause; it only changes when the bug surfaces.
    2. Removing the optimizer kwargs only (S1 + S2) makes the bug fire earlier, not fix it (Test N). When total_seqlens=/extra_chunks= are dropped, the Triton kernel falls back to cu_seqlens[-1].item() (a GPU->CPU sync) and the mismatch surfaces immediately during capture warmup.
    3. Even keeping just seq_len_host: torch.Tensor in the registered op's signature is sufficient to re-trigger the crash (Test O2). This was unexpected: Test L on a faster reduced-model repro passed with the signature kept. The full-yaml setup (world_size=4 MoE EP + real weights + full layers) exposes some framework-side handling of the host-shadow tensor that the fast repro doesn't. Practical consequence: the minimum fix has to revert the signature too -- you can't keep just the new parameter and revert only the body.

    Conclusion: the minimal fix is the full revert of tensorrt_llm/_torch/auto_deploy/custom_ops/mamba/mamba_backend_common.py to its pre-#13566 state. mamba2_metadata.py and waives.txt parts of #13566 are intentionally untouched (the compute_extra_chunks_cpu helper added to mamba2_metadata.py is semantically identical to the inline loop it replaced in Mamba2Metadata.__init__, and Mamba2Metadata is not on the AutoDeploy path).

    Fixing PR: #14640

  5. added a commit that references this issue on May 27, 2026
    56d14df
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AutoDeploy<NV> AutoDeploy BackendCustomized kernels<NV>Specialized/modified CUDA kernels in TRTLLM for LLM ops, beyond standard TRT. Dev & perf.feature requestNew feature or request. This includes new model, dtype, functionality support

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