[bong-water-water-bong]

Two pin moves that go together: the add-on fix and the fork waiver removal.

pin	from	to	carries
config/gpu-kernels.config	94bc42e5*	fd69590c	gpu-kernels#60 - hrx_hc_post_comb comb layout (dst + hc*src, not dst*hc + src), so identity=0 no longer multiplies the residual by the transposed comb
third_party/llama.cpp	ced49c61	32559003	#220 (arch_name() is a std::string), #222 (small-rows matcher bounds exclusive + decline ARGSORT when no dispatch covers it), and 2cf6612 (drop the DSV4_HC_POST waiver)

(*the gpu-kernels pin had already moved forward in the branch's main; check_pins reports the move is ahead.)

Evidence (strixhalo, test-backend-ops -b HRX0)

• DSV4_HC_POST with the fixed add-on and the waiver removed: 6/6 - the four identity=0 shapes went from ERR 0.077612553 / 0.217479424 / 0.174023630 / 0.173662859 to OK, identity=1 unchanged;
• full suite: 4592/4592, Backend HRX0 OK; the only remaining waiver is the TOPK_MOE internal non-contiguous view.
• Add-on functional gates: tools/check.sh gfx1151 builds every artifact; its fingerprint gate still flags four pre-existing kernels without HRX_SYM on main (hrx_hc_post_comb, hrx_hc_comb, hrx_lightning_indexer, kqt_mm_ptq1) - untouched files fail identically, so it is not this hunk.

Merge gate

build is the required context (the engine build does not compile the add-on); the device evidence above is from the HRX build on strixhalo and the fork PRs. registry/architectures.json regenerated (sources: 32559003, 298/298) and tools/check_pins.py reports ced49c61b -> 32559003a is ahead.