diff --git a/benches/engine_control/CMakeLists.txt b/benches/engine_control/CMakeLists.txt index cbd158c1..25ddd80e 100644 --- a/benches/engine_control/CMakeLists.txt +++ b/benches/engine_control/CMakeLists.txt @@ -62,9 +62,21 @@ target_sources(app PRIVATE src/main.c src/control.c src/tables.c + src/smart_dwt.c ) target_include_directories(app PRIVATE src) +# MCU self-monitoring backend: vendor-specific where we have one AND +# the ADC is enabled. The G4 backend uses Zephyr's ADC API; on builds +# that explicitly disable ADC (e.g. the LTO experiments where the +# ADC IRQ-table interaction crashes the chip), fall back to the stub +# so the CSV row format stays uniform regardless of the variant. +if(CONFIG_SOC_SERIES_STM32G4X AND CONFIG_ADC) + target_sources(app PRIVATE src/smart_mcu_g4.c) +else() + target_sources(app PRIVATE src/smart_mcu_stub.c) +endif() + # -DENGINE_BENCH_TOTAL_SAMPLES=N on the west build line becomes # -DTOTAL_SAMPLES=N to the compiler. Default is 150 (QEMU smoke-test # friendly); Renode long runs pass 10000+. diff --git a/benches/engine_control/boards/nucleo_g474re.conf b/benches/engine_control/boards/nucleo_g474re.conf new file mode 100644 index 00000000..3ba6f0c7 --- /dev/null +++ b/benches/engine_control/boards/nucleo_g474re.conf @@ -0,0 +1,13 @@ +# NUCLEO-G474RE bench Kconfig overlay — enables ADC for smart-data MCU +# health snapshots (smart_mcu_g4.c). +# +# The DT overlay in `boards/nucleo_g474re.overlay` puts ADC1 + the +# two internal channels (TS=ch16, VREFINT=ch18) in place; without +# CONFIG_ADC, the driver source isn't compiled in and the +# DEVICE_DT_GET(DT_NODELABEL(adc1)) call in smart_mcu_g4.c fails to +# link with `undefined reference to __device_dts_ord_*`. +# +# CONFIG_ADC_STM32 auto-selects when CONFIG_ADC=y and the DT compatible +# match fires. + +CONFIG_ADC=y diff --git a/benches/engine_control/boards/nucleo_g474re.overlay b/benches/engine_control/boards/nucleo_g474re.overlay new file mode 100644 index 00000000..f410b42f --- /dev/null +++ b/benches/engine_control/boards/nucleo_g474re.overlay @@ -0,0 +1,43 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * Copyright (c) 2026 PulseEngine + * + * NUCLEO-G474RE bench overlay — enable ADC1 internal channels + * for smart-data MCU health snapshots. + * + * Zephyr's stock nucleo_g474re DTS leaves ADC1 disabled; the + * silicon-anchor protocol needs it to read the on-die temperature + * sensor (TS, channel 16) and internal reference (VREFINT, + * channel 18) so the H-row in the captured CSV records actual + * thermal and supply state alongside the algorithm timings. + * + * Channel numbers per STM32G474RE reference manual RM0440 §21.4.31 + * (ADC channels) — TS = IN16, VREFINT = IN18. + */ + +&adc1 { + status = "okay"; + st,adc-clock-source = "SYNC"; + st,adc-prescaler = <4>; + pinctrl-0 = <>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + channel@10 { + reg = <16>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; + + channel@12 { + reg = <18>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; +}; diff --git a/benches/engine_control/prj.conf b/benches/engine_control/prj.conf index c7939c02..e006f1c0 100644 --- a/benches/engine_control/prj.conf +++ b/benches/engine_control/prj.conf @@ -10,6 +10,12 @@ CONFIG_ISR_STACK_SIZE=2048 # Enable the primitives the benchmark exercises in the ISR / thread path. CONFIG_EVENTS=y CONFIG_RING_BUFFER=y +# 2048-sample ring (32 KB) is needed to absorb high-RPM ISR bursts on +# real silicon at 115200-baud UART throughput without dropping samples. +# RING_BUFFER_LARGE lifts Zephyr's static-assertion size cap so +# RING_BUF_DECLARE accepts the larger backing array. Inert for the +# QEMU/Renode CI lanes (their drops were 0 already at the smaller ring). +CONFIG_RING_BUFFER_LARGE=y # Pump tick rate up so k_timer can approximate 10 μs periods # (default is 10 ms / 100 Hz, way too coarse for 60 kHz targets). diff --git a/benches/engine_control/silicon/boards/nucleo_g474re/NOTES-llvm-lto-crash.md b/benches/engine_control/silicon/boards/nucleo_g474re/NOTES-llvm-lto-crash.md new file mode 100644 index 00000000..fcf32e13 --- /dev/null +++ b/benches/engine_control/silicon/boards/nucleo_g474re/NOTES-llvm-lto-crash.md @@ -0,0 +1,75 @@ +# LLVM-LTO + Gale build crashes on NUCLEO-G474RE silicon + +**Status:** known-broken on real silicon as of gale@`418c6b8c`. Renode CI passes the same build. +**Discovered:** 2026-05-10, during Phase B of the silicon-anchor protocol. +**Action:** silicon-anchor protocol intentionally **does not** capture an LTO variant for this board until this is fixed. + +## What runs + +- The build itself succeeds (FLASH 26,592 B, 1 surviving `gale_` symbol vs 3 in the rustc-direct gale build — LTO is doing meaningful inlining). +- `west flash --runner openocd` writes the ELF cleanly. +- The chip starts executing; a few bytes of the bench's `print_csv_header` reach the VCP (`# DWT rows: ...`, partial `# health rows:...`), then the chip resets / re-boots / faults. + +## Crash signature + +Halting the chip via `openocd ... halt` once it's in the fault state: + +``` +PC: 0x08004d9a → arch_system_halt at zephyr/kernel/fatal.c:30 +xPSR: 0x21000022 → IPSR ISR_NUMBER = 0x22 = 34 = External IRQ 18 +CFSR: 0x00000000 (no Cortex-M fault flags — not a hardfault) +HFSR: 0x00000000 +SHCSR: 0x00070000 (USGFAULTENA + BUSFAULTENA + MEMFAULTENA — all enabled, none active) +ICSR: 0x0400f822 (VECTACTIVE = 34 = ExtIRQ 18; pending: USG, MEM, BUS, SVCALL faults) +VTOR: 0x08000000 (vector table at start of flash, normal) +``` + +**External IRQ 18 on STM32G474 = ADC1_2 (ADC1 / ADC2 global interrupt)**, per RM0440 §11.3 (Interrupt and exception vectors). + +The chip is permanently sitting in `arch_system_halt`, which is reached via Zephyr's `z_irq_spurious` → fatal handler chain when an IRQ fires without a registered handler. + +## Hypothesis + +Smart-data emission's `smart_mcu_g4.c` uses Zephyr's ADC API (`DEVICE_DT_GET(DT_NODELABEL(adc1))` + `adc_channel_setup` + `adc_read`). Under the LLVM cross-language LTO link step, one of the following is happening: + +1. **Init-order race:** the ADC driver's `Z_DEVICE_DT_INST` static initializer registers the ADC IRQ handler in the IRQ table, but the LLVM linker is reordering the initializer such that an ADC interrupt fires (perhaps from an ADC self-calibration sequence in `smart_mcu_init`) before the handler entry is in place. +2. **IRQ table eviction:** LTO's aggressive inlining is folding the ADC IRQ handler symbol into the calling code, but the IRQ-table-vs-handler symbol matching logic in `gen_isr_tables.py` doesn't see the inlined version, leaving the table slot pointing at `z_irq_spurious`. +3. **Calibration state corruption:** STM32G4 ADC requires explicit calibration (`LL_ADC_StartCalibration`) before first conversion. If LTO reorders init-fn pointers vs the device-driver auto-init, calibration may be skipped and the first ADC operation triggers an internal error → ADC IRQ 18. + +Renode's `stm32f4_disco` simulation lane passes because Renode does not model the ADC peripheral with the same interrupt fidelity — the published Renode "LLVM+LTO+Gale = same as rustc-direct" claim is consequently silicon-untested. + +## Reproduction + +Toolchain matched at LLVM 21.1.8 (rustc 1.94.1 + brew `llvm@21` + brew `lld@21`): + +```sh +SDK_DIR=/Volumes/Home/zephyr-sdk/zephyr-sdk-1.0.1 +ARM_BIN="${SDK_DIR}/gnu/arm-zephyr-eabi" +GCC_LIB_DIR=$(dirname $("${ARM_BIN}/bin/arm-zephyr-eabi-gcc" -print-libgcc-file-name -mcpu=cortex-m4 -mthumb -mfloat-abi=soft)) +PICOLIBC_DIR="${ARM_BIN}/arm-zephyr-eabi/lib/thumb/v7e-m/nofp" +LLD_LIBS="-L${GCC_LIB_DIR} -L${PICOLIBC_DIR}" + +export PATH=/opt/homebrew/opt/llvm@21/bin:/opt/homebrew/opt/lld@21/bin:${ARM_BIN}/bin:$PATH +export ZEPHYR_BASE=/Volumes/Home/git/pulseengine/zephyr +export ZEPHYR_SDK_INSTALL_DIR=${SDK_DIR} +GALE_ROOT=/Volumes/Home/git/pulseengine/gale-smart-data + +west build -b nucleo_g474re -d /tmp/silicon-lto -s "$GALE_ROOT/benches/engine_control" -- \ + -DZEPHYR_TOOLCHAIN_VARIANT=llvm \ + -DCMAKE_TRY_COMPILE_TARGET_TYPE=STATIC_LIBRARY \ + -DZEPHYR_EXTRA_MODULES="$GALE_ROOT" \ + -DOVERLAY_CONFIG="$GALE_ROOT/benches/engine_control/prj-gale.conf;$GALE_ROOT/zephyr/gale_lto_overlay.conf" \ + -DCMAKE_EXE_LINKER_FLAGS="${LLD_LIBS}" \ + -DENGINE_BENCH_SWEEP=long +``` + +## Discriminating tests for next session + +1. Build LTO **without smart-data** (drop the `boards/nucleo_g474re.conf` `CONFIG_ADC=y` and conditionally compile-out `smart_mcu_g4.c`). If it boots, ADC interaction is confirmed. +2. Build LTO **without `CONFIG_ISR_TABLES_LOCAL_DECLARATION`** (remove from `gale_lto_overlay.conf`). Tests whether the local ISR-table machinery is the trigger. +3. Build with the `arm-zephyr-eabi-gcc` toolchain + `CONFIG_LTO=y` (GCC-side LTO, no clang). If GCC-LTO works and clang-LTO doesn't, narrows the bug to the LLVM linker plugin / lld. +4. Capture the chip's pre-fault `printk` output via openocd `tracesetup` + ITM trace, to see the last function called before the IRQ 18 fires. + +## Why this matters for the publication + +The "Three Quiet Barriers" blog post claims LLVM-LTO+Gale produces handoff timing equivalent to rustc-direct+Gale (both at 347 cyc on Renode `stm32f4_disco`). On real `nucleo_g474re` silicon, the LTO build does not run at all. Until this crash is root-caused, **no headline "LLVM cross-language LTO works on this MCU family" claim can be sustained for the G4** — only for the F4 (which the published Renode CI uses). diff --git a/benches/engine_control/silicon/boards/nucleo_g474re/NOTES-wasm-cross-lto-spike.md b/benches/engine_control/silicon/boards/nucleo_g474re/NOTES-wasm-cross-lto-spike.md new file mode 100644 index 00000000..df48f7b4 --- /dev/null +++ b/benches/engine_control/silicon/boards/nucleo_g474re/NOTES-wasm-cross-lto-spike.md @@ -0,0 +1,2260 @@ +# Wasm-cross-LTO via wasm-ld → loom → synth — spike report + +**Status:** structurally proven, cyclically gapped by upstream tooling issues. +**Date:** 2026-05-10. **Re-run on upgraded tools: 2026-05-29 (see update below).** + +--- + +## UPDATE 2026-06-02 — OPTIMIZATION PHASE begins (sem works; now widen the wasm surface) + +Goal of this phase (30-min /loop, cron 1d91fb59): track new synth/loom releases, feed the +maintainer perf+optimization recommendations, and compile MORE of the bench through +`clang→wasm-ld→loom→synth` so there are more codegen paths to optimize. Plus a 4h-no-release +reminder rule: ping both repos + watch comments if either goes quiet 4h. + +### synth v0.11.15 — regression PASS +v0.11.15 is one fix (#206, ARM32 indexed loads); release note says Cortex-M Thumb-2 was +already correct. Confirmed: rebuilt the sem object — **byte-identical** to the v0.11.14 +`faithful4.o` (208+494 B code, 1588 B ELF, `cmp` clean). So the **907-cyc handoff transfers +without a reflash**. loom unchanged (v1.1.5). + +### Second wasm function: the control ALGORITHM (`control_step`) +Reshaped to scalar in/out: `control_step_decide(rpm, load, coolant, knock) -> spark<<16|fuel`. +Pure integer + two static tables (`int8[20][20]`, `u16[20][20]`). **Compiles on v0.11.15**: +376 B, 0 relocs. New paths vs `decide`: integer division + a read-only data segment. +Artifacts: `/tmp/wasm-algo-poc/` (control_wasm.c, tables.c, control.loom.wasm, control_algo.o). + +Hand-decoded Thumb-2 → filed **[synth#210](https://github.com/pulseengine/synth/issues/210)**: +- 🔴 **suspected coolant-operand drop**: `movw r2,#80; subs r3,r2,r2` → `(80-coolant)` becomes `80-80=0`, + zeroing enrichment on the mid-range path (#193-class). Discriminator vector: `(3000,50,40,0)` → + correct fuel **2645**; bug gives **2300**. Gates the algorithm's on-silicon number. +- 🟡 const-divisor strength-reduction + guard elision (4× `udiv`+`udf` for `/500 /5 /80 /1000`). +- 🟡 emit data segments as relocatable `.rodata` (R_ARM_THM_MOVW/MOVT_ABS) instead of baked + linmem `[fp,off]` addresses with a 64 KB gap — read-only-data analogue of the call-reloc work. +- 🟡 regalloc: 6 spills with r9/r10 free + no constant CSE → 376 B vs ~100 B gcc. + +**Host-side wasm testbed stood up (08:05):** `/tmp/wasm-algo-poc/wasm_oracle.sh` runs +`control_step_decide` in wasmtime 42 and checks vs the native reference — ALL 4 vectors PASS, +incl. the coolant discriminator `(3000,50,40,0)→fuel 2645`. Proves our wasm is correct, so +synth#210's coolant-drop is purely synth's ARM lowering — posted as confirmation on the issue. +First piece of "test environment as wasm": a fast, hardware-free functional oracle for any +loom/synth input. (Caveat: `wasmtime --invoke` must be one-shot per process — loop capture empties.) + +**flight_control bigger example started (08:31):** compiled `controller_step` (the second function, +from the bigger composed bench) as a scalar-in/u32-out wasm shim → synth v0.11.15 gives 348 B, 0 relocs, +**functionally correct** in the wasmtime oracle (4 vectors, `asr.w` SAR lowering correct). Codegen +reinforces #210 (no constant CSE, verbose selects, spills) and surfaces a NEW recommendation: the +`[-127,127]` saturation clamps should use Thumb-2 **`SSAT`** (one instruction) instead of ~12-instruction +compare/boolean/select sequences ×3 axes. Posted to synth#210. Oracle (`wasm_oracle.sh`) now covers +engine_control algo + flight_control controller — ALL PASS. (`flight_control/src/control.c`.) + +**filter_axis added (09:01):** the complementary-filter hot math `((prev+gyro)*980 + accel*20)/1000` +as a value-in shim → synth v0.11.15: 66 B, correct on 4 vectors incl. negative (`-1917`, sdiv toward +zero). Finding: **signed** constant division emits TWO dead guards (div-by-zero + INT_MIN/-1 overflow, +~12 of 66 bytes) since the divisor 1000 can be neither — sharper case of #210 Opt 1. Posted to #210. +Oracle now covers 3 functions (engine `control_step`, flight `controller_step`, flight `filter_axis`), +ALL PASS — wasm+native agree everywhere; only divergence is the control_step coolant-drop (#210 headline). + +**ARM-level testbed + validated escalation (09:32):** built `/tmp/wasm-algo-poc/arm_harness.py` — runs +synth's Cortex-M output under unicorn (tables loaded at `[fp+0x10000]`/`[fp+0x10190]`, fp=linmem base, +args r0–r3). VALIDATED on a trivial `add3` (=60, matches wasmtime). Ran the engine `control_step_decide` +ARM output: returns `0xfc2703e8` vs wasm-correct `0x00210a55`. Tracing the table accesses pinned it: +`lb=8=40/5` → **`load_bin` is fed the coolant arg (r2=40) not load (r1=50)**, and `rb` is clobbered +between the two lookups (fuel reads row6 correct, spark reads row1). So #210 is broader than a dropped +coolant operand — it's **4-arg parameter→use mis-routing** (#193/#204 family). Posted validated +escalation + offered the harness (arm_harness.py + control_algo.text.bin + tables.blob) to synth#210. +This means the engine algorithm's silicon cycle number must wait for the param-routing fix (a buggy +cycle count would be unrepresentative — the control flow itself is wrong). + +Testbed now has two layers: wasm oracle (3 fns, functional) + ARM-level unicorn harness (validates the +actual synth output). + +## UPDATE 2026-06-02 10:01 — SECOND SILICON DATA POINT (filter_axis, wasm-cross-LTO vs native) + +ARM-harness-checked all three functions' synth output: **filter_axis CORRECT** on ARM; control_step +mis-routes params (#210); controller_step has an **elevator saturation sign-flip** (+127→−127, upper +clamp miscompiled, 7-arg ABI is r0–r6). Since filter_axis is correct AND has no fp/table dependency +(clean AAPCS r0–r2 drop-in), measured it on silicon directly — bypassing the #210 blocker. + +Built `/tmp/filter-bench` (standalone Zephyr app, links `filter_algo.o`; calls the synth symbol via a +function pointer with the thumb bit set, since synth#170 = no `$t` symbol). Flashed G474RE, DWT CYCCNT, +min/200, head-to-head vs native gcc -O2 of identical C (both via volatile fn-ptr = identical overhead): + +| vector | synth (wasm→loom→synth) | native gcc | ratio | +|---|---|---|---| +| (1000,100,500) | 41 cyc | 21 cyc | 1.95× | +| (-2000,50,-300) | 41 cyc | 21 cyc | 1.95× | +| (0,2,0) | 39 | 19 | 2.05× | + +**~1.95× native — matches the sem primitive's 1.92× (907/471).** Functionally correct on hardware. +On a function this tiny the whole gap is `/1000`: synth `sdiv` + 2 dead guards vs gcc reciprocal-multiply +(synth#210 Opt 1 = highest-leverage fix). Run artifact: +`silicon/runs/2026-06-02-nucleo_g474re-filter-axis-wasm-vs-native-v0.11.15/`. Posted silicon perf + +controller saturation bug to synth#210. + +## UPDATE 2026-06-02 10:31 — gap DECOMPOSED on silicon (correction to the 1.95× figure) + +Built variants v_full/v_nodiv/v_div through the pipeline, flashed, measured (DWT min/200, overhead now +min/200 back-to-back = **1 cyc** true floor; the earlier 1.95× used a single-sample ovh=5 overestimate). +Reproduced identically across two flashes: + +| variant | synth | native | ratio | +|---|---|---|---| +| full `((p+g)*980+a*20)/1000` | 46 | 19 | 2.42× | +| nodiv `((p+g)*980+a*20)` | 29 | 12 | 2.42× | +| div `x/1000` | 40 | 15 | 2.67× | + +**Decomposition of the 27-cyc gap:** base codegen (mul+add) = 17 cyc (spills/no-CSE) — the LARGER lever; +divide handling = 10 cyc (sdiv+2 dead guards vs reciprocal-multiply). So **Opt 3 (regalloc/CSE) ≥ Opt 1 +(const-div)** — corrected my earlier "it's all the divide" claim on #210 (even divide-free code is 2.42×). +Together they'd take this function 46→~25, near native. Run: silicon/runs/2026-06-02-nucleo_g474re- +filter-decomposition-v0.11.15/. (filter_axis headline number corrected: 2.42×, not 1.95×.) + +## UPDATE 2026-06-02 11:01 — bigger example (flight_control) RUNS on silicon (native baseline) + +`flight_control` (the 5-primitive composed bench) builds + flashes + runs on the G474RE (Phases 1-4; +FLASH 23.7KB RAM 52.8KB). Native baseline, step 1/5 (sensor_hz=500, contention=0, payload=16), 6 events: +`algo=141 handoff=1307 t_lock=339 t_post=858 t_round=1987 t_bcast=748` cyc. +**STALL at step 2/5** (sensor_hz=1000, payload=32): `count=0 [drain_timeout]`, sweep never reaches +`=== END ===`. This is a flight_control **bench-logic** issue at the higher sensor rate (actuator-drain +path), NOT synth/loom — flag for the bench owner; the short-sweep 1000 Hz cell needs a drain fix in +`flight_control/src/main.c`. The bench `algo` segment (141 cyc) = filter_step+controller_step, i.e. the +same math already wasm-ified (controller_step + filter_axis); a wasm-cross-LTO flight run would swap that +segment in. Run: silicon/runs/2026-06-02-nucleo_g474re-flight_control-native-baseline/. + +## UPDATE 2026-06-02 11:31 — #210 root cause LOCALIZED (arg-matrix diagnostic) + +Ran a matrix through wasm→loom→synth→ARM in the unicorn harness: `add4`, `add4d` (4 args + divide), +`add5`, `add6` — ALL correct. Only `control_step` (4 args + 2 indexed table loads) mis-routes. So the +bug is **not** the multi-arg ABI and **not** divide-with-args; it's the **indexed-memory-load path**: +table-address materialization (movw/movt base + mul index) clobbers the param registers (r1=load, +r2=coolant) before `load_bin`/`rpm_bin` read them → `load_bin` sees coolant, `rb` clobbered between +lookups. Posted as root-cause narrowing on synth#210. Now HOLDING #210 (no maintainer reply yet today); +the 4h-no-activity reminder will nudge. `filter_axis` (no memory) stays correct + measured (2.42×), so +the value path is solid — this routing bug is the sole gate on table-based functions. + +## UPDATE 2026-06-02 12:01 — 4h no-activity reminders filed + +>4h since last release/maintainer activity. synth: posted a friendly status nudge on the existing #210 +(didn't fragment a new issue) summarizing the silicon results + priority asks (param-routing fix > Opt1/ +Opt3 > SSAT). loom: filed status/sync issue **loom#155** (907-cyc result + forward question on inlining +the flight_control *composed* algo — the next genuine two-function seam for loom). Both reminders now +tracked in state; future firings watch comments, don't duplicate; clock resets on next real release or a +maintainer comment. + +## UPDATE 2026-06-02 12:32 — loom maintainer engaged (#155); composed module delivered + +loom reply: aliasing is sound (single Z3 memory Array → read-sees-write by address equality); the real +limit is the #151 inliner only proving pure/no-trap/leaf/straight-line/**no-memory** callees, so a +memory-reading callee (`controller_step` reads `flight_state`) **reverts** (sound no-op, not a miscompile). +They committed to building **general memory-through inline verification** and asked for our multi-fn module ++ oracle as the validation substrate. DELIVERED: built `flight_algo` = `filter_step`(writes *st) → +`controller_step`(reads *st) as a 3-function wasm module (real through-memory seam), verified correct in +wasmtime (`drive(...)=0x07fdf307` = native bit-for-bit), confirmed loom v1.1.5 reverts it as predicted, +posted module + recipe + base64 + oracle/harness to loom#155. Artifacts: /tmp/flight-wasm/. + +## UPDATE 2026-06-02 13:01 — #210 regalloc bug GENERALIZES to pointer params (composed algo blocked) + +Tried to get the synth "before" (loom-reverted) silicon number for the composed `flight_algo`. Compiled +it (flight_algo 62B + filter_step 256B + controller_step 414B, 2 internal-call relocs; `drive` skipped), +linked the internal calls, ran in the unicorn harness with **fp=0**. Result: fp=0 contract HOLDS and the +entry pointers are correct (r0=&st, r1=&s), but `filter_step` **clobbers the `s` pointer register** mid-body +(r1: 0x20001100 → 0xfffffe70, a loaded/computed value) → unmapped read. So the composed algo hits the +**same #210 regalloc/param-clobber bug, now generalized to POINTER PARAMS** — not just table indices: any +memory-accessing function can overwrite a live pointer/param register. ⇒ composed-algo silicon number is +BLOCKED on the #210 fix; **scope note for the maintainer's next #210 reply**: the fix must keep live +pointer/param regs across memory-accessing bodies, not only table-index materialization. (Held the comment +— #210 already has the root cause; staged this generalization for when they re-engage.) + +## UPDATE 2026-06-02 13:32 — loom ACTIVELY IMPLEMENTING memory-through inlining + +loom maintainer confirmed the substrate + oracle (`0x07FDF307` is now their differential gate), reproduced +the v1.1.5 no-op revert, and root-caused **two general fixes**: (1) thread the caller's memory `Array` into +the callee-body modeling + share the load-encoding helper with the main encoder (→ bit-identical Z3 for +modeled-call vs inlined-body), (2) deterministic per-encode havoc naming so corresponding impure calls +unify (else spurious revert). Implementing now behind Z3 + negative-soundness + my-oracle + corpus gates; +will cut a release + report before/after. I hardened their gate with **5 verified native==wasmtime vectors** +(v2/v4 hit controller_step's ±127 saturation rails) and flagged that synth v0.11.15 miscompiles this +composed module on ARM (filter_step clobbers the s-ptr — pointer-param generalization of #210), so the +synth-side silicon number may lag the loom-side proof (the inlined output might dodge it — fewer live ptrs). + +## UPDATE 2026-06-02 14:02 — loom BUILT memory-through inline verification; helping land controller_step + +loom now verifies memory-reading inlines as a sound capability (minimal `getx(p)` inlines+verifies; +soundness guard: correct load proven, wrong-offset rejected; deterministic havoc; 387 tests; oracle +0x07FDF307 holds) — branch `feat/155-memory-through-inline-verification`. controller_step not landing yet +for 3 reasons, helped on all: (1) `drive` made it 2-call-site (clang folded flight_algo into drive) → sent +**drive-free flight_seam.wasm** (single-call = on-device); (2) filter_step's partial-width `i32.load16_s` +unmodeled → stays opaque/havoc, only controller_step needs inlining (full-width); (3) even single-call it +hits a FALSE counterexample (sound conservative revert) → built+sent **min_seam.wasm** (minimal `seam=wr;rd`, +rd reads what wr wrote with controller_step's clamp/select suspect, rd single-call, 2 real calls verified) + +native gate table, to bisect; pointed to `benches/flight_control/src/control.c`. Artifacts +/tmp/flight-wasm/{flight_seam,min_seam}.wasm. + +## UPDATE 2026-06-02 15:02 — loom v1.1.6 SHIPPED (our feature); verified; silicon gated on synth#210 + +loom **v1.1.6** released: "Verified inlining of memory-reading callees (gale flight_control seam, #155)" — +the feature our substrate drove. My isolation modules pinned the false counterexample (it was the *writer*, +not select/param-reuse → loom now keeps memory-WRITING callees opaque, inlines memory-READING ones, Z3- +proven). Built+installed v1.1.6 from source (loom-cli; no binary asset). VERIFIED on our modules: +- `flight_seam`: controller_step inlined (714→826B wasm; synth ARM output relocs 2→1, flight_algo 62→488B). +- Oracle on v1.1.6 output: `drive=0x07FDF307` + saturation vectors (v2=0x07817F81, v4=0x0700817F) PASS. +⇒ loom side DONE + correct. **Silicon cycle delta GATED on synth#210**: the v1.1.6-inlined module still +faults in the fp=0 unicorn harness at pc=0x25a *inside the kept `filter_step` call* (synth pointer-clobber, +unchanged). Inlining controller_step doesn't dodge it. Delivered the staged #210 generalization (bug hits +pointer params, not just tables) + connected to the loom milestone — #210 now blocks BOTH the engine algo +and the flight composed-algo silicon numbers. Artifacts /tmp/flight-wasm/*.116.wasm. + +**15:32 follow-up:** loom maintainer confirmed #155 COMPLETE (controller_step inline shipped+verified; +silicon = synth's problem, not loom's) and invited the writer side. Filed **loom#157** (inline memory- +WRITING callees / by-body store modeling) with the min_seam writer repro (full-width stores) + differential +gate — loom-independent of synth, advances toward full filter_step dissolution (also needs partial-width +loads, noted). loom#155 done; loom#157 open. + +## UPDATE 2026-06-02 16:32 — loom v1.1.7 (writer side); KEY FINDING + a regression + +loom **v1.1.7** shipped the writer-side inline (#157, requested ~1h earlier): `min_seam` now **fully +dissolves** (both wr+rd inline, 0 calls). **KEY FINDING:** the fully-dissolved min_seam runs **correctly on +Cortex-M** (unicorn fp=0) — synth#210's pointer-clobber only bites at CALL boundaries, so a **fully-inlined +`flight_algo` would dodge #210 entirely**, enabling the composed-algo silicon measurement WITHOUT the synth +fix. ⇒ new primary path to the flight number = loom full dissolution, not waiting on synth#210. + +**BUT v1.1.7 REGRESSION (filed loom#159):** `flight_seam` no longer inlines `controller_step` (v1.1.6 did: +1 call; v1.1.7: 2 calls, neither inlined). Trigger = reader-after-partial-width-writer (min_seam full-width +control still dissolves). The v1.1.7 writer path attempting the un-modelable partial-width `filter_step` now +also poisons the following reader-inline. Filed with evidence + min_seam control + the `seam16` partial-width +repro (the #157 follow-up). Not a miscompile (oracle holds) — a lost-optimization regression. + +## UPDATE 2026-06-02 17:02 — CORRECTION: full dissolution does NOT dodge synth#210 + +Tested the 16:32 "full dissolution dodges #210" claim by manually fully-inlining flight_algo into ONE flat +function (0 calls) → synth → ARM → unicorn: **still clobbers** r1 (s-ptr) → 0xfffffe70 at pc=0x76, *identical* +to the called version. So **synth#210 is REGISTER-PRESSURE-driven, not call-boundary-driven** (the engine +`control_step` was also a single function). The min_seam "flat=clean" result was misleading — min_seam is +trivially small (stays under the pressure threshold); flight_algo's many int16 fields trip it regardless of +inlining. ⇒ **full dissolution does NOT unblock the flight silicon number; synth#210 is the singular blocker.** +Corrected on loom#159 (the v1.1.7 regression there is still real as an optimization matter, just not a silicon +unblock). New synth#210 data point (staged): clobber reproduces on a flat no-call function → purely regalloc +not keeping pointer/param regs live across memory-address materialization. + +## UPDATE 2026-06-02 18:02 — synth v0.11.16 FIXES #210; ENGINE control_step ON SILICON (2nd data point ✅) + +synth **v0.11.16** (a804390) landed the #193 param-liveness reservation → the coolant clobber is **fixed**. +VERIFIED: `control_step` correct on ARM (all 4 vectors, coolant=40→0x00210a55/fuel 2645) AND on real silicon +(selfcheck synth==native==0x00210a55). The manually-flat flight_algo is also correct now. + +**MEASURED the engine `control_step` on silicon** (the original part-3 "second data point" goal — ACHIEVED): + +| function | wasm-cross-LTO (v0.11.16) | native gcc | ratio | +|----------|---------------------------|-----------|-------| +| k_sem_give handoff | 907 | 471 (LLVM-LTO) | 1.92× | +| filter_axis | 46 | 19 | 2.42× | +| **control_step (engine algo)** | **188** | **80** | **2.35×** | + +(DWT min/200; synth path includes the fp-setup trampoline pointing `[fp+0x10000]` at the lookup-table blob.) +Gap dominated by 4× `udiv` (binning divides + dead guards) + table-index regalloc = synth#209 Opt1/Opt3. +Run: silicon/runs/2026-06-02-nucleo_g474re-control_step-engine-algo-synth-v0.11.16/. Reported to synth#210. + +## UPDATE 2026-06-02 18:43 — loom v1.1.9 (partial-width); synth#212 + loom#163 filed + +loom **v1.1.9** shipped partial-width inlining (our #161): verified seam16→0 calls (fully dissolves), +flight_seam→1 (filter_step now blocked ONLY by `i32.div_s`, not partial-width), divseam→1 (rdd div-blocked). +synth#210 correctness CLOSED + maintainer **starting Opt1 (div SR + guard elision)** — re-sent self-contained +control.loom.wasm + 4 vectors for their regression guard. FILED **synth#212**: inlined-controller-after-opaque- +call reads stale divided fields on v0.11.16 (cmd 0x07fd7f7f vs 0x07fdf307 — ail/ele wrong via ÷-path, rud/yaw ++state correct; FLAT version correct; loom wasm correct in wasmtime ⇒ synth lowering bug; maintainer requested). +FILED **loom#163**: div_s modeling (divseam repro, signed-trunc vectors) = last piece for full flight_algo dissolution. + +## UPDATE 2026-06-02 19:42 — loom v1.1.10 FULL dissolution; COMPOSED flight_algo ON SILICON (3.35×) + +loom **v1.1.10** (div_s, #163) → `flight_algo` **fully dissolves** (filter_step+controller_step both inline, +0 calls, one 784B fn; verified unicorn-correct + oracle 0x07FDF307). Compiled through synth v0.11.16 → ARM → +**measured on silicon: synth 332 vs native 99 (flat) = 3.35×, CORRECT (0x07fdf307)**. The bigger-example +composed algo, fully fused, running on hardware. Run: silicon/runs/2026-06-02-nucleo_g474re-flight_algo- +FULLY-DISSOLVED-loom1.1.10-synth0.11.16/. Posted to loom#163. + +**Full silicon table (wasm-cross-LTO vs native):** +| | synth | native | ratio | +|---|---|---|---| +| k_sem_give handoff | 907 | 471 (LLVM-LTO) | 1.92× | +| filter_axis | 46 | 19 | 2.42× | +| control_step (engine algo) | 188 | 80 | 2.35× | +| flight_algo (composed, fully dissolved) | 332 | 99 | 3.35× | + +CORRECTION: fp=0 + real pointers WORKS on HW — the earlier flat_flight "silence" was serial-capture flakiness +(0 bytes), NOT a fault. Retracted the "pointer/linmem HW blocker" worry. Lesson: capture occasionally misses → retry. + +## UPDATE 2026-06-02 20:12 — v0.11.17 guard-elision: control_step −14 cyc, BUT regresses flight_algo (#215) + +synth **v0.11.17** (Opt1 guard-elision) measured on silicon: **control_step 188→174** (−14 cyc, 2.35×→2.15×, +correct 0x00210a55; .text 390→364). Reported to #209. **BUT v0.11.17 REGRESSES the fully-dissolved flight_algo** +(0x07FDF307 v0.11.16 → 0x20FD1014 v0.11.17 — controller-tail fields wrong, filter/divides correct; control_step +unaffected) → filed **synth#215** (confirmed in unicorn; guard elision perturbs regalloc/layout in the bigger fn). +synth#212 (inlined-after-call) FIXED in **v0.11.18** (building, R12/IP reserve). loom#163 closed — loom capability +series COMPLETE (maintainer graceful close-out). + +## UPDATE 2026-06-02 20:42 — v0.11.18 FIXES #212 + #215; all 4 data points correct + guard-elision + +synth **v0.11.18** (R12/IP scratch reserve) FIXED both #212 (inlined-after-call) and #215 (guard-elision +flight_algo regression). Re-measured on silicon, both correct: +- control_step: 188(v16)→174(v17)→**172**(v18), native 80 → **2.15×** (0x00210a55). +- flight_algo (composed, fully dissolved): 332(v16)→wrong(v17 #215)→**315**(v18), native 99 → **3.18×** (0x07FDF307). + +Confirmed #215 fixed (unicorn + silicon); reported v0.11.18 numbers to #209. **Current silicon table:** +| | synth | native | ratio | +|---|---|---|---| +| k_sem_give handoff | 907 | 471 (LLVM-LTO) | 1.92× | +| filter_axis | 46 | 19 | 2.42× | +| control_step | 172 | 80 | 2.15× | +| flight_algo (composed) | 315 | 99 | 3.18× | + +## UPDATE 2026-06-02 21:42 — v0.11.19 (Opt1b reciprocal-mul) REGRESSES control_step (won't compile) + +synth **v0.11.19** = Opt1b (UMULL reciprocal-multiply for *unsigned* constant division, #209). #215 closed. +REGRESSION: **control_step FAILS to compile** — "register exhaustion: all allocatable registers live on the +stack." It's the only fn with **multiple unsigned-const divides** (/500 /5 /80 /1000) → 4× UMULL (each +RdLo+RdHi+magic+multiplicand) under the R0–R8 pool (post-#212 R12 reserve) exhausts the allocator (bails vs +spills). Scope: ONLY control_step; signed-div fns (filter_axis, flight_algo, divseam) + no-div fns OK (Opt1b +is unsigned-only). Compiled fine on v0.11.18 (172 cyc). Filed on #209 (comment 4606581465) w/ 3 fix options +(spill-under-pressure / cost-gate reciprocal-mul→udiv fallback / recompute magic per-use). flight_algo +unchanged on v0.11.19 (signed divides untouched → no reflash). + +## UPDATE 2026-06-02 23:12 — v0.11.20 Opt1b measured: NEAR-NEUTRAL on M4; Opt3 is the real lever + +synth **v0.11.20** (#217 cost-gate fix) → control_step compiles with all 4 UMULL (udiv:0), correct. Silicon: +188(v16)→172(v18 guard-elision)→**168(v20 reciprocal-mul)**, native 81 → **2.07×**. Opt1b bought only **−4 cyc**. +KEY (honest, corrects my ~110-135 prediction): **Cortex-M4 has fast HW `udiv` (~2-12 cyc), so reciprocal-multiply +is near-neutral here** (a win only on M0/M0+ without HW divide; grew code 350→410 B). ⇒ the remaining ~2× gap is +**general codegen (regalloc/CSE/spilling = Opt3)**, NOT division — confirmed by the filter_axis decomposition AND +now control_step (divides fully optimized, still 2×). Redirected the lever to Opt3 on #209. + +**Standing silicon table (all correct on HW):** sem 1.92× | filter_axis 2.42× | control_step **2.07×** (v0.11.20 +full Opt1) | flight_algo(composed) 3.18× (v0.11.18). loom done. + +NEXT: watch #209 for **Opt3 (regalloc/CSE)** = the real 2× lever → re-measure on land. Run: +silicon/runs/2026-06-02-nucleo_g474re-control_step-v0.11.20-Opt1b-reciprocal-mul/. Testbed `../wasm-testbed/`. + +--- + +## UPDATE 2026-05-29 — re-run on synth v0.11.0 / loom v1.1.1 / meld v0.19.0 + +Tools upgraded (synth v0.3.0→v0.11.0, loom v1.0.3→v1.1.1, meld v0.2.0→v0.19.0). +The two **original** blockers are fixed; **two new blockers** took their place, so +the silicon-cycle measurement is still gated. + +### What got fixed +- **synth#120 vreg-unmapped panic — FIXED.** 194 functions (incl. the previously + panicking `gale_compute_ipi_mask`) now compile clean. `compiler_builtins::float::div` + now produces a clean `Result::Err`, not a panic (v0.5.0 panic→Result conversion holds). +- **loom v1.0.3 inline hang — GONE.** v1.1.1 no longer hangs; it catches each Z3 + failure and reverts the function, so the run completes. + +### New blockers (filed 2026-05-29) +- **[synth#167](https://github.com/pulseengine/synth/issues/167) (BLOCKER).** synth's + `arm` backend now lowers **every** wasm `call` (internal *and* import) to an identical + `__meld_dispatch_import` placeholder `bl` (`f000 d000` → garbage `0xC00000`+idx), with + **0 relocations and no inlining** — in both `--relocatable` and full `--cortex-m` modes. + Minimal repro: a 2-func no-import module's internal `call $callee` becomes `bl ` + even though the callee sits at a known address in the same object. The `synth backends` + table marks the `arm` backend `ELF: no`. ⇒ The merged `.o` is **non-linkable** into + Zephyr; this is a regression vs v0.3.0 (which produced linkable objects). **This is the + reason the seam no longer dissolves on v0.11.0** — `gale_k_sem_give_decide` is not + inlined and its call is an unrelocated placeholder. +- **[synth#168](https://github.com/pulseengine/synth/issues/168).** `arm` regalloc: + "register exhaustion: no consecutive pair of free registers for i64" hard-fails on + `compiler_builtins::float::div::div`. Dodgeable by not linking float div (see below). +- **[loom#145](https://github.com/pulseengine/loom/issues/145).** Z3 `SortDiffers + { BitVec 64 vs 32 }` (the old #98, claimed fixed in v1.0.0) **still reproduces** on + i64-heavy modules, plus new `bool.rs:70` / `bv.rs:174` `unwrap()`-on-`None` panics. + Now caught+reverted (good) but the inliner is a no-op on i64 and emits 21 MB+ of panic + spew (5796 + 2511 + 773 panics on the 1 MB merged module). + +### Local recipe fix discovered this run +The original recipe used `wasm-ld --whole-archive --export-all`, which pulls in ALL of +compiler_builtins (incl. the float::div that trips synth#168). For the hot-path target, +re-link **without** `--whole-archive` and export only the needed symbols — the linker's +DCE drops float::div and shrinks the module 1 MB → ~5 KB: + +```sh +wasm-ld --no-entry --export=z_impl_k_sem_give --export=gale_k_sem_give_decide \ + --allow-undefined --gc-sections libgale_ffi.a shim.wasm.o -o merged.both.wasm +``` + +This sidesteps synth#168 entirely. The route still hits synth#167 (calls become +meld-dispatch placeholders), so **no linkable object / no silicon measurement yet.** +Blocked on synth#167. + +### UPDATE 2026-05-30 — synth v0.11.1 retest (#167 + #168 FIXED) + +synth **v0.11.1** (`6f7e3ac8`, PR #169) fixes both: + +- **synth#167 FIXED.** Internal + import calls now emit real `R_ARM_THM_CALL` + relocations with the corrected `f000 f800` Thumb-BL placeholder (was `f000 d000`, + which baked in a ~+0x600000 garbage addend). `merged.both.wasm` → `merged.both.o` + now carries 7 relocations (the `z_impl → gale_k_sem_give_decide` seam call as + `R_ARM_THM_CALL → func_6`, plus the 5 kernel imports) and links with `ld -r`. + Note the seam is a **relocated call, not inlined** — so this route currently maps + to a rustc-direct-shaped seam (≈574 cyc class), not LLVM-LTO's folded body + (471 cyc). Inlining is a separate synth/loom capability (synth#170 / loom#145). +- **synth#168 FIXED.** `--all-exports` on the full 1 MB module no longer hard-fails; + synth emits `warning: skipping function … register exhaustion` and continues — + 750/824 functions compiled, 74 i64-heavy compiler_builtins (incl. `float::div`) + skipped. Graceful degradation. + +**New remaining blocker — [synth#173](https://github.com/pulseengine/synth/issues/173).** +The import-call relocations target generic `func_N` symbols, NOT the wasm import +field names (`k_spin_lock`, `z_unpend_first_thread`, …). synth knows the names (it +logs them) but emits none into the ELF, so the object still can't resolve against +the real Zephyr kernel. A `--defsym func_0=k_spin_lock …` aliasing layer is a viable +local stopgap to chase the silicon number; proper fix is upstream (#173). + +### UPDATE 2026-05-30b — `--defsym` workaround test surfaced a +4 call bug ([synth#174](https://github.com/pulseengine/synth/issues/174)) + +Applied the `--defsym func_N=` workaround for #173 + a stub object, +linked `merged.both.o` to an absolute image — links cleanly, all symbols resolved. BUT +raw-Thumb disasm shows **every `R_ARM_THM_CALL` resolves to symbol+4**: `z_impl_k_sem_give` +calls `gale_k_sem_give_decide+4` (skipping its first two `movs`), `k_spin_lock+4`, etc. +Minimal repro: `caller`→`callee` lands at `callee+0x4`. The `0xF800` "zero" placeholder +from the #167 fix nets to +4 under R_ARM_THM_CALL. **So even with #173 worked around, the +linked code is wrong** — calls enter callees one instruction-pair late. + +Also confirmed: synth emits no `$t`/`$d` mapping symbols, so neither `arm-zephyr-eabi-objdump` +nor `llvm-objdump` will decode the output (must dump `.text` to flat binary + `-Mforce-thumb`). +That's tracked in synth#170. + +**Net gating after the v0.11.1 retest:** #174 (+4 call offset, BLOCKER for execution) → +#173 (import naming) → #170 ($t mapping symbols / standalone resolution) → then the seam is +a relocated call (not inlined), so silicon would land in the rustc-direct class, not LTO parity. + +### UPDATE 2026-05-30c — synth v0.11.2 (#173 FIXED; #174 still blocks) + +v0.11.2 (`f11ed177`): **#173 FIXED** — import-call relocations now carry the real wasm +field names (`k_spin_lock`, `z_unpend_first_thread`, …), so the merged object links against +the Zephyr kernel with **no `--defsym` aliasing**. **#174 still reproduces** (mini.wat: +`bl 4 `) — the +4 call offset remains the execution blocker. #170 still open. +Net gating now: **#174 (+4, BLOCKER)** → #170 (mapping symbols) → relocated-call-not-inlined. + +### UPDATE 2026-05-30d — synth `8f213351` (#174 FIXED): TOOLCHAIN NOW PRODUCES CORRECT LINKABLE CODE ✅ + +synth commit `8f213351` (#177) fixes #174 (BL placeholder -4 addend). Retest: + +- **minimal**: `caller` → `bl 0x8000000` = `callee` exactly (was `callee+0x4`). +- **gale seam** (`merged.both.wasm` → `merged.both.o`, linked with real-named stubs, **no + --defsym**): all 6 calls in `z_impl_k_sem_give` resolve to the exact symbol entry — + `gale_k_sem_give_decide`@0x0 (the C↔Rust seam), `k_spin_lock`, `z_unpend_first_thread`, + `arch_thread_return_value_set`, `z_ready_thread`, `z_reschedule`. + +**The wasm-ld → synth → ARM ET_REL route now emits a correct object that links against the +Zephyr kernel.** Closed across the loop: #167, #168, #173, #174. Remaining: #170 ($t/$d +mapping symbols + standalone --cortex-m resolution) — disassembly/standalone only, NOT an +execution blocker for the --relocatable→ld path (function symbols carry the Thumb bit). + +**What's left to an actual silicon number:** (1) integrate `merged.both.o` into the bench — +override the bench's native `z_impl_k_sem_give` so the linker pulls ours, provide the panic +stub (func_5), build + flash the G474RE; (2) capture cycles. Expected class: the seam is a +**relocated call, not inlined**, so ≈ rustc-direct (~574 cyc), NOT LTO parity (471). LTO +parity needs synth internal-call inlining or loom's verified inliner (loom#145, i64-blocked). + +### UPDATE 2026-05-30e — on-target test reveals a FUNDAMENTAL blocker ([synth#178](https://github.com/pulseengine/synth/issues/178)) + +Drove toward the actual silicon run. The wasm shim's `z_impl_k_sem_give` **dereferences a +pointer** (`sem->count`, the kernel-passed `struct k_sem *`). Decoding the compiled body: + +``` +movw ip,#0x100; movt ip,#0x2000 → ip = 0x20000100 (FIXED) +ldr.w r8,[ip] → reads sem->count from 0x20000100, NOT from r0 (the sem ptr) +``` + +synth's **optimizer constant-folds the dynamic load address to a fixed `0x20000100`, ignoring +the pointer parameter**. Minimal repro `(func (param i32)(result i32) local.get 0 i32.load)` +→ same. `--no-optimize` is correct (`ldr [fp, r0]`), so it's an optimizer bug → filed +**synth#178**. Secondary architectural point (also in #178): even `--no-optimize` uses `fp` as +a linmem base, so a native drop-in needs `linmem_base=0` / a native-pointer ABI. + +**Why this is fundamental:** gale's verified `decide(count, limit, has_waiter)` takes **values**, +so it compiles fine (that's the working `GALE_USE_SYNTH` path, 582 cyc, seam intact). The whole +point of the wasm-LTO shim was to move `z_impl` — which **must deref the host `k_sem` pointer** — +into wasm so the seam dissolves. But wasm's linear-memory model doesn't map a native pointer, +so a host-pointer-dereferencing function can't currently be a native drop-in. **The seam can be +dissolved only for value-only functions — but then there's no host-pointer seam to dissolve.** + +Did NOT flash: the code provably targets the wrong RAM (0x20000100), so a flash would only +confirm a known-broken result. Blocked on synth#178 (+ native-pointer ABI). Loop `e4b93e62` +continues; will retest on the next synth release. + +--- + +**Goal:** demonstrate that the PulseEngine pipeline (`wasm-ld → loom → synth`) can dissolve the C↔Rust FFI seam at wasm-IR level, producing silicon timing equivalent to LLVM-LTO. + +## TL;DR + +The toolchain inlines through the seam — synth's emitted ARM .o has `z_impl_k_sem_give` with no `bl gale_k_sem_give_decide`, the Rust decision body is folded into the C function. Two blockers prevent silicon-LTO parity: + +1. **loom Z3 backend panics on i64 sort** (`SortDiffers { left: (_ BitVec 64), right: (_ BitVec 32) }`) — the formally-verified inliner reverts every function on the gale-ffi wasm. Without loom, we lose verification + the inliner shape that matches LLVM-LTO. +2. **synth emits 1.68× larger ARM than LLVM-LTO** for the inlined body (138 vs 82 bytes), because it doesn't recognize the u64-packed FFI return pattern and falls back to generic 64-bit shift-and-mask. + +## Reproduction commands + +```sh +mkdir -p /tmp/wasm-shim-poc && cd /tmp/wasm-shim-poc + +# 1. Compile a wasm-portable host shim that mimics z_impl_k_sem_give's +# hot path with kernel APIs as externs (which become wasm imports). +# See wasm_host_shim.c in this dir. + +clang --target=wasm32-unknown-unknown -O2 -nostdlib \ + -c wasm_host_shim.c -o shim.wasm.o + +# 2. Build gale-ffi as a wasm32 static archive (already produced by +# the bench's GALE_USE_SYNTH=ON path; can also build manually): +( cd /Volumes/Home/git/pulseengine/gale-smart-data/ffi && \ + cargo rustc --release --target wasm32-unknown-unknown --crate-type=staticlib ) + +# 3. wasm-ld static-links them into a single core wasm module. +wasm-ld --no-entry --export-all --allow-undefined \ + --whole-archive /Volumes/Home/git/pulseengine/gale-smart-data/ffi/target/wasm32-unknown-unknown/release/libgale_ffi.a \ + --no-whole-archive shim.wasm.o \ + -o merged.wasm + +# 4. Synth → ARM ET_REL. Both z_impl_k_sem_give and +# gale_k_sem_give_decide end up in the .o, with the latter inlined +# into the former (no bl in z_impl's body). +synth compile merged.wasm --target cortex-m4f --all-exports --relocatable -o merged.o + +# 5. Verify the inlining empirically. +arm-zephyr-eabi-objdump -d merged.o | awk '/:/,/^$/' | grep -E '\bbl\b' # should be empty +arm-zephyr-eabi-nm --print-size merged.o | grep "z_impl_k_sem_give$" # 138 bytes +``` + +## Comparison vs LLVM-LTO (silicon-measured baseline) + +``` + body size silicon handoff (cyc) + ADC=n ADC=y + baseline (no Gale) — 528 506 + rustc-direct (FFI bl preserved) — 574 582 + LLVM-LTO (cross-language inliner) 82 bytes 471 558 ← gold + wasm→synth (Rust only, seam intact) n/a — 582 + wasm-ld merge → synth (this spike) 138 bytes not yet measured +``` + +The "not yet measured" cell needs a CMake `GALE_USE_SHIM_WASM` flag that swaps the bench's native `gale_sem.c` for the wasm-merge-derived archive. Estimated silicon impact based on the 1.68× code-size ratio: ~510 cyc handoff (ADC=n), still better than rustc-direct's 574 but worse than LTO's 471. That estimate is to-be-validated. + +## What synth produces (vs LTO, for the same inlined body) + +LTO version of the no-waiter path (from +silicon/runs/.../gale-lto-noadc-systick/firmware.elf): + +``` +8004398: ldrd r2, r1, [r0, #8] ; load count, limit +800439c: cmp r2, r1 ; the only check +800439e: it cc +80043a0: addcc r2, #1 ; saturate increment +80043a2: str r2, [r0, #8] ; write back +``` + +5 instructions. LLVM saw both C's `cmp/it/addne` and Rust's identical +check and dedup'd them into one. + +Synth version of the same path (from /tmp/wasm-shim-poc/merged.o +z_impl_k_sem_give at 0x2f5e4): + +``` +2f5ec: mov r5, r0 +2f5ee: movw ip, #256 +2f5f2: movt ip, #8192 +2f5f8: ldr.w r3, [ip] ; loads via abs address (wasm linear-mem mapping) +2f5fc..2f60e: more abs-address loads + waiter check +2f61c: and.w r0, r0, r2 ; mask u64 → u8 action +2f620: and.w r1, r1, r3 +2f624: cmp action with WAKE constant +2f63a..2f660: 64-bit lsl/lsr/orr to extract new_count from u64-packed return +2f668: bx lr +``` + +~30 instructions. Sub-optimal for two reasons: (a) wasm linear-memory +loads use absolute address pairs (`movw + movt`) instead of relative +offsets from a base register, and (b) the u64-packed decision is +unpacked via generic shifts instead of a direct field access. + +Both are fixable in synth's backend. + +## Full integration attempt + new finding — synth memset is broken + +After the initial spike I attempted full integration into the bench +to get silicon-measurable timing. The integration path: + + 1. Edit `zephyr/gale_sem.c` to wrap `z_impl_k_sem_give` in + `#ifndef GALE_WASM_LTO_OVERRIDE_SEM_GIVE` so the bench's native + compilation skips it. + 2. Build merged.wasm via wasm-ld → synth → ARM ET_REL. + 3. Wrap merged.o in libgale_ffi.a using arm-zephyr-eabi-ar (not + Apple ar — Apple ar's ranlib doesn't index ARM ELF symbols + correctly, archive shows up as "no global symbols"). + 4. Place the merged libgale_ffi.a at the bench's expected path + (replacing the rustc-direct cargo output). + 5. Build with `-DEXTRA_CFLAGS=-DGALE_WASM_LTO_OVERRIDE_SEM_GIVE=1 + -DEXTRA_LDFLAGS=-Wl,--allow-multiple-definition`. + +The build succeeded — final ELF: 219 KB FLASH (vs LTO's 26 KB), 66 KB +RAM. Linker warnings about `.meld_import_table` orphan section +(synth-emitted, lands at VMA 0 in non-loaded section, harmless). + +**But the chip doesn't boot.** PC stays in the synth-emitted `memset` +function (`0x0802c614`, 454 bytes) for >10 seconds, bouncing between +0x0802c668 and 0x0802c67e — a tight inner loop that doesn't terminate +correctly on the boundaries Zephyr's startup uses. Zephyr's z_bss_zero +calls memset(bss_start, 0, bss_size); synth's memset never returns. + +Workaround attempts that didn't stick: +- `--allow-multiple-definition` + `objcopy --weaken-symbol=memset`: + weak-vs-strong resolution didn't override; ld picked synth's. +- `objcopy --redefine-sym memset=__synth_memset`: renamed the C-symbol + but the Rust mangled `_ZN17compiler_builtins3mem6memset17h...E` + remained, and the final ELF still resolves `memset` to synth's + buggy code at 0x0802c614 (the bytes are still there from merged.o's + .text section). +- `objcopy --strip-symbol=memset`: removes the symbol table entry + but doesn't remove the bytes; ld still places synth's code at + 0x0802c614 and exposes it as `memset` from another reference. + +The root cause is that synth's wasm-to-ARM lowering of memset +produces a loop that doesn't terminate on the boundaries Zephyr's +startup uses (`memset(bss, 0, bss_size)` where bss_size is in bytes, +8-byte aligned). The synth output disassembles to a pattern with +`subs.w r3, r2, #32; bpl.n ...; rsb r3, r2, #32; lsl.w r3, r1, r3 …` +which is the i64-shift-with-bytecount pattern from Rust's u64 +left-shift implementation — synth seems to have lowered memset's +inner loop using i64 shift operations that don't apply to byte +counts. + +## Action items, filed upstream + +| # | upstream issue | severity | summary | +|---|---|---|---| +| 1 | [pulseengine/synth#93](https://github.com/pulseengine/synth/issues/93) | **blocker** | memset/memcpy/memmove i64-codegen non-termination — chip hangs in memset+0x4c on `z_bss_zero` | +| 2 | [pulseengine/synth#94](https://github.com/pulseengine/synth/issues/94) | enhancement | u64-packed FFI return unpacking — register-direct field access vs generic 64-bit shifts (~50% of LTO size gap) | +| 3 | [pulseengine/synth#95](https://github.com/pulseengine/synth/issues/95) | enhancement | wasm linear-memory access lowering — base+offset vs movw+movt+ldr (~20% of LTO size gap) | +| 4 | [pulseengine/loom#98](https://github.com/pulseengine/loom/issues/98) | bug | Z3 SortDiffers panic in inline_functions on i64 — every gale-ffi function reverts, inliner is no-op | + +### Status detail per issue + +**synth#93 (blocker).** The wasm→ARM lowering of compiler_builtins' memset +produces a non-terminating loop on Zephyr's startup +`memset(bss, 0, sizeof(bss))` invocation. The chip hangs at +memset+0x4c forever. Until this is fixed, no integration of +merged-wasm into a real bench can boot. + +**synth#94.** When synth lowers a wasm function that returns i64 and the +caller immediately bit-masks into byte-fields, it currently emits +generic 64-bit shift extraction. Recognizing the packed-struct-return +pattern would close ~50% of the LTO-parity size gap. + +**synth#95.** wasm `i32.load` from a constant address currently emits +`movw + movt + ldr` (10 bytes). Conventional ARM ABI uses base+offset +addressing (2-4 bytes per load). + +**loom#98.** Z3 backend's i64 sort handling chokes on `BitVec 64` vs +`BitVec 32` comparisons. Every function in gale-ffi reverts in the +inline_functions pass, so loom is effectively a no-op for i64-heavy +modules. + +With (1) fixed, the wasm-LTO bench will boot and we get measurable +silicon cycles. With (2)+(3) on top, the wasm-LTO route should +approach LLVM-LTO parity (within ~10% on silicon cycles) while +delivering the verification-by-construction property LLVM-LTO doesn't +have. + +## What we have data-to-compare on + + Silicon (sha b48a81ac/f6f61281): + baseline (no Gale, ADC=n) 528 cyc handoff median + rustc-direct gale (ADC=n) 574 cyc (+46 = FFI seam) + gale via wasm→synth (Rust only, ADC=y) 582 cyc (seam preserved) + LLVM-LTO gale (ADC=n) 471 cyc (-57 below baseline) + LLVM-LTO gale (ADC=y, post-fix) 558 cyc (+52 above baseline) + wasm-LTO via wasm-ld+synth (ADC=y) ELF builds, chip won't boot + + Toolchain-level: + wasm-ld merge + arm-zephyr-eabi-ar works + synth inlining via merged-module works (no bl in z_impl_k_sem_give) + synth emitted body size 138 bytes (1.68x LTO's 82 bytes) + synth memset codegen broken (infinite loop) + loom inline_functions broken (Z3 SortDiffers on i64) + +The **structural claim** holds: the wasm-LTO toolchain (meld/wasm-ld → loom +→ synth) inlines through the C↔Rust seam. The disassembly evidence is +robust — synth's emitted ARM has zero `bl gale_k_sem_give_decide` in +the inlined `z_impl_k_sem_give`. + +The **silicon-cycle claim** requires fixes upstream: the memset bug +blocks boot, and the i64 codegen patterns prevent LTO parity once we +get there. Two PRs against pulseengine/synth and one against +pulseengine/loom. + +## Why this matters for the publication + +The current "Three Quiet Barriers" successor can claim: + +> "Cross-language LTO via wasm IR is feasible end-to-end with the +> existing PulseEngine pipeline. wasm-ld merges, synth transpiles, +> and the C↔Rust seam dissolves at wasm level. The remaining gap to +> LLVM-LTO parity is two specific codegen patterns in synth and a +> Z3 sort fix in loom — both well-scoped engineering work, neither +> a fundamental architectural barrier." + +That's a stronger claim than "wasm + synth = same as rustc-direct" +(which is what the current `GALE_USE_SYNTH=ON` path delivers without +the merge step). + +### RESULT 2026-05-31 — ON-TARGET MEASUREMENT CAPTURED ✅ + +The wasm-cross-LTO route now runs correctly on the physical NUCLEO-G474RE. +Full sweep completes (150 samples, 5 RPM steps, drops=0, `=== END ===`). + + **wasm-cross-LTO handoff (silicon, gale variant, synth v0.11.14 / loom v1.1.5): + median 907 cyc** (steady-state; min 904, max 1607 cold; n=148). algo_cyc=259. + +Reference points (handoff cyc): baseline ~528, rustc-direct ~574, LLVM-LTO ~471, +wasm→synth seam-intact (GALE_USE_SYNTH) ~582. So the seam-DISSOLVED wasm-cross-LTO +at **907 cyc is ~1.6× native** — SLOWER despite the seam being structurally dissolved +(decide inlined, no `bl gale_k_sem_give_decide`). The gap is NOT architectural; it is +(a) synth ARM codegen quality (spill/reload, i64 handling, no peephole vs gcc/LLVM) and +(b) integration overhead unique to this build: the fp=0 trampoline + the out-of-line +kernel-API wrappers (gale_wasm_wrappers.c) that turn Zephyr's `static inline` k_spin_lock / +arch_thread_return_value_set into real CALLs (native/LTO inline them). A production +integration would shrink (b); synth codegen maturity would shrink (a). + +Run artifact: silicon/runs/2026-05-31-nucleo_g474re-wasm-cross-lto-e8488f0c/. +Took synth #167/168/171/173/174/178/188/195/197/202/204 + loom #145/147/151/153 to get here. + +## UPDATE 2026-06-03 — RISC-V / MULTI-TARGET thread opened (native-first; synth Opt3 stays interrupt-priority) + +Goal: bring wasm-cross-LTO to RISC-V (ESP32-C3 / Renode / qemu_riscv32), staged like ARM — NATIVE baseline +first, then the synth wasm-cross-LTO path. Lower priority than the synth Opt3 watch (interrupt for that). + +### The KEY design question — pieces that STAY THE SAME vs DIFFER across targets +The pipeline splits into a target-independent **front half** (write + verify ONCE) and a target-specific +**back half** (a small per-arch adapter): + +**SHARED (identical for ARM & RISC-V):** +- C source of the algorithm/primitive + the value-in/value-out shims. +- The compiled **wasm modules** (clang→wasm32) — pure, architecture-free. +- **loom seam-dissolution** — operates on wasm, emits dissolved wasm; same artifact feeds any backend. Fully target-agnostic. +- **wasmtime functional oracle** + verified vectors (`run_testbed.sh` Layer 1) — wasm semantics, target-independent. + +**DIFFERS per target (factor into `arch/{arm,riscv}/` adapters):** +- **synth backend**: `-b arm` (Thumb-2, per-rule SMT / ASIL-D) vs `-b riscv` (RV32, binary-verify / ASIL-B). +- **ABI / trampoline**: ARM AAPCS (args r0–r3, `r11`=linear-memory base for `[fp+off]`) vs RISC-V (args a0–a7, + its own linmem-base reg) — the fp/linmem trampoline + table-data placement is per-arch. +- **relocations**: `R_ARM_THM_CALL` vs `R_RISCV_CALL`/`HI20`/`LO12`. +- **runtime + linker**: Cortex-M vector table (Zephyr) vs `synth riscv-runtime` (startup.c + linker.ld, RAM@0x80000000). +- **cycle harness**: Cortex-M **DWT CYCCNT** vs RISC-V **`mcycle`/`rdcycle` CSR**; board G474RE vs esp32c3/qemu_riscv32. +- testbed: Layer 1 (wasm oracle) shared; Layer 2 (unicorn) + Layer 3 (silicon micro-bench) get per-arch variants. + +### Status (2026-06-03) +- synth **has** a `riscv` backend (`-b riscv`, available, ELF + binary-verify) + `riscv-runtime` (rv32imac). BUT the + CLI `-t` target profiles are ARM-only, so `-b riscv` errors "cannot compile for ArmCortexM" — wasm→RISC-V codegen + exists, RV32 target-profile CLI wiring is a **gap to file** when we expand to the synth part. +- **Native RISC-V confirmed**: riscv64-zephyr-elf-gcc compiles `filter_axis` for rv32imac (`mul`/`div` emitted, HW M-ext). + `synth riscv-runtime -t rv32imac` gives startup.c + linker.ld (the runtime adapter). qemu-system-riscv32/64 present. +- Prediction to test: RV32IM has a hardware divider (like M4 `udiv`), so reciprocal-multiply should be near-neutral + on RISC-V too — a cross-target confirmation of the M4 Opt 1b finding. + +### NEXT (RISC-V, native-first) +1. Minimal qemu_riscv32 (or esp32c3) harness using `riscv-runtime` startup/linker: read `mcycle` CSR around + `filter_axis_native`, emit result (UART/semihosting). → native RISC-V baseline. +2. Then `synth -b riscv` → file the RV32 target-CLI gap; once it compiles, run + measure → RISC-V wasm-cross-LTO. +3. ARM-vs-RISC-V comparison table. Interrupt for synth Opt3 throughout. + +### RISC-V update 2026-06-03 — NATIVE baseline DONE; synth-rv32 blocked on #218 +`filter_axis` runs CORRECT on RV32 end-to-end (riscv-gcc rv32imac_zicsr + `synth riscv-runtime` startup/linker ++ qemu-system-riscv32 `virt` `-icount` + NS16550 UART @0x10000000): selfcheck 1088 / -1917, measured **14** +(qemu `-icount` = instruction-count proxy, NOT silicon cycles — relative only; real RV cycles later from +ESP32-C3/Renode). Harness `/tmp/rv-bench/` is reusable for the synth path (swap the native obj for +`synth -b riscv` output). Design fact: **RISC-V linear-memory base = `s11`** (the RV analogue of ARM `r11`). +Filed **synth#218** (riscv backend unreachable from CLI — no RV32 `-t`); synth-rv32 wasm-cross-LTO is gated +on it. Run: `runs-riscv/2026-06-03-qemu_riscv32-filter_axis-NATIVE-baseline/`. + +### RISC-V update 2026-06-03 (later) — synth-rv32 wasm-cross-LTO PROVEN FUNCTIONAL (v0.11.21); #220 filed +synth v0.11.21 published (#218 riscv-CLI fix). ARM regression ALL GREEN (riscv fix didn't touch ARM). +**Expanded to the synth part:** `synth compile filter.loom.wasm -b riscv -t rv32imac` → RV32 ELF (88 B, +EM_RISCV), runs **CORRECT on qemu_riscv32** (selfcheck 1088 / -1917) — the wasm→loom→`synth -b riscv`→RV32 +path works end-to-end. Hit + filed **synth#220**: the riscv backend uses callee-saved **s1–s6** as scratch +with **no prologue/epilogue** (RISC-V psABI violation → corrupts caller → hang). Disasm-confirmed; worked +around with an s-register-preserving trampoline → correct, ~50 icount (incl ~24 tramp; core ~26 vs native +rv32 17). synth's arithmetic/division riscv codegen is correct; only ABI reg-preservation is broken. +Clean synth-rv32 number pending the #220 fix (drop the trampoline). Run: runs-riscv/2026-06-03-qemu_riscv32- +filter_axis-SYNTH-v0.11.21/. Issues: #218 (fixed), #220 (open). Real RV silicon (ESP32-C3/Renode) still user-gated. + +### RISC-V update 2026-06-03 (later2) — riscv backend is a skeleton: filed #223 (missing Select/LocalTee) +Pushed control_step/controller_step/flat_flight through `synth -b riscv`: all rejected — `control_step`/ +`controller_step` → "unsupported wasm op for RV32 skeleton: **Select**" (the clamps/saturation); `flat_flight` +→ "**LocalTee**". So the RV32 backend handles straight-line value-in (filter_axis ✓) but is missing common +ops. Filed **synth#223** (Select + LocalTee, with lowering hints). Two open riscv issues now: **#220** (clobbers +callee-saved s1–s6, ABI) + **#223** (op coverage). As they land, the same dissolved wasm compiles to RV32 and +we get the ARM-vs-RISC-V table. filter_axis synth-rv32 stands (correct, ~26 core icount vs native 17, modulo #220). + +### RISC-V update 2026-06-03 (later3) — clean filter_axis synth-rv32 (v0.11.22); cross-target ~2× confirmed +synth v0.11.22 (#220 callee-saved ABI fix) PUBLISHED. ARM regression ALL GREEN. **Clean filter_axis synth-rv32 +(trampoline-free): 37 icount vs native rv32 17 = 2.18×**, correct. The fix added the s-reg save/restore +prologue; the gap is that synth spills into callee-saved **s1–s6** (needs save/restore) where native gcc keeps +this leaf in caller-saved t-regs — the **RISC-V analogue of ARM Opt 3** (reported on #220). Cross-target: +RV32 **2.18×** ≈ ARM **2.42×** → the ~2× wasm-cross-LTO-vs-native gap is **general codegen, not arch-specific**. +#223 (Select + non-param locals + extend16_s) FIXED → **v0.11.23** (PR open, not yet published); maintainer's +unicorn diff shows control_step rv32 correct (0x00210a55). NEXT: v0.11.23 → control_step/controller_step/ +flat_flight synth-rv32 → full ARM-vs-RISC-V table. Real RV silicon (ESP32-C3/Renode) still user-gated. + +### RISC-V update 2026-06-03 (later4) — v0.11.23: all 3 compile; controller miscompiles -> filed #226 +synth v0.11.23 (#223 Select+non-param-locals+extend16_s) PUBLISHED; ARM ALL GREEN; control_step/controller_step/ +flat_flight all now COMPILE on -b riscv. **controller_step synth-rv32 MISCOMPILES** (0x00ce0001 vs 0x05ce7f9c; +native correct in same harness). Disasm root-cause: **regalloc live-range bug** — `t2 = updates<<24` (0x24) is +clobbered by a reused `slt t2,...` (0x5c) for the aileron clamp, then the final pack `or s5,t2,s4` (0x9c) reads +the stale t2 → updates byte lost. Filed **synth#226** (RV32 temp allocator not honoring live ranges; ARM-regalloc +analogue, now a correctness bug). filter_axis rv32 stands (2.18×). control_step/flat_flight compile; their RUN needs +the s11 linmem/table (control_step) + s11=0 pointer (flat_flight) setup — next firing (control_step maintainer- +validated via their unicorn diff = 0x00210a55). RISC-V issues: #218/#220/#223 fixed, #226 open. + +### RISC-V update 2026-06-03 (later5) — control_step rv32 CORRECT + measured; cross-target ~2× confirmed on 2 fns +control_step rv32 (v0.11.23) verified on qemu via the **s11 table-trampoline** (s11=&gale_tables-0x10000; synth +reads tables at [s11+0x10000]; #220-fix excludes s11 so synth preserves it): **CORRECT (2165333)**, synth 141 / +native 62 = **2.27×** (incl ~6-cyc tramp). Confirms the maintainer's control_step_riscv_differential on real qemu. +**Cross-target table** (ARM real-cyc | RISC-V icount): filter_axis 2.42× | 2.18×; control_step 2.07× | 2.27× — +both ~2.1–2.4× per ISA, gap = regalloc/spill (synth uses callee-saved s-regs; native uses t-regs) = **#209 Opt 3, +arch-INDEPENDENT** (posted to #209). controller_step blocked on #226→v0.11.25 (pending). flat_flight compiles; run +needs s11=0 pointer setup (next). RISC-V issues: #218/#220/#223 fixed, #226 fixed→v0.11.25 pending. + +### RISC-V update 2026-06-03 (later6) — flat_flight rv32 hangs (likely #226); Opt3 = top perf item +#209: maintainer confirmed the cross-target evidence + **Opt 3 (regalloc + constant-CSE) is now the top perf item** +(retargetable, lands after the v0.11.24/.25 correctness train). #226→v0.11.25 is CI-gated (rivet 0.15.0 status-enum +/ PR#229). Built the **s11=0 pointer trampoline** for flat_flight rv32 (native deref via [s11+ptr], s11=0), but +flat_flight **hangs in the call** (markers: MAIN-OK-before prints, RETURNED doesn't; boot/harness fine — control_step +works in the same harness). flat_flight contains the #226 controller-pack (updates<<24 across selects) → **likely +#226-gated** (corrupted reg used as ptr/counter → hang). Not filed (probable #226 dup); will re-verify on v0.11.25 +and isolate (s11=0 path vs new bug) if it still fails. RISC-V working: filter_axis 2.18× + control_step 2.27×. + +### RISC-V update 2026-06-03 (later7) — synth-rv32 path durable in repo (arch/riscv/run_synth.sh) +No new release (v0.11.25 #226-fix CI-gated PR#229; Opt3 perf-release-gated). Consolidated the synth-rv32 harness +into the repo: **arch/riscv/run_synth.sh** regenerates control_step from the shared sources (clang→wasm-ld→loom), +compiles with `synth -b riscv -t rv32imac`, links the s11 table trampoline, runs on qemu → **2165333 correct, +141/62=2.27×**. Now both arch/riscv adapters are durable + reproducible: run_native.sh (baseline) + run_synth.sh +(wasm-cross-LTO). Ready to add controller/flat_flight when v0.11.25 lands. RISC-V working: filter_axis 2.18× + +control_step 2.27×; controller/flat_flight gated on #226/v0.11.25. + +### RISC-V update 2026-06-03 (later8) — FULL RISC-V TABLE COMPLETE (v0.11.25, #226 fixed) +synth v0.11.25 (#226 live-range fix) PUBLISHED; ARM ALL GREEN. **All 4 functions correct on qemu_riscv32:** +controller_step now correct (0x05ce7f9c, 114/49=**2.33×**); flat_flight now RETURNS correct (0x07fdf307, +193/75=**2.57×**) — was #226-gated (the defer-filing call was right). **Cross-target table (ARM real-cyc | RISC-V icount):** +filter_axis 2.42×|2.18×; control_step 2.07×|2.27×; controller_step —|2.33×; flat_flight 3.18×|2.57×. Same ~2–2.6× +gap both ISAs, widening with complexity; lever = regalloc/spill = **#209 Opt 3 (universal, retargetable)**. Posted +to #209. RISC-V backend issues #218/#220/#223/#226 ALL FIXED — the same dissolved wasm runs correct on RV32 across +the whole set. (RV32 = icount proxy; real silicon via ESP32-C3/Renode follow-up.) NEXT: Opt 3 perf release. + +## UPDATE 2026-06-03 — v0.11.27 composed-path codegen breakdown (Opt3 increment #2 targets) + +After v0.11.27 (#231 leaf-alloc + #232 div fix), the leaves are optimal (filter/controller: 0 frame, 0 spills; +filter 2.18x->1.35x). The composed `flat_flight` barely moved (2.57x->2.41x). Disassembled its RV32 output +(186 instr, 756 B) to localize the remaining overhead — three measured inefficiencies, leverage order: + +1. **const-CSE (biggest):** 37 const materializations (li/lui, ~20% of body), only 16 distinct -> 21 redundant (57%). + Systematic per-axis dup: ±127 saturation each 4x, filter coeffs 980/20/1000 each 2x, shifts 6/7 2-3x, INT_MIN/-1 guards 2x. +2. **pressure-aware spilling:** flat_flight exhausts 7 caller-saved t-regs -> spills to 32B stack frame (7 sw + 10 lw = 17 instr, 9%); + control_step likewise (6 spills, 16B). Caller-saved preference is right for leaves; for pressure functions a callee-saved + s-reg (1 save+restore, amortized) beats N stack reloads. RV32 analogue of the ARM "reclaim r9/r10" item. +3. **copy-coalescing:** 38 mv (20%) in flat_flight, 32 in control_step — value-stack lowering emits a mv per transfer. + +Posted to synth #209 (comment 4612930170) as the concrete recommendation for the next Opt3 increment. +The leaf gap is closed; the composed gap = const-CSE + pressure-aware s-reg spill + mv-coalescing. + +## UPDATE 2026-06-03 — flight_control wasm-LTO variant: on-silicon functional validation + +Flashed both flight_control variants on the real NUCLEO-G474RE (openocd, VCP autodetect): +- **NATIVE** and **GALE_FC_WASM_LTO=ON** both boot and produce a valid, identically-structured + event stream (E,,,,,,,...). The dissolved flight + algorithm (filter_step + controller_step via the r11=0 trampoline) **runs correctly on the + actual chip**, not just unicorn/qemu. This is the real-silicon functional checkmark for the + Phase-5 wasm variant. + +Caveat on measuring the algo cost *from the bench*: the bench's `algo` column times only an +ISR placeholder (`squelch = |gyro_x+gyro_y+gyro_z|`), NOT filter_step/controller_step (those run +in the fusion thread + controller, untimed). So `algo` is identical (≈141 cyc) native vs wasm — +it isn't measuring the dissolved code. Ad-hoc timing around the real calls is dominated by the +non-inlined `k_cycle_get_32` overhead (~65–145 cyc) and is too noisy for a clean delta without +the microbench's min-over-200 + overhead-subtraction discipline. + +**Authority for the flight-algo silicon cycle delta remains the dedicated microbench**: +`flat_flight` (= filter+controller composed) = 315 cyc wasm-cross-LTO vs 99 native = 3.18× +(loom v1.1.10, full dissolution). The bench variant is for *running* the dissolved algorithm in +the full 5-primitive context; the microbench is for the clean cycle number. +Follow-up (optional): add overhead-subtracted min-over-N timing around the bench's real +filter_step/controller_step calls if an in-context number is wanted. + +## UPDATE 2026-06-04 — MUTEX dissolves via wasm-cross-LTO (2nd primitive after sem) + +Proved the mutex primitive dissolves through the same pipeline as the sem (907 cyc): +`clang wasm_mutex_shim_poc.c` (wasm-portable z_impl_k_mutex_unlock) → `wasm-ld` merge with +`libgale_ffi.a` (built `cargo rustc --target wasm32-unknown-unknown --crate-type=staticlib`, +relocatable objects) → `loom optimize --passes inline` → `synth compile --target cortex-m4f`. + +**Seam dissolved** (the success criterion): `merged.o` defines only `z_impl_k_mutex_unlock` +(530 B ARM) + a synth helper — **no `gale_k_mutex_unlock_decide` symbol** (the verified-Rust +decision is inlined/folded into the C function, exactly like LLVM-LTO and the sem result). +Call relocations from the dissolved function are only the kernel APIs: +`k_spin_lock/unlock`, `gale_w_current`, `z_unpend_first_thread`, `z_ready_thread`, +`arch_thread_return_value_set`, `z_reschedule` — i.e. it reuses **every** sem `gale_w_*` +wrapper + the one new `gale_w_current`. No `bl gale_k_mutex_unlock_decide`. + +Remaining for the silicon number: objcopy-rename the kernel imports to `gale_w_*` (as the sem +does), wire `GALE_WASM_LTO_MUTEX_LIB` to override the bench's native `z_impl_k_mutex_unlock`, +flash G474RE, and measure k_mutex_unlock native / LLVM-LTO / wasm-cross-LTO — the 2nd primitive +data point alongside the sem's 907. + +## UPDATE 2026-06-04 (cont) — mutex integration wired; blocked on synth#235 (ET_REL helper) + +Built libwasmmutex.a (merged.o = dissolved z_impl_k_mutex_unlock, kernel imports objcopy-renamed +to gale_w_*) + wired the integration (gale_mutex.c #ifndef GALE_WASM_LTO_OVERRIDE_MUTEX_UNLOCK guard; +GALE_WASM_LTO_MUTEX_LIB CMake block, mirroring the sem). Reuses all sem gale_w_* wrappers + gale_w_current. + +Link blocker (filed synth#235): the dissolved unlock calls a non-inlinable helper — +core::panicking::panic_fmt (the lock_count overflow-checks=true panic path; gale Cargo.toml forces +overflow-checks=true). synth emits the export (ET_REL) referencing it as undefined `func_9`, but +--func-index (only way to compile a non-export) emits ET_EXEC (with startup stubs), which ld rejects +("cannot use executable file as input"). So no linkable object set until synth can emit reachable +internal callees as ET_REL. NOT disabling overflow-checks (would diverge from the faithful production +build). Workaround options for next firing: export the helper via wasm-tools so --all-exports emits it +ET_REL, or provide a panic_fmt stub. Once linkable -> flash G474RE -> k_mutex_unlock 2nd primitive number. + +## UPDATE 2026-06-04 (cont) — MUTEX UNBLOCKED by synth v0.11.28, links + runs on G474RE + +synth#235 fixed in v0.11.28 (#236, my option 1: --all-exports --relocatable emits reachable internal +callees). Built #236 from source; re-ran the mutex dissolution: merged.o now defines z_impl_k_mutex_unlock ++ func_8/9/10 (the inlined decision + panic_const_add_overflow->panic_fmt chain), only the 7 kernel-API +imports undefined (all -> gale_w_* wrappers). objcopy-renamed imports -> gale_w_*, ar -> libwasmmutex.a, +linked into flight_control via GALE_WASM_LTO_MUTEX_LIB: LINKS CLEAN. Flashed nucleo_g474re: boots + runs the +100Hz loop to the results print with the dissolved mutex live = wasm-cross-LTO k_mutex_unlock works on silicon. +NEXT: clean k_mutex_unlock cycle microbench (DWT min-over-N, native vs wasm-cross-LTO) for the head-to-head +number, the 2nd primitive data point alongside sem 907. (v0.11.28 still a PR; canonical once released.) + +## UPDATE 2026-06-04 (cont) — mutex LINKS (v0.11.28) but drop-in FAULTS on silicon (synth#237) + +Installed v0.11.28 (released; #235 fix). The mutex now links + the bench boots, BUT the dissolved +z_impl_k_mutex_unlock MPU-FAULTS at runtime on the G474RE (str.w r6,[r11,r12], r12≈0x08003101 = a +flash/.rodata addr → Data Access Violation, before any output). Root cause = base-register conflict: +the body mixes (a) the host k_mutex* arg [needs linmem_base=0 for native deref] and (b) a function-static +(the shim's `static k_spinlock lock`) [needs base=&wasm_data]. base can't be both. fp=0 trampoline + +overflow-checks=off (drop panic) both insufficient — the static-data access still faults. Filed synth#237 +(native-pointer vs wasm-static base conflict; asks for base-independent .data/.rodata reloc for statics). + +This is the SAME wall the sem drop-in hit historically (NOTES above: "host-pointer-dereferencing function +can't be a native drop-in"). HONEST scope: value-in/value-out dissolutions (filter_axis, control_step, +flat_flight) work + measured on silicon; host-pointer PRIMITIVE drop-ins (sem z_impl, mutex z_impl) are +ABI-blocked. The mutex k_mutex_unlock silicon NUMBER is gated on synth#237. Native gale k_mutex_unlock +(reference) measured = 124 cyc (uncontended, DWT min/200). v0.11.28 gives the LINK; #237 is the runtime ABI. + +## UPDATE 2026-06-04 — mutex root cause = linmem STACK (not BSS static); design-Q answered (#237) +Maintainer fetched mutex_m.loom.wasm@f027273: no (data) segs, no const-addr statics. Real cause = +the wasm linmem **stack**: `(global $__stack_pointer (mut i32) i32.const 65536)` → 16B frame → +SP-relative i32.store; synth lowers `[$sp+K]`→`[r11+sp+K]`; r11=0 trampoline → abs 0x1000~ → DAV. +Measured `$__stack_pointer`/linmem-store usage across shipped leaves (answers maintainer Q-b): + filter_axis 0/0, controller_step 0/0 (register-only); control_step 1/**0** (tables via fp=&tables, no stack writes); + flat_flight 1/**6** (DID spill — ran via fp=RAM-linmem-base harness, NOT a native fp=0 drop-in). +Q-a: $__stack_pointer baked from const 65536 in-function; no external/runtime globals-init (just my tramp). +Fix (maintainer's court): under --native-pointer-abi, materialize `__synth_wasm_data+65536` (MOVW/MOVT) for +the SP base (+ any global init'd to a linmem addr); host-ptr [0+ptr+off] stays native. Self-contained. +→ #237 c4623207735. remeasure_wasm_lto.sh staged; reflash+post k_mutex_unlock cyc (native 124) when build lands. + +## UPDATE 2026-06-04 (b) — ABI design call: FULLY SELF-CONTAINED (#237 c4623417761) +Maintainer decoded synth output: 2 faults — (1) `ldr [r9,#0]` reads $__stack_pointer from an R9 globals +table my tramp never sets (garbage SP); (2) baked movw/movt #0x10000 stack-top literals. Asked: keep R9 +table (tramp sets r9=__synth_wasm_data) vs self-contained (no R9, globals inlined as __synth_wasm_data-rel consts). +RECOMMENDED self-contained: an R9-base contract defeats drop-in (ISR/ctx-switch/scheduler must preserve a +2nd synth base reg); reuses v0.11.29 .bss+MOVW/MOVT substrate exactly; collapses both faults to one rule +(every linmem addr = __synth_wasm_data+N, every host-ptr arg = [0+ptr]); negligible size cost; generalizes +to any dissolved fn. Tramp stays trivial (mov r11,#0). Maintainer to implement as one coherent pass. + +## UPDATE 2026-06-04 (c) — maintainer accepted self-contained, BUILDING; oracle validated (#237 c4623714140) +Decoded m.loom.wasm to confirm the SP-anchor pass is necessary+sufficient: +- frame is LIVE: local 1 = SP-16 dereferenced via i32.load offset=4/8/12 (lines 51/58/64) -> SP base MUST be real RAM. +- 6x i32.const 65536: 1 = SP global init (relocate); 5 = &lock arg to k_spin_lock/unlock (lines 28/54/66/93/104), + wrapper-ignored, correctly left bare by the SP-anchor rule. +- SIZING CAVEAT given: frame at TOP of linmem [65520,65536); .bss must reserve full 2 pages = 131072 B, not data high-water. +Pass = register-promote $__stack_pointer + init __synth_wasm_data+65536 + .bss=full pages; leave frame-size + &lock consts. +Deliverable clock running (policy: dialogue doesn't reset it); reflash G474RE within min of a build. native ref 124. + +## UPDATE 2026-06-04 (d) — v0.11.29 RELEASED (data-statics half only); mutex unchanged (#237 c4623947806) +v0.11.29 (commit 2305948, #238 merge) = --native-pointer-abi DATA-statics work. Tested: +- value leaf control_step: clean .text-only ET_REL, NO regression. +- mutex .o (v0.11.29 --native-pointer-abi) = BYTE-IDENTICAL (cmp) to mutex_v0.11.29_bss_still_faults.o: + still 12x R_ARM_THM_CALL, no .bss/.data/__synth_wasm_data. diff v0.11.28..v0.11.29 = 0 stack_pointer changes. + -> identical object = identical fault; did NOT reflash (byte-diff suffices per loop rule). +SP register-promotion pass (the deliverable) NOT in v0.11.29. Asked maintainer: landing in v0.11.30? +Deliverable clock kept running (policy: a release that doesn't address the deliverable doesn't reset it). + +## UPDATE 2026-06-04 (e) — PR#240 (synth 0.11.30) TESTED on G474RE: object-correct, but 2 blockers (#237 c4624307408) +Built PR#240 (91c7ec1). Object matches oracle: 6 MOVW/6 MOVT __synth_wasm_data, .bss NOBITS, 0 R9; control_step bit-identical. +BLOCKER 1: .bss = 0x20000 (128KB, full 2-page declared mem) = 100% of 128KB RAM -> link overflow 6408B. Real footprint + is page-1-only (no data segs, 16B frame). Patched .bss sh_size 0x20000->0x10000 (NOBITS, code unchanged) -> RAM 54.89%, links. + FIX: size __synth_wasm_data to high-water addressed offset, NOT min_pages x 65536. (my earlier min_pages caveat was wrong.) +BLOCKER 2 (real): BUS FAULT even with SP base relocated (__synth_wasm_data=0x20000080) + 64KB .bss. Dissolved obj = 4 fns: + func_7=body (SP-promoted, all 6 MOVW/MOVT here) + func_8/9/10 internal callees (loom didn't inline). Fault in func_9 at + 0x4dc `f84b 600c` = STR.W r6,[r11,r12] -> wasm-linmem store with base r11=0 (trampoline). Callees still use [r11+linmem]. + FIX: extend __synth_wasm_data materialization to ALL emitted fns (callees too), so r11 never a linmem base; r11=0 = host ptrs only. +Repro committed: mutex_v0.11.30_pr240_full.o, _bss64k.o, _busfault.txt. native ref 124. Reflash on a callee-promoted build. + +## UPDATE 2026-06-04 (f) — EXPAND: controller_step ARM silicon = 169/61 = 2.77x (filled the "—" cell) +While mutex/#237 is in maintainer hands (PR#240 callee-promotion fix), pushed the expand thread: +measured controller_step (7-arg value fn) on G474RE. SELFCHECK 0x05e33e81 == native (functionally correct). +KEY ABI FINDING: synth's cortex-m convention passes args in r0-r7 (capstone: arg1=r0, arg2=r1, ..., +arg7 read from saved-r6 slot after `push {r4-r8,lr}`), NOT AAPCS (r0-r3 + stack). So control_step (4 args) +was AAPCS-clean, but >4-arg fns need an arg-shuffle trampoline (controller-microbench/ctl_tramp.S: +push{r3-r7,lr}; ldr r4/r5/r6 from [sp+24/28/32]; blx synth body). 169 includes ~8-cyc marshalling; +body alone ~161. Candidate maintainer ask (HOLD until #237 settles, don't pile): does synth's >4-arg +cortex-m convention intend r0-r7? It means every >4-arg drop-in carries a trampoline + shuffle cost. +Landed reusable controller-microbench/ (build.sh, ctl_tramp.S, RESULT-2026-06-04-g474re.txt). + +## UPDATE 2026-06-04 (g) — v0.11.30 MERGED (leaf core); #237 REOPENED; oracle NOT covered on HW (#237 c4624659657) +PR#240 merged (22d2df8). Maintainer: leaf+balanced-SP core done; gmutex "covered" (12 relocs/0 R9). REBUTTED w/ HW: +- built v0.11.30 from merged main -> mutex .o BYTE-IDENTICAL (cmp) to the object that BUS-FAULTed last firing. +- raw-byte scan: 13x STR.W/LDR.W [r11,...] wide mem-ops (e.g. f84b 600c = STR.W r6,[r11,r12]) in callees + func_8/9/10 (loom didn't inline). All 12 __synth_wasm_data relocs are in the leaf body func_7 only. +- static "12 relocs/0 R9" check MISSES this: [r11+reg] accesses are NOT relocations (readelf -r shows nothing). +-> GI-NPA-003 (callee/non-leaf linmem promotion) is REQUIRED for the named gmutex oracle to RUN, not a generalization. +Tag for v0.11.30 held pending on-target diff (GI-NPA-VER-003). Reflash on a callee-promoted build; native ref 124. + +## UPDATE 2026-06-04 (h) — EXPAND/OPT: refreshed #209 const-CSE data, linked to allocator track (#209 c4624854458) +Mutex/#237 in maintainer hands (no reply to my HW rebuttal yet; PR#243 liveness foundation VCR-RA-001 opened). +Pushed the #209 lever: re-derived flat_flight codegen on loom 1.1.10 + synth 0.11.29 (measure, don't guess): + 588B/180 instr; const mat 34 loads/13 distinct = 61% redundant (clamps #0x7e/#0x7f x6 each, #0 x4, shifts 7/6 x3); + stack spills 7 str + 10 ldr = 17. (was 37/16/57% — refreshed.) Posted to #209 w/ 2 recs on the allocator track: + (1) const-CSE hoist clamp/shift consts (~12% fewer instr, compounds w/ composition); + (2) liveness-based spill regalloc (VCR-RA-001/#243) for the 17 [sp] spills. Same lever on RV (2.41x) = retargetable. + Offered flat_flight as the silicon regression target; reflash on each allocator-track build. + +## UPDATE 2026-06-04 (i) — PR#243 liveness MERGED (pure-analysis, byte-identical); #209 plan set +PR#243 (def/use+liveness primitive, VCR-RA-001 step1) merged to main (026d58b). Regression-tested vs v0.11.29: +flat_flight + controller_step + control_step ALL byte-IDENTICAL -> pure analysis, no codegen change, no regression. +Maintainer (#209): adopted flat_flight as Track-A frozen silicon regression target (README North Star, PR#244); +plan = CFG-aware liveness -> interference graph over virtual regs -> spill-under-pressure (replaces exhaustion +hard-fail); const-CSE enabled by same primitive (local_dead_defs = dead-store dual). Baseline LOCKED: +315cyc/588B/180instr/34const(13 distinct)/17spills. Posted handshake (#209 c ). Reflash+post delta on +each allocator-track build. Both threads healthy in maintainer hands: GI-NPA-003 (mutex callees) + VCR-RA-001 (#209). + +## UPDATE 2026-06-04 (j) — #245 const-CSE detection merged (byte-identical); built flat_flight ARM harness; CORRECTED baseline +PR#245 (const-CSE detection redundant_const_defs + dead-store dual, VCR-RA-001) merged. Byte-diff vs v0.11.29: +flat_flight + controller_step IDENTICAL -> pure-analysis (PR says so), codegen-application pending = silicon-delta deliverable. +EXPAND: built flat_flight ARM-silicon microbench (flat_flight-microbench/, buffer-harness fp=&wasm_linmem, 0 statics, +64KB linmem). Measured CURRENT: synth=262/native=103 = 2.54x (SELFCHECK 0x07fdf307 OK). +=> table's 315/99/3.18x was STALE (synth v0.11.18). Corrected RESULTS-SUMMARY + #209 (c4625286555) to 262/2.54x. +262 includes ~8-cyc fp-setup tramp; body ~254. const-redundancy 34/13/61% + 17 spills on this current object (unchanged by #245). +Measurement-ready: flat_flight-microbench (262) + controller-microbench (169) both staged for the const-CSE-application delta. + +## UPDATE 2026-06-04 (k) — NUDGED GI-NPA-003 (mutex callee, stalled); #247 test-only +Allocator track active (#243 liveness -> #245 const-CSE detection -> #247 liveness-vs-selector tests); all pre-codegen-app. +GI-NPA-003 (mutex callee promotion) STALLED: no maintainer reply to HW rebuttal since 17:23 (~1.75h); deliverable clock +crossed 2.5h. Posted friendly deliverable nudge (#237 c4625460808): confirm GI-NPA-003 queued, NOT closed by the leaf +merge (static 12-relocs/0-R9 passes while object BUS-FAULTs via 13 [r11] callee ops). Clock reset post-nudge. +#209 HEALTHY: measurement-ready (flat_flight 262 + controller 169 harnesses); waiting on const-CSE codegen-application. + +## UPDATE 2026-06-04 (l) — full 262->103 gap decomposition posted (#209 c4625712211) +Maintainer acting on my #209 data: PR#248 (real-selector evidence -> const-CSE is THE lever, dead-store/#246 a no-op), +PR#249 (immediate-folding encoder probe, And-imm path dead). Both test/ (pre-codegen-app, no byte change). +Disassembled both sides of the gap (synth 180 instr/262cyc vs gcc-O2 68 instr/103cyc): + clamps: synth 18 IT-blocks vs native 6 (3x; re-materializes 0x7e/0x7f x6) = BIGGEST chunk + mla: synth 0 (4 mul + sep add) vs native 2 (fuses g*980+a*20) -> mul+add->mla peephole + const-CSE: 21 redundant const-loads (#245); spills: 17 vs 0 (VCR-RA-001); strd: 0 vs 1 + sdiv 2/2 + branches 0/0 = ALREADY AT PARITY (backend bones right) +=> const-CSE+spills recover ~40-55 of 159cyc; clamp-lowering + mla-fusion are the bigger instruction-selection levers. +flat_flight-microbench(262) + controller(169) quantify each lever as it lands. Offered to file clamp/mla as tracked issues. + +## UPDATE 2026-06-04 (m) — FIRST codegen-application delta measured on silicon (PR#250) +PR#250 (feat/selector: fold i32.const C; i32.and -> and rD,rA,#C for C in 0..0xFF) = first delta-emitting transform. +Built (unmerged, ce6364c) + measured on G474RE: + flat_flight: 180->179 instr (movw 33->32, .text 588->584B); silicon 262 -> 261 cyc; SELFCHECK 0x07fdf307 OK + controller_step: 120->119 instr (movw 27->26); silicon 169 -> 168 cyc; SELFCHECK 0x05e33e81 MATCH +Folded exactly 1 AND-imm/fn (tail+not-spilled guard gates the other ~3 & 0xFF sites -> coupled to spill-elim). +Validates the maintainer-transform -> my-silicon-reflash loop end-to-end. Posted #250 c4625889530. +Bigger levers still ahead (per gap decomp): const-CSE on 0x7e/0x7f clamps x6, mla-fusion, clamp-lowering 18->6 IT. +Captures: flat_flight_pr250_261cyc.txt, controller_pr250_168cyc.txt. + +## UPDATE 2026-06-04 (n) — immediate-fold family complete (net -1cyc); #252 no-op on gale; big levers still ahead +#250 (AND-fold) + #251 (ORR/EOR encoder NOP fix, latent path) MERGED to main (a7676ec). #252 (or/xor fold) OPEN: +built + byte-diffed vs #250 -> IDENTICAL on flat_flight + controller (no or/xor-const sites; packing ORs registers). +So AND/OR/XOR immediate-fold family = net -1 cyc on gale benches (the single AND site, #250: 262->261, 169->168). +Posted #252 note: redirect to the needle-movers (const-CSE on 0x7e/0x7f clamps x6, mla-fusion, clamp-lowering 18->6 IT += ~150cyc of the 262->103 gap). Microbenches staged for each. #251 latent (we never emitted ORR/EOR-imm; selfchecks valid). + +## UPDATE 2026-06-04 (o) — #251/#252/#253 byte-identical no-ops on gale; FILED #255 (encoder bug-class audit) +Tested merge batch vs body of work: main(5cc26a0, #250+#251+#252+#253) == #250-build for flat_flight + controller +(small frames, no or/xor-const) and mutex == v0.11.30 (still faults). So #251/#252/#253 are latent-miscompile +correctness fixes we don't hit; only #250 AND-fold moves us (-1cyc, measured). No reflash needed. +PROACTIVE: audited arm_encoder.rs for the #251/#253 bug class (Operand2::Imm without ThumbExpandImm). Found 3 more: +encode_thumb32_cmp_imm + adds + subs still pack raw i:imm3:imm8 -> silent miscompile for imm>0xFF (e.g. cmp #1000). +#253 fixed add/sub (ADDW T4 + Err) but not the flag-setting S-variants or cmp. Filed issue #255 w/ suggested +shared try_thumb_expand_imm guard; offered on-target test vector. cmp_imm likely LIVE (threshold compares >=256). +Big perf levers (const-CSE on clamps, mla, clamp-lowering) still unlanded; microbenches staged. + +## UPDATE 2026-06-05 (p) — #255 FIXED (#256, ~1h!); exact const-CSE target posted; #254 no-op +My encoder bug report #255 -> FIXED by PR#256 (CMP/ADDS/SUBS via ThumbExpandImm) + closed within ~1h. Validated: +latent path (selector materializes ALL cmp consts: cmp #1000 -> movw+cmp-reg, even cmp #50), output correct. +#254 (add/sub fold) + #256: byte-identical no-ops on flat_flight/controller. +Disassembled flat_flight on #256 -> the "61% redundant const" is EXACTLY the clamp bounds: movw #0x7e x6 + #0x7f x6 += 12 movw of 2 distinct values. const-CSE APPLICATION (#245 detection -> emission) collapses 12->2 + frees regs +(relieves part of the 17 spills) = THE pending lever. BONUS: #256 unblocks cmp-imm folding (6 cmp-reg -> cmp #127), +same shape as #250 AND-fold. Posted #209 c4626463863. Microbenches staged (flat_flight 261, controller 168). +GI-NPA-003 (mutex): HOLDING re-nudge (nudged once, unanswered; maintainer responsive to reports but prioritizing +allocator track; re-ask = noise). Threshold extended 2.5h->4h for a genuine escalation if still untouched. + +## UPDATE 2026-06-05 (q) — BIGGER EXAMPLE validated: flight_control macro bench runs dissolved algo on silicon +EXPAND (independent of paused maintainer): built flight_control bench (Phase 5, GALE_FC_WASM_LTO=ON) on current +toolchain (synth 0.11.30 main256 + loom 1.1.10). Runs on G474RE: full 5-step sweep, NO FAULT, dissolved +filter_step+controller_step (pointer args, r11=0 tramp). Head-to-head algo: wasm-LTO=157 vs native=141 = 1.11x. +algo sensitive to build (157!=141) => measures the ACTUAL dissolved algo, not a placeholder (corrects old note). +In-context overhead ~11% (vs microbench 2.5x) — dissolved algo is a fraction of per-sample work (handoff/lock/ +post/round common). drain_timeouts on hi-rate/contention steps = bench rate tuning, not wasm. Captures in +benches/flight_control/runs/. RESULTS-SUMMARY macro-bench row added. = the "bigger example/big testbed" deliverable. + +## UPDATE 2026-06-05 (r) — quiet period (maintainer offline ~1h, EU evening); filed mla-fusion #257 +No new synth artifacts since #256 (22:01 UTC 06-04, ~1h ago); #209's 22:08 comment was mine (avrabe=me). Maintainer +likely wrapped for the night after the #250-256 session. 4h rule NOT triggered; open channels #209/#237/#257 satisfy +no-silence intent (won't file a redundant reminder overnight). Corrected loop clock: last_seen = true maintainer +activity, not my own. +EXPAND/OPT (independent): filed #257 — mul+add->mla fusion (lever #2 of the 262->103 gap decomp). Exact evidence: +flat_flight filter g*980+a*20 emits `mul;...;add.w` x2 sites where gcc-O2 uses `mla` (1 instr). Pure instruction +selection, composes with VCR-RA-001. Bonus noted: mul-by-const strength-reduction. Microbenches staged for the delta. +Pending levers: const-CSE application (maintainer building, 12->2 movw), cmp-imm fold (#256-unblocked), #257 mla, clamp-lowering(held). + +## UPDATE 2026-06-05 (s) — gap-decomposition fully tracked: filed #258 (clamp-lowering, lever #3) +Still quiet (02:01 EU, maintainer offline ~2h, main unchanged). Disassembled flat_flight clamp lowering precisely: +positive bound = `movw #0x7f; cmp rN,r5` -> should be `cmp rN,#0x7f` (3 sites); negative bound = +`movw #0x7e; mvns; cmp rN,r7` -> should be `cmn rN,#127` (3 sites). Both materialize instead of using the +immediate forms (encoders ready: cmp via #256, Cmn already present). Filed #258 (selector peephole): eliminates +6 movw + 3 mvns + 6 regs, complements const-CSE (dedup vs eliminate), relieves part of the 17 spills. +=> the measured 262->103 gap is now 3 tracked actionable issues: #209/#245 const-CSE (lever1, maintainer building), +#257 mla-fusion (lever2), #258 clamp cmp/cmn-fold (lever3). Microbenches + macro bench staged for each delta. +GI-NPA-003 (mutex) clock >4h but HOLDING re-nudge until maintainer active window (midnight EU; already nudged once). + +## UPDATE 2026-06-05 (t) — encoder audit extended: filed #259 (load/store imm12 no bounds-check) +Still quiet (02:32 EU, maintainer offline 2.5h). Continued the #255 encoder-bug-class audit into load/store: +encode_thumb32_ldr/str/ldrb/ldrsb/ldrh/ldrsh/strb/strh _imm all do `offset & 0xFFF` with NO bounds check +(0 Err in L6256-6470) -> silent wrong-address for offset>=4096. Same class as #253 but on memory (worse). +Latent for current workload (fields/frames <4096) but defensive-fix-worthy like #251/#256. Filed #259 w/ suggested +Err+register-offset fallback. INDEPENDENT BACKLOG NOW EXHAUSTED: 3 opt levers (#209/#257/#258) + 2 encoder +classes (#255 fixed, #259) + macro bench. Future offline firings = minimal holds until maintainer active window. + +## UPDATE 2026-06-05 (u) — maintainer AM session: #259 fixed (#261); both encoder classes closed +Maintainer back ~06:00-06:26 EU: fixed my #259 (load/store imm12 bounds-check) via PR#261 (CLOSED) + changelog #260. +Tested c91cec9 vs #256-build: flat_flight + controller BYTE-IDENTICAL (latent guard, offsets<4096, no regression). +Both reported encoder bug-classes now guarded: #255->#256 (arith-imm), #259->#261 (load/store-imm). Posted #259 close-out +(on-target test moot: guard makes >=4096 an Err -> selector materializes, wrong-address path unreachable). Optimization +levers #257(mla)/#258(clamp)/#209(const-CSE application) still OPEN — the bigger work, queued. Benches staged. + +## UPDATE 2026-06-05 (v) — LEVER #3 (clamp cmp/cmn fold #258) LANDED+MEASURED: -6cyc on silicon +Maintainer wired my lever #3: PR#262 "fold compare bounds into cmp/cmn immediates (#258)". Measured on G474RE: +flat_flight 261->255, controller 168->162 (both -6cyc, SELFCHECK correct). cmn fold fired on negative bounds +(movw 32->26, mvns 6->3, cmn 0->3, net -9 instr). First BIG lever (vs immediate-folds -1). Posted #258 c4628561325. +PR#263 = MLA op-support (#257) but "ready-to-wire", NOT emitting (mul=4/mla=0) -> byte-unchanged, wiring next. +Arc: flat_flight 315(v18)->262->261(#250)->255(#262); native 103. Pending: const-CSE application (#209, 12->2 movw +on bound ASSIGNMENTS the cmn fold doesn't touch) + mla wiring (#257/#263). Benches staged. Capture: flat_flight_262clampfold_255cyc.txt + +## UPDATE 2026-06-05 (w) — v0.11.31: mla WIRED (#264) but fires 0x on real flat_flight; #266 no-op +v0.11.31 (#265) released: mla fusion wired (#264) + #266 (AND/CMN ThumbExpandImm). Tested on G474RE-build: +flat_flight v0.11.31 BYTE-IDENTICAL to #258-build (mul=4/mla=0, 170 instr, still 255 cyc) — MLA fusion fires +ZERO times on the actual gale flat_flight despite maintainer's "~18 muls fused" (a simpler fixture). Exact reason: +filter mul->add are scheduler-interleaved across the 2 axes; the adjacent `mul r8,r6,r7; add r2,r5,r8` should fuse +to `mla r2,r6,r7,r5` but mul is the add's 2nd operand -> likely add-commutativity not matched; the other mul's +consumer has a ldrsh between (conservative block). Re-commented #257 (c4628718993). #266 byte-identical (cmn #127<=0xFF). +LEVERS: #258 clamp DONE (-6, 255). #257 mla wired-but-0-fires (reported). #209 const-CSE application pending. Benches staged. + +## UPDATE 2026-06-05 (x) — mla NOW FIRES (PR#274, my diagnosis) but silicon REGRESSES +2cyc +My instrumented diagnosis (reg-reuse blocks whole-function used_elsewhere) -> maintainer PR#274 (live-range-bounded fix, +synth 0.11.32). Built: mla NOW fires on flat_flight (mul 4->2, mla 0->2, -2 instr, 0x07FDF307 correct). +BUT G474RE: 255 -> 257 cyc (+2, STABLE x2 re-measures). mla is net-NEGATIVE over the greedy selector — folding +extends r3/r4/r8 live ranges to the mla point, selector pays elsewhere > the 1cyc/site MLA saving. byte-count +(-2 instr / 1891->1819B) looked like a win; on-target cycles regressed. Reported #274 c4631214680: GATE mla behind +the allocator (VCR-RA-001); its value is coupled to register allocation. Capture: flat_flight_274mla_257cyc_REGRESSION.txt. +KEY: this is exactly why on-target measurement matters — host/byte checks would have merged a regression. + +## UPDATE 2026-06-05 (y) — v0.11.32 mla default-on: MIXED on silicon (filter +win, flat_flight +regress) +v0.11.32 (#274 merged) ships mla fusion default-on. Tested body of work on silicon (mla fired on filter_axis+control_step+flat_flight): + filter_axis: 37 (v31) -> 36 (v32) = -1 cyc WIN (1 fusion, clean). SELFCHECK 1088. + flat_flight: 255 -> 257 = +2 cyc REGRESS (2 fusions interleaved across axes, live-range pressure). 0x07FDF307. + controller_step: unchanged (no mul). control_step: 2 mla fired but UNMEASURED (needs tables harness) - pending. +=> mla MIXED: helps simple kernels, hurts the complex interleaved one. Filed #277 + refined (c4631625693): + NOT blanket default-off (forfeits filter_axis win) -> allocator-gate (#272, resolves pressure) or cost-guard. +KEY: on-target measurement revealed BOTH the regression AND that it's mixed — byte-count/host checks would see neither. +Built filter_axis microbench (register-only, 3-arg AAPCS). Clock=v0.11.32. + +## UPDATE 2026-06-05 (z) — mla regression RESOLVED: maintainer un-wired (PR#278) per my #277, verified 255 on silicon +My #277 on-target finding (mla +2 regress, mixed) -> maintainer agreed + un-wired mla default-on (PR#278/v0.11.34). +VERIFIED on G474RE: #278 flat_flight = 255 (0x07FDF307), byte-identical to v0.11.31 (mla un-wired). Regression gone. +Maintainer ADOPTED my methodology as their bar: "byte-count insufficient for register-affecting transforms; need +on-target/allocator-aware gate before default-on." fuse_mul_add stays as infra, re-wires WITH the allocator (#272, +spill-aware) so it's net-positive on both filter_axis (simple, +win) and flat_flight (interleaved) shapes. +v0.11.33 (#276 call_indirect reachability) = no-op on our value benches (byte-identical). Posted #277 close c. +Baselines restored: flat_flight 255, filter_axis 37 (mla un-wired). Allocator wiring (#272) remains the #209 lever. + +## UPDATE 2026-06-05 (aa) — v0.11.34 un-wire mla: full-suite shows mla was net-POSITIVE (control_step also a win) +v0.11.34 (#278 un-wire mla) released. Re-measured all mla-affected benches on G474RE: + filter_axis: mla 36 / no-mla 37 (-1 WIN); control_step: mla 156 / no-mla 158 (-2 WIN); flat_flight: mla 257 / no-mla 255 (+2 REGRESS). +=> mla WINS 2/3, net -1 across suite. Blanket un-wire (#278) trades the filter+control wins (+3) for the flat_flight fix (-2) = net +1 WORSE. +Regression signature is specific: flat_flight's INTERLEAVED 2-fusion (both mul products live at the combining add). filter/control = single fusion, product dead after = clean win. +Reported #277 c4632454747 (constructive, not revert): cost-guard skips only the interleaved shape (keeps wins now), OR allocator-gate recovers all. +Corrected control_step baseline to 158 (v0.11.34 released, mla un-wired; mla-on=156). Current released: filter 37, controller 162, control_step 158, flat_flight 255, macro 1.11x. + +## UPDATE 2026-06-05 (ab) — MILESTONE: maintainer routes const-CSE + mla through the allocator (my data decisive) +Maintainer decisions (#209 c14:52, #277 c14:35), explicitly crediting my on-target data: +- const-CSE (#209): lands via the ALLOCATOR (rematerialization-avoidance), NOT a standalone peephole. My #277 mla + regression data was "decisive" — const-CSE is the SAME register-affecting class (resident const extends live range + -> regresses over greedy selector). ~14 redundant const materializations confirmed on v0.11.34 flat_flight. +- mla (#277): cost-guard DECLINED (principled — it's the patch-accretion VCR-RA-001 exists to remove). My suite data + = "the concrete justification to prioritize the allocator wiring." +- Both collapse into ONE prerequisite: virtual-register selector output + allocator wiring (recovers const-CSE + mla + 17 spills together, net-positive by construction). +- ACCEPTANCE GATE (maintainer set, using MY baselines): re-enable fusion only when net-positive across + filter 37 / control_step 158 / flat_flight 255 on-target, NO per-shape guard. +PR#279 (model SelectMove/Select in reg_effect — see resident clamp consts across IT-block chains) = first increment. +Confirmed acceptance contract #209 c4632909409: I run the no-guard check + per-bench delta breakdown when the build lands. +5 silicon benches frozen+staged. The allocator wiring is now THE convergence point for all the optimization levers. + +## UPDATE 2026-06-06 (ac) — PR#283 in-place select: BIGGEST lever (-33cyc across clamp benches) +PR#283 (in-place Select, elide keep-val2 move, VCR-SEL-002). Measured on G474RE, all correct: +flat_flight 255->241 (-14, 170->157 instr, 0x07FDF307); controller 162->150 (-12, 110->99); control_step 158->151 (-7, 121->113); +filter_axis unchanged (no select). = -33cyc total. The clamps (18 IT-blocks) were the dominant cost; eliding the per-Select +keep-val2 move cuts directly in. CONFIRMS instruction-selection (clamp lowering) is the larger slice of the 255->103 gap, +NOT the allocator (const-CSE was -1). flat_flight now 241/103 = 2.34x. Posted #283 c. New acceptance gate when merged: +flat_flight 241 / controller 150 / control_step 151 / filter 37 — const-CSE/allocator deltas stack on top. + +## UPDATE 2026-06-10 07:55 — v0.11.35 validated (cycle-neutral, −6% code); #288 realloc flag-on gate CLEARED on silicon + +synth **v0.11.35** (#285 Chaitin spill-cost ranking): full suite re-measured on G474RE — **flat_flight 241, +controller 150, control_step 151, filter 37 — all identical to v0.11.34, all selfchecks OK**, code −6% +(ff 560→526B, ctl 316→296, cs 370→346). Cycle-neutral release, no issue needed. + +**#288 `SYNTH_RANGE_REALLOC=1`** (main b657521, "first consequential allocator step", flag default-off +*pending gale's on-target confirmation*) — confirmation DELIVERED same-day to #209: flag-on is +**byte-identical** on ff/ctl/cs; fires only on the filter family (r4–r8 re-coloured → r0/r1, add.w→adds, +−2B), correct on unicorn funccheck + silicon SELFCHECK, **cycles neutral (37/29/30 both states)** → +gate cleared to default-ON. Next lever posted with the data: **dead callee-saved-save elimination after +realloc** — filter's prologue still saves the now-dead {r4–r8} (~12 of 37 cyc is push/pop overhead → +−25%+ on small leaves; composes with VCR-RA-002 R10-pool). + +Ops: macOS cleaned /tmp/opt3 + /tmp/wasm-algo-poc (funccheck modules + fv_algo.o) — recreated; fv_algo.c ++ build_fv_algo.sh now LIVE IN-REPO (silicon-microbench/). Serial-capture flakiness root-caused: cat/stty +drops boot output ~50% of runs; **pyserial captures every time** → capture_serial.py added to wasm-testbed/. + +## UPDATE 2026-06-10 15:45 — #209 reply: all 3 accepted; v0.11.36 today (flag ON + dead-save elim); PREDICTION on record + +Maintainer (13:15Z): v0.11.35 validation recorded (241/150/151/37 = the reference set), **`SYNTH_RANGE_REALLOC` +default-ON in v0.11.36** (authorized by our silicon gate), **dead callee-saved-save elimination ships in the +same v0.11.36** (v1 scope: shrink push/pop to post-realloc used set, only for fns with NO SP-relative body +accesses; frame-bearing fns = v2 with offset rebasing). #237 (mutex SP-init) → v0.11.37. Tag incoming today. + +**Prediction (pre-tag, falsifiable):** filter full 37→25±2, nodiv 29→17±2, div 30→18±2 (push{r4-r8,lr}+ +ldmia≈12 cyc eliminated). flat_flight/controller/control_step: NO change (realloc byte-NO-OP + v1 scope +excludes SP-relative fns). If the big-3 move or filter lands outside 23–27 → publish the falsification. + +## UPDATE 2026-06-10 16:10 — PR #309 (v0.11.36 cand.) pre-merge validated: filter −8 cyc uniform; prediction FALSIFIED on magnitude + +Built b762ac1 pre-merge: big-3 **byte-identical** (241/150/151 stand); filter family on silicon: **full 37→29, +nodiv 29→21, div 30→22 (−8 uniform)**, all SELFCHECKs OK, funccheck ALL GREEN both flag states. Prologue +`push {r4-r8,lr}` → 16-bit `push {r4,lr}` (40→34 B). **Prediction (−12) falsified: −8 measured** — v1 retains +{r4,lr} for AAPCS alignment (~4 cyc left on the table). Posted validation + falsification + v2 lever to #309: +**leaf-function prologue elimination** (no outgoing calls ⇒ no push/pop at all, bx lr) → expected 29→~25. +Verdict posted: good to merge + tag. Gap vs native: filter full 1.95×→1.53×. + +## UPDATE 2026-06-10 17:1x — 907 PROVENANCE BROKEN: sem shim was never faithful; faithful rebuild hangs (investigation open) + +Re-built the sem .o on v0.11.35 + loom 1.1.11 (the loop's "rebuild the sem .o" check, first since v0.11.15): +code 702→524 B (−25% across 20 releases). Drop-in re-measure on the engine_control bench: + +1. **MPU FAULT** (DAV @0x8002b35, `sys_dlist_remove`←`z_abort_timeout`) — root-caused: **`wasm_host_shim_poc.c` + has ALWAYS passed `(void*)0)` as the wait_q** (git history confirms, single commit) and declared + `struct k_sem {count,limit}` — skewed −8 B vs the real layout (`wait_q` first). `z_unpend_first_thread(NULL)` + reads the vector table; the rebased zephyr v4.4.0 final (#44, June 6) turned that latent unsoundness into + a hard fault. ⇒ **The May-31 907-cyc run's wake path was never semantically sound; 907 needs re-validation.** +2. **Shim FIXED to faithful** (real k_sem mirror {wq_head,wq_tail,count,limit}, `z_unpend_first_thread((void*)sem)` — + identical contract to gale_sem.c's give: unpend→retval_set(0)→ready). v0.11.35 object: 532 B, links clean + (localize gale_k_sem_give_decide vs native FFI duplicate — new step, wasm-ld now keeps it global). +3. **No fault now, but bench HANGS at first handoff** (headers + D,boot, then silence; reader poll rows absent too). + Prime suspect: the **u64-packed decide return** (r0:r1) under v0.11.35's changed i64 lowering — action field + reads wrong → neither WAKE nor count update. NEXT: unicorn-emulate the v0.11.35 sem body with stubbed gale_w_* + imports; check decide's u64 return + count store offset; if miscompiled → NEW synth issue with the repro. + (v0.11.14 cross-check impossible on today's module: it predates internal-callee emission — module shape drifted.) + +Isolation status: NOT yet attributable to synth — could be shim/contract. Do NOT file until unicorn isolates it. + +## UPDATE 2026-06-10 17:1x — sem hang ISOLATED → synth#311 filed (i64 unpack clobbers the live u64 pair) + +Unicorn isolation of the faithful-shim hang: the give body stores **[sem+8]=0 where the verified decide +contract requires 1** — disasm shows `bl gale_k_sem_give_decide; movw r0,#8; movw r1,#255` — the unpack's +mask constants are materialized INTO the live u64 return pair before being read. Built a 15-line minimal +repro (`u64repro.c`): wasmtime ground truth `check(3,4)=8` vs synth ARM under unicorn `=0xDEAD` — and loom +had inlined the callee there, so the single-function i64 shift/mask path is wrong too, not just post-call. +**Silent wrong-code** (no fault) — k_sem_give does nothing → bench hangs. Reproduces byte-identical on the +PR #309 head. Same class as #232/#255 (constants vs liveness) → **filed synth#311** with both repros + the +alloc_temp_avoiding suggestion. BLOCKS: sem re-baseline (907 refresh) + every packed-u64 verified-decide +primitive. Staged for same-day re-measure on the fix. + +## UPDATE 2026-06-10 18:1x — #311 BISECTED: v0.11.18's #214 (R12 reservation) is the culprit; broken since June 2 + +u64 lane across tags: v0.11.14/17 GREEN; **v0.11.18 first RED** (single commit f7190fc = #214 R12/IP +encoder-scratch reservation, itself the #212 fix); RED through v0.11.35 + #309 head. Mechanism: constants +formerly materialized into R12; with R12 reserved the fallback picks r0/r1 with NO liveness check → clobbers +live u64 returns. NOT a v0.11.35 regression — every release since v0.11.18 silently miscompiles packed-u64 +unpacks; our sem survived only because it was pinned on v0.11.15 faithful4.o. Posted bisect + mechanism + +fix scope (alloc_temp_avoiding on the scratch-less constant fallback) to #311. + +## UPDATE 2026-06-10 18:4x — #311 backend scope-check → filed synth#312 (RV32 rejects i64 local.tee) + +Ran the u64 repro through the RV32 backend: **refuses to compile** (`RISC-V selector: stack type mismatch +at op LocalTee(2): expected i32, found i64`) — fail-safe vs ARM's silent wrong-code, but a hard blocker: +the packed-u64 verified-decide pattern currently has NO working backend (ARM = #311 silent miscompile since +v0.11.18; RV32 = #312 compile rejection). Filed #312 with the cross-backend table + ask (i64 local ops via +a-reg pairs). u64_funccheck.py grows an RV32 leg when it compiles. + +## UPDATE 2026-06-10 19:1x — RV32 re-baseline on v0.11.35: flat_flight 181→172 (−9); filter/control_step unchanged + +qemu_riscv32 -icount, RV32 funccheck ALL GREEN. filter 23 / control_step 129 (both = v0.11.27), +**flat_flight 172 (was 181, native 75: 2.41×→2.29×)**, chk correct. Cross-target read: the v0.11.28-35 +allocator levers moved RV32's composed path while ARM flat_flight stayed 241 — RV32 had more residual +register pressure to harvest. controller icount number pending (funccheck-correct). Run archived: +runs-riscv/2026-06-10-qemu_riscv32-v0.11.35-rebaseline/. + +## UPDATE 2026-06-10 20:1x — PR #310 pre-merge tested: call-form FIXED, inlined shape still RED → 2 new defects pinpointed on #311 + +Built #310 head (9107188): u64 lane still 4/4 RED on the loom-inlined shape — but the #310 fixes all hold +(8-byte tee slot, both halves stored, shifts/masks correct). Capstone'd the tail and pinpointed the REAL +remaining defects: (1) **i64.eq boolean materialization emits `cmpeq/cmpne` instead of `moveq/movne`** — +result computed in flags, thrown away; (2) **`select` conditions on a stale vstack reg (r8** = the +extend_u hi-half from 40 insns earlier). The inlined failure is the i64.eq→select chain, NOT constants. +Posted full annotated disasm + 50-line wat to #311 (answers the maintainer's open question pre-tag). + +## UPDATE 2026-06-10 20:4x — RV32 table completed: controller_step 100 on v0.11.35 (unchanged, correct) + +Final RV32 v0.11.35 re-baseline: filter 23 / controller 100 / control_step 129 (all = v0.11.27), +flat_flight 172 (−9). Only the composed path moved — leaves were already harvest-complete after v0.11.27's +caller-saved preference. Run dir complete. + +## UPDATE 2026-06-10 21:2x — #311 defect #3 found (callee i64 return drops hi half); loom v1.1.12 unbuildable → loom#198 + +**#310 re-test (90e3c5a):** MOVS→CMP transmutation fix VERIFIED — u64 lane 4/4 GREEN (maintainer credited the +disasm as "the whole diagnosis"; our wat = their committed fixture u64_unpack_inlined.wat). But the REAL sem +body still stores count=0 → traced INSIDE decide: packed result computed correctly in r5/r6, epilogue emits +`mov r0,r5` and **NO `mov r1,r6`** — callee-side i64 return materializes only the lo half whenever the value +isn't already in r0/r1. Defect #3 posted to #311 (call-site tagging ✔, return-site pair move missing). +**loom v1.1.12** (CRITICAL #196 elem-segment fix): tag does NOT build from source (stale CodegenOptions +literal + ISLE u32 prelude collision vs locked cranelift-isle 0.132.1) → filed **loom#198**. We stay on +v1.1.11 SAFELY: all suite modules verified 0 elem segments (#196 class can't bite them). + +## UPDATE 2026-06-11 08:1x — v0.11.36+37 TAGGED overnight; all #311 legs VERIFIED; sem silicon number blocked on NEW integration hang (ADC lock) + +v0.11.36 (#311 all 3 legs + #237 globals/sizing + realloc-ON + dead-save elim) and v0.11.37 (#312 RV32 i64 +locals) both tagged. Installed v0.11.37: **testbed ALL GREEN incl u64 lane (both shapes)**; sem unicorn gates +PASS (no-waiter count 0→1 ✔, WAKE arm retval+ready ✔); big-3 byte-identical (241/150/151 stand); filter .o +byte-identical to measured #309 head → **29/21/22 ships in the release**; sem module .bss ELIMINATED (#237 +used-extent sizing — no stack-size workaround). + +**BLOCKER:** engine_control + wasm-sem hangs at H,boot (ADC health read) BEFORE any bench give. Evidence: +1 give system-wide (adc init unlock, correct/surgical); main pended on ADC ctx LOCK (live: waiter, count=0, +limit=1) with ADSTART=0/IER=0 (conversion never started, lock held); no fault; idle PC; relocs correct; no +symbol shadowing; native-gale control = full sweep CLEAN. The give is object-level correct everywhere — +hang is in the ADC driver lock/start sequence, only with the override linked. NEXT: gdb thread walk + +trampoline hit-count through the H-read window; consider bench variant with health stub (smart_mcu_stub.c) +to decouple the sem number from the ADC question. Status posted to #311 (comment 4677468542). + +## UPDATE 2026-06-11 10:1x — SOUND SEM RE-BASELINE: **860 cyc** (v0.11.37, faithful shim); ADC-hang bypassed + confirmed as the blocker + +CONFIG_ADC=n (health stub — the bench's own comment notes ADC IRQ-table interactions crash LTO variants too) +→ full sweep clean: **handoff median 860, min 860, max 1586 cold, n=148, drops=0**. First semantically-sound +number: faithful shim (real wait_q, correct unpend/wake — all three #311 legs verified on silicon) is +**47 cyc FASTER than the unsound 907** while doing more work correctly — 20+ releases of codegen +(caller-saved pref, const-CSE remat, in-place select, spill-cost, i64 pair work) on the same path. +860/471 = 1.83× LLVM-LTO (was 1.92×). ADC interaction = separate tracked thread (pre-existing class). +Run: runs/2026-06-11-nucleo_g474re-wasm-cross-lto-v0.11.37-faithful/. + +## UPDATE 2026-06-11 10:4x — #312 VERIFIED on v0.11.37; u64 lane grows the promised RV32 leg (3-way differential) + +`synth compile -b riscv -t rv32imac` on the u64 repro: compiles (328 B; was a hard selector rejection) and +under unicorn RISCV32 computes **4/4 correct**. u64_funccheck.py is now a **wasm/ARM/RV32 three-way +differential** — both backends of the packed-u64 verified-decide pattern are guarded per release. The +"fail-safe vs silently-wrong" backend split is closed, both lanes correct, exactly as scheduled. + +## UPDATE 2026-06-11 15:4x — mutex lane: NEW blocker (register exhaustion since v0.11.36) → synth#326 + +remeasure_wasm_lto.sh on v0.11.39: #237's bss/SP fixes hold (no -z stack-size needed), but z_impl_k_mutex_unlock +now SKIPS at compile: "register exhaustion: no free callee-saved register to hold a call result while reloading +a preserved param". Bisect: compiled on v0.11.35, first-bad **v0.11.36** (the #311 call-result PAIR tagging = +likely pressure source — the fix that made sem correct costs a reg pair across calls; mutex is our densest body). +v0.11.38's 3b-lite spill-retry does NOT cover this site. Fail-safe (skip) but blocks the mutex silicon number +(native ref 124). Filed **synth#326** w/ bisect + mechanism + ask (extend 3b retry or note as known-limitation +until full RA-001 wiring). Staged for same-day measure on fix. + +## UPDATE 2026-06-11 17:5x — v0.11.40: #326 VERIFIED (mutex lane compiles+runs); TWO shim faithfulness bugs fixed; one anomaly left + +v0.11.40 installed: suite + sem BYTE-IDENTICAL, testbed ALL GREEN, and **the mutex lane compiles again** +(#326 resolver-scratch fix verified). First run exposed the mutex shim's own unfaithfulness — SAME class as +the sem-907 finding: (1) `wait_q` declared as ONE pointer (v4.4 _wait_q_t = dlist = TWO) → owner read at +4 += dlist tail → always "not current" → rc=-EPERM (observed owner=0x200101b0); (2) unpend called with the +wait_q CONTENT not its address. Both fixed (faithful k_mutex mirror + `(void*)mutex`). After fixes: +**rc=0** on silicon — but **owner reads 0x1 post-release (exp NULL)** and the cycle line is pending that. +NEXT: clean unicorn isolation of the release path (the ad-hoc flat-bin harness mis-assembled — use the +section-aware loader like the sem one). Native ref 124 cyc; measurement follows the owner fix. + +## UPDATE 2026-06-13 09:4x — RETRACTED the #326 "undefined encoding": it was MY flat-link harness, synth is clean + +Reconciled the rc=0-on-silicon vs undefined-encoding contradiction. synth v0.11.40 mutex object is CLEAN: +882 B, 269 insns, capstone covers 100% of .text, no f5e0 anywhere; byte-identical to the object I'd +disassembled. The `f5e0 0109` at body+0xc was my `ld -Ttext=0x8000` unicorn-prep harness mis-applying the +R_ARM_THM_MOVW_ABS_NC reloc on a `movw r1,#imm` against a zero stub — NOT synth codegen. Posted full +retraction to #326 (comment 4697891080); the exhaustion fix is verified working, #326 can close. +LESSON: never disasm a flat -Ttext link of a relocatable with unresolved MOVW/MOVT data relocs — the +patched immediates masquerade as undefined opcodes. Use section-aware load + real symbol resolution +(the sem isolation harness did this correctly). + +REMAINING (ours): bench selfcheck rc=0 (unlock OK) but owner=0x1 post-release (exp NULL) + cycle line +absent → measure loop faults/hangs. Shim logic inspects correct (owner@+8 matches v4.4 dumb-waitq k_mutex). +NEXT: instrument the shim with printk of {cur, decide fields, new_owner} + reflash, observe on silicon +(don't guess); serial capture is flaky so retry. The 124-cyc-ref number follows once owner round-trips. + +## UPDATE 2026-06-13 10:1x — mutex owner=0x1 isolated to a REAL on-silicon failure (root cause NOT yet found; two hypotheses falsified) + +Instrumented the mutex-microbench selfcheck + the unpend wrapper, clean pyserial capture (reset+retry): +``` +DBG pre-unlock: owner=0x200101b0 lock_count=1 cur=0x200101b0 ← correct (owner==cur, count=1; shim reads real k_mutex fine) +DBG unpend(wait_q=0x20010238) -> 0 ← correct (no waiter -> NULL) +SELFCHECK ... owner=0x6f42202a lock_count=1852404847 ← GARBAGE (ASCII fragments) after unlock +***** BUS FAULT ***** +``` +So: pre-state correct, unpend correct → corruption happens DURING the unlock body's no-waiter tail +(owner:=NULL; lock_count:=0; spin_unlock; return). Real, reproducible on hardware (not a capture/harness +artifact — earlier garbled run was capture corruption; this is clean). + +FALSIFIED hypotheses (do NOT report as synth bugs): +1. "undefined encoding f5e0 0109" — was my flat-link harness (retracted on #326). +2. "body writes past its stack frame" — naive max[sp,#56] vs sub-sp#40 looked like overflow, BUT the + push {r4-r8,lr} moves sp down 24 first, so [sp,#56] = entry-8 = inside the saved-reg block, NOT past frame. + Frame math is sound; overflow hypothesis dead. + +NEXT (do not guess): gdb on the live target — break at the trampoline `pop {r11,pc}`, read sp vs entry-sp +(stack-balance check), and on the BUS FAULT read CFSR/BFAR + stacked PC to see the faulting access. Only +after that, attribute to synth (body codegen) vs our trampoline/shim. Sem path (860, same trampoline) works, +so it's mutex-body-specific. Diagnostic instrumentation reverted from the shared wrapper. + +## UPDATE 2026-06-13 10:4x — gdb on-target: mutex unlock BODY executes correctly (3rd hypothesis falsified); residual queued + +gdb/openocd on the live G474RE (break trampoline entry 0x08003d78 + post-body pop 0x08003d84): +- ENTRY sp=0x20002560, r0=0x20001238 (&m). AT-POP sp=0x20002558 = **entry−8 exactly** (the push{r11,lr}) + → **stack is balanced**; the synth body restores sp perfectly. Stack-imbalance hypothesis FALSIFIED. +- post-body read m@+8 (owner)=**0x0 (correct NULL)**, m@+12 (lock_count)=0x1. So the body DID write + owner=NULL on the no-waiter path; the earlier serial "owner=0x6f42202a garbage" was CAPTURE corruption, + not real memory. The #326 resolver-scratch fix genuinely works at the body level. + +THREE hypotheses now falsified, ZERO claimed: encoding (harness), frame-overflow (sp math), stack-imbalance (gdb). +RESIDUAL (queued, not a synth claim): (a) lock_count reads 0x1 where the no-waiter path sets 0 — but the +12 +offset isn't yet confirmed against the real k_mutex DWARF, so this read may be untrustworthy; (b) a later +bus fault (measure loop / printk) not yet caught at z_arm_fault with CFSR/BFAR. NEXT focused session: confirm +k_mutex field offsets from DWARF, re-read owner/lock_count at the verified offsets, and trap the fault PC. +Decision: stop multi-firing rabbit-hole here — body-level correctness is established; residual is bounded. + +## UPDATE 2026-06-13 11:0x — mutex residual sharpened to ONE fact (DWARF-confirmed); attribution method pinned + +DWARF (ptype /o struct k_mutex): wait_q@0(8) owner@8 lock_count@12 owner_orig_prio@16 — so the prior gdb +reads were at CORRECT offsets. Post-unlock (no-waiter): **owner@8=NULL (correct), lock_count@12=1 (anomalous — +the UNLOCKED branch sets it 0)**. Real, not a misread. +Disasm of the body: all mutex-field stores are linmem-relative `str.w rX,[fp,ip]` (computed offset, fp=0 via +tramp), so static disasm CANNOT confirm whether the lock_count store fires — owner@8 demonstrably written, +lock_count@12 not (or overwritten). DEFINITIVE next step (focused session, NOT this firing's rabbit-hole): +gdb hardware watchpoint on (&m+12) across the unlock to see if/when it's stored; that attributes synth +(missing/mis-offset store) vs shim. NOT posting to any issue until attributed. Note: the "bus fault" only +appeared in the corrupted-capture serial run; clean gdb runs hit entry+pop with no fault — fault reality +still open (re-confirm in the watchpoint session). + +## UPDATE 2026-06-13 11:3x — mutex lane: blocker characterized, ISOLATION PAUSED (needs focused session, not loop firings) + +Consolidated after 4 loop-firings of isolation. Established facts (hardware/gdb-grounded): +- SINGLE unlock (selfcheck) WORKS: gdb confirms sp balanced (entry-8 at tramp pop) + owner@8 written NULL. +- The 200× measure loop NEVER emits "E,k_mutex_unlock,cyc=" (5 robust pyserial retries) — hangs or silently + faults in the loop. This (not the selfcheck) is the blocker. +- lock_count@12 reads 1 post-unlock (DWARF-confirmed offset; UNLOCKED branch should zero it) — prime suspect + for loop-state divergence across the 200 lock/unlock iterations. +- serial "owner=0x1" is a printk/capture ARTIFACT (gdb reads the same field = 0 = NULL). Don't trust serial + field values here; trust gdb. +- watchpoint on 0x20001244 (lock_count) caught a `<-1` write but the stop-PC decode was inlined-noise; + attribution (synth missing/mis-offset store vs shim) still OPEN. + +DECISION: pause loop-firing isolation (4 firings is enough; this is a focused-debug task, not a 30-min tick). +RESUME RECIPE (one sitting): rebuild /tmp/mtx-gdb; gdb break at the measure-loop body; STEP through iterations +2-3 watching m.owner/m.lock_count + sp at each tramp pop; find the iteration where it diverges/faults; read +CFSR/BFAR if it faults. Then attribute + either fix the shim or file a sharp synth issue. NO issue post until then. +Sem lane (860, sound) unaffected; mutex was always the harder host-pointer primitive. + +## UPDATE 2026-06-13 15:4x — mutex measure-loop blocker = DEADLOCK, mechanism fully traced (attribution still bounded-open) + +Ran the owed gdb session. The measure loop does NOT bus-fault — it DEADLOCKS: +- Halted hung target → backtrace = **idle thread** (idle→k_cpu_idle→arch_cpu_idle→__enable_irq), lock_count=1 owner=0. +- Mechanism (sound from Zephyr k_mutex_lock logic): dissolved unlock no-waiter path writes owner=NULL ✓ but + leaves **lock_count=1**; next `k_mutex_lock(&m,K_FOREVER)` sees lock_count≠0 ∧ owner≠current → BLOCK path → + z_pend_curr forever on an ownerless mutex → main never returns → CPU idle → cycle line never emits. +- So the earlier "hang" + "lock_count=1" findings UNIFY: lock_count-not-zeroed IS the deadlock cause. + +Shim source IS correct (no-waiter else-branch: `mutex->owner=NULL; mutex->lock_count=0U;`). owner@8 store +lands (gdb), lock_count@12 store does NOT → strong indication the compiled body drops the 2nd adjacent +field store. NOT yet confirmed (auto-continue hw-watchpoint traces were inconclusive — the boot-time +selfcheck unlock races reset-then-break). NO synth issue filed until confirmed (4th-false-alarm guard). +CLEAN ATTRIBUTION METHOD (next): disasm the body, breakpoint exactly at the lock_count-store site (or +single-step the no-waiter tail), confirm whether a store to [mutex+12]=0 is emitted/executed. If dropped → +synth issue w/ the deadlock as impact; if shim → fix in gale-smart-data. Either way the fix is small now +that the mechanism is pinned. Sem(860) unaffected. + +## UPDATE 2026-06-13 16:1x — mutex deadlock ATTRIBUTED & FILED (synth#331): spill-slot collision miscompile + +Got the clean attribution WITHOUT a flaky watchpoint run — by decoding the actual compiled +`body.o` (synth v0.11.40) with llvm-objdump (thumbv7em). The lock_count=0 store IS emitted +(falsifies "synth drops the store"); the bug is a SPILL-SLOT COLLISION: +- `[sp,#0x24]` = mutex-ptr arg0 home slot (entry 0x8), live to 0x1e2. +- 0x13a reuses that slot for `gale_w_unpend_first_thread`'s result (reloc-confirmed). +- no-waiter path 0x1e2 reloads the clobbered slot (=0 when no waiter) as the mutex base, + so `lock_count=0` store (0x1ee) writes linmem[12] not mutex->lock_count -> stays 1. +- owner store (0x156) survived via register copy r7; predicts EXACT observed (owner=0, + lock_count=1) -> the hardware deadlock. Has-waiter path (0x16a) corrupt too (unexercised). +Decode rests on the real flashed binary + the real hardware symptom (not a guess). Filed +synth#331 with disasm + reloc evidence + kill-criterion + fix direction (don't reuse a live +arg's spill slot for a call result; keep mutex base in callee-saved reg across the body). +Same family as #311 (live-value clobber) / related to #326 (exhaustion at same site). + +CONSEQUENCE: mutex k_mutex_unlock silicon cycle number (native ref 124) is BLOCKED on the +synth#331 fix — the deadlock prevents measurement. Owed-by-me item is now a sharp, +maintainer-owned blocker (bucket 2). sem(860) unaffected; testbed control/controller/filter ++ u64 lane all green on v0.11.40 (run this firing). + +## UPDATE 2026-06-13 16:3x — optimize thread: quantified flag-fold recommendation -> synth#209 + +Mutex thread blocked on synth#331 (filed last firing, no maintainer response yet). Pushed the +OPTIMIZE thread instead. Disassembled a CORRECT dissolved body (control_step_decide, v0.11.40, +113 insns/354B, silicon 151 cyc vs 67 native = 2.25x) to find where we lose to native/LLVM-LTO. + +DOMINANT loss = comparison->select FLAG ROUND-TRIP, 6 occurrences in this one body: +synth does `cmp ; ite; movCC #1/#0` (materialize i32 bool) then `cmp bool,#0; it; movCC` +(re-test it). 7 insns where 3 suffice (cmp; it; movCC). Bool is dead after the re-test +(verified r8 redefined at 0x90). ~4 removable insns x6 ~= 24 cyc ~= 29% of the 84-cyc gap, from +ONE pattern — and it recurs in every body with a compare feeding a select (controller/filter +clamps; likely a chunk of the sem 907-vs-471 gap too). Posted to #209 with disasm evidence, +quantified impact, the recommended compare->select fusion peephole (keep condition in NZCV, don't +materialize), kill-criterion (re-measure control_step toward ~127 when a release lands). +Secondary: 10 mov rX,rY reg-shuffles/113 (coalescing) + single [sp] scratch churn — noted as +lower-priority allocator items. + +## UPDATE 2026-06-13 17:0x — optimize thread: headline (sem) overhead breakdown -> synth#209 follow-up + +No new release (v0.11.40/v1.1.13). 4h rule N/A (~2h42m). #331/#209 no maintainer response yet. +Pushed optimize thread to the HEADLINE: rebuilt the fully-dissolved k_sem_give path with the +exact release recipe (build-wasm-dist.sh, FFI wasm staticlib + shim -> wasm-ld -> loom inline -> +synth). 540B/165 insns, 4 funcs, seam folded (no bl decide). Findings: +- Flag round-trip (the #209 finding) RECURS in sem (sites 0x50/54, 0x7c/80, 0x186/8e) -> not + control_step-specific. +- BIGGER lever: 35/165 insns (21%) are str/ldr [sp] data spills (+14 mov rX,rY) -> excess + spilling, ~70 cyc estimate, plausibly a large slice of the 389-cyc gap to LLVM-LTO (471). + Recommended spill-reduction/regalloc as #1 priority, flag-fold as #2. Posted to #209 + (comment 4698894095) with honest scope: static counts from real object, cycle figures are + ESTIMATES, kill-criterion = re-measure on-silicon when a release lands. +CAUGHT a misattribution risk first: my initial shim-only build still had `bl decide` (not the +measured shape) -> rebuilt the real dissolved form before analyzing. Did not present shim-only +numbers as the headline. + +## UPDATE 2026-06-13 17:3x — synth#331 ANSWERED by maintainer -> delivered committed repro (jess#28) + +synth-side loop confirmed #331 is a real high-priority silent miscompile; ruled out (a) static +frame-layout overlap and (b) the i64-pool result-park by code-reading; reproduced the SHAPE but +NOT the collision (register-pressure-dependent) -> asked for the failing module in jess. +DELIVERED: rebuilt the dissolved k_mutex_unlock fresh on v0.11.40 (clang->wasm-ld+FFI staticlib-> +loom inline->synth --native-pointer-abi), CONFIRMED the collision still reproduces (identical +signature, offsets rel body-start 0x138: arg0 home [sp,#0x24]@+0x8, clobbered by unpend result +@+0x13a, no-waiter reload @+0x1e2 -> lock_count store misses). Committed to pulseengine/jess +repro/synth-331/ (PR #28): dissolved.wasm + wat + FAILING.o + shim + README (repro cmd, annotated +collision, expected/actual, silicon symptom, kill-criterion). Replied on #331 (comment 4698973255) +pinpointing the gap their ruling-out leaves: the result is parked on arg0's #204 PARAM-HOME slot +(not an i64-pool slot) under R4-R8 pressure -> param-home HashMap slot handed out as spill dest. +Agreed interim = exhaustion-Err skip; +1 on VCR-RA-003 v-next slot-non-aliasing validation. +Mutex cycle number (ref 124) still gated on the fix; clock reset (maintainer engaged). + +## UPDATE 2026-06-13 15:5x — expand/measure: control_step silicon RE-MEASURED at v0.11.40 + +No release (v0.11.40/v1.1.13). 4h N/A (synth 0h25m post-#331-reply; loom 3h42m). #331/#209 no +new response. Pushed the measure thread (hardware, not guess): rebuilt control_step-microbench at +the CURRENT toolchain, flashed G474RE, captured: + SELFCHECK 2165333 OK ; E,control_step,synth=151,native=67 = 2.25x (reproducible x2 boots) +-> down from 158 (v0.11.34) = ~3% codegen improvement 0.11.34->0.11.40, functionally correct. +Confirms the 151 I used in the #209 flag-fold analysis is the CURRENT on-silicon truth (not an +estimate) -> hardware-locked the "before" baseline for the #209 kill-criterion (target ~127). +Wrote RESULT-2026-06-13-g474re.txt, refreshed RESULTS-SUMMARY footnote §, posted baseline-lock to #209. + +## UPDATE 2026-06-13 16:1x — loom#142 still-reproduces confirmation + flat_flight silicon refresh + +No release. synth 0h55m. loom 4h12m (over 4h) BUT reminder_issue_open non-null -> per rule, no new +reminder issue; responded on the open channel instead. Confirmed loom#142 STILL reproduces on the +LATEST release v1.1.13: measured assets across v1.1.10-13 = compliance-report tarball only, NO loom +binary -> release-build-fails root cause unaddressed (#198 build-from-tag fix didn't touch the +release-artifact path). Re-commented on #142 (4699120397) with the asset table + kill-criterion; +not blocking gale (we build loom from source). + +Measure thread: re-measured flat_flight on G474RE at v0.11.40 = 241/103 = 2.34x, SELFCHECK +0x07fdf307 OK -> STABLE vs v0.11.35 (241), down from 262 (v0.11.30). Wrote RESULT-2026-06-13-v0.11.40, +refreshed RESULTS-SUMMARY ‡ footnote. Current-toolchain silicon picture now: control_step 151 (was 156), +flat_flight 241 (stable). Both functionally correct on v0.11.40. + +## UPDATE 2026-06-13 17:0x — 🎯 MUTEX UNBLOCKED & MEASURED: synth#331 fix verified on silicon + +synth#331 FIXED (PR#333/681f0bf), shipped as v0.11.41 release commit on main (GH Release not +published yet; gh release list still shows v0.11.40). Built synth 0.11.41 FROM MAIN (cargo build, +31s) and ran the long-blocked mutex re-measurement: +- DISASM: collision gone. arg0 home moved to [sp,#0x68], written ONCE (never re-clobbered); unpend + result parks on DISTINCT [sp,#0x28]; no-waiter lock_count=0 store (0x31a-0x326) reloads the + un-clobbered mutex base -> CORRECT. (area_reserved guard fix, exactly as diagnosed.) +- SILICON (G474RE): SELFCHECK k_mutex_unlock rc=0 owner=0 OK (no deadlock!); E,k_mutex_unlock,cyc=501. +- FIRST mutex wasm-cross-LTO number: 501/124 native = 4.04x — WORST ratio in suite. Cause: 86/269 + insns (31%) are [sp] spills (vs sem 21%, control_step 5%) -> spill density tracks the ratio. +Posted: #331 silicon-verified close (4699204002) closing the kill-criterion; #209 mutex spill +evidence (4699204055, the spill%-vs-ratio table) reinforcing spill-reduction as #1 lever. +RESULT-2026-06-13-v0.11.41.txt written, RESULTS-SUMMARY mutex row 501. The long-self-owed mutex +deliverable is DONE. Next: re-measure on the published v0.11.41 GH release when it lands (sanity); +push synth on the spill-reduction pass -> re-measure mutex (best test case). + +## UPDATE 2026-06-13 17:3x — v0.11.41 PUBLISHED + installed + body-of-work regression-clean + +synth v0.11.41 published (17:18) -> installed to ~/.cargo/bin (was 0.11.40), reset clock. Tested +against the full body of work on the official release: +- testbed run_testbed.sh: ALL GREEN (12 OK + u64 3-way lane 4/4), no skip/exhaustion. +- sem: rebuilt .o = byte-structurally IDENTICAL to 0.11.40 (540B, 4 funcs 20/230/6/284, 165 insns, + 35 spills/21%) -> #331 fix (has_i64==false path) doesn't touch sem (has_i64==true) -> 860 HOLDS. +- control_step: rebuilt = IDENTICAL (354B, 113 insns) -> 151 HOLDS. +- flat_flight: testbed-green (functional) -> 241 HOLDS. +- mutex: 501 (FIXED, was deadlock <=0.11.40). +=> v0.11.41 regression-clean AND fixes the mutex. CONSOLIDATED current-toolchain silicon picture + (synth 0.11.41 + loom 1.1.13, G474RE): + k_sem_give 860 / 471 LLVM-LTO = 1.82x + k_mutex_unlock 501 / 124 native = 4.04x (NEW; worst ratio, 31% spill) + control_step 151 / 67 = 2.25x + flat_flight 241 / 103 = 2.34x +loom clock: 5h12m but reminder channel non-null + already responded #142 -> no new reminder. +NEXT expand frontier (queued, multi-firing): promote mutex to a shippable wasm module (the sem #59 +pattern: build-wasm-dist.sh + Kconfig + release-wasm.yml) now that it works. Optimize thread (#209) +comprehensive + awaiting maintainer (flag-fold + spill-reduction, 3-pt spill%-vs-ratio evidence, hw baselines). + +## UPDATE 2026-06-13 17:5x — expand: testbed now covers kernel primitives (sem+mutex) + #331 guard + +No release (v0.11.41 latest). synth 0h29m; loom 5h42m (channel non-null + responded #142 -> no +reminder). #209 VCR-SEL-004/VCR-RA accepted, no PR yet -> passive (I'm the on-silicon gate). +EXPAND step: run_testbed.sh covered only the 4 algos + u64 lane; the kernel primitives (where +#331 lived) were NOT in per-release validation. Added primitives_codegen_check.sh (wired into +run_testbed.sh): for sem+mutex via the dist recipe -> compiles (no exhaustion-skip) + seam folded +(no bl decide reloc) + mutex arg0-home spill slot WRITE-ONCE = the #331 collision signature +(v0.11.40 wrote [sp,#0x24] twice — entry + unpend-result park; fixed v0.11.41 writes [sp,#0x68] +once). GREEN on v0.11.41. Now every synth release I test auto-checks both primitives' codegen +health + guards the #331 fix in OUR consumption (complements the synth-side jess fixture). + +## UPDATE 2026-06-13 20:3x — expand: Phase-5 macro bench re-measured on v0.11.41 (the bigger example) + +No release (v0.11.41 latest). synth 1h0m; loom 6h12m (channel non-null + responded #142 -> no +reminder). #209 VCR-SEL-004/VCR-RA accepted, no PR yet (open synth PRs all dependabot) -> passive. +EXPAND step (the mandate's "bigger example"): rebuilt + reflashed the flight_control Phase-5 macro +bench (GALE_FC_WASM_LTO=ON, 5 primitives on 100Hz loop) on v0.11.41 + measured on G474RE silicon: +- full 5-step sweep, NO FAULT; in-bench algo = 157 cyc, perfectly stable (min=med=max, n=9). +- = native 141 (gcc, synth-independent) -> 1.11x, ~11% in-context overhead -> UNCHANGED from + v0.11.30. The composed-context result holds on the post-#331 toolchain. (Measured wasm side on + hw; native carried forward — gcc -O2, unaffected by synth version.) +Wrote runs/RESULT-2026-06-13-v0.11.41.txt, refreshed RESULTS-SUMMARY Phase-5 paragraph. The bigger +example is validated current. Net current-toolchain picture stable: sem 860, mutex 501, +control_step 151, flat_flight 241, macro-bench algo 157/1.11x. + +## UPDATE 2026-06-13 21:1x — EXPAND: shippable mutex wasm-cross-LTO module -> gale PR #60 + +No release (v0.11.41 latest). synth 1h30m; loom 6h43m (channel non-null -> no reminder). #209 +VCR-SEL-004/VCR-RA accepted, no PR yet (maintainer confirmed VCR-RA-002 still `proposed` on #242) +-> passive, I'm the on-silicon gate. EXPAND step: promoted the silicon-validated mutex to a +shippable module mirroring sem #59 (unblocked by the v0.11.41 #331 fix). gale PR #60: +- zephyr/wasm/mutex_unlock_shim.c (production, faithful k_mutex layout) +- zephyr/wasm/gale_wasm_mutex_tramp.S (r11=0 native-pointer trampoline) +- scripts/build-wasm-dist.sh refactored -> build_module() helper, emits BOTH sem+mutex + manifest. +Verified: valid ET_REL mutex .o (body global, decide localized, imports->gale_w_*, no leftover +un-renamed), #331 signature absent (arg0 home #0x68 write-once), primitives lane GREEN, first +silicon 501 cyc. Follow-up PR: Kconfig CONFIG_GALE_WASM_LTO_MUTEX + CMakeLists consume + release.yml +attach. PR #60 pending CI+review (gale main protected). + +## UPDATE 2026-06-13 21:5x — EXPAND: completed mutex module (PR #60) + caught 2 real bugs by building + +No release. synth 1h59m; loom 7h12m (channel non-null -> no reminder). #209 no VCR PR yet (passive). +PR #60 CI: MERGEABLE, no failures (UNSTABLE = qemu matrix still running). Completed #60 from +build-pipeline-only into the FULL mutex module (consumption wiring mirroring sem): gale_mutex.c +#ifndef guard, Kconfig CONFIG_GALE_WASM_LTO_MUTEX, CMakeLists consume block, release.yml name. +Verified by BUILDING tests/kernel/mutex/mutex_api on nucleo_g474re — caught TWO real bugs assuming +would have shipped: + 1. func_N collision: sem.o & mutex.o each export synth's internal func_7/func_8 as GLOBAL -> + multiple-definition at final link when both modules on (#59 never hit, sem shipped alone). + Fixed: build-wasm-dist.sh exports ONLY the body (objcopy --keep-global-symbol), localizing + decide + func_N. Verified both-on links. + 2. Kconfig mis-gate: GALE_WASM_LTO_MUTEX landed inside `if GALE_KERNEL_SEM` -> unreachable w/o + sem kernel. Fixed: moved under GALE_KERNEL_MUTEX (depends on). Verified with SEM kernel OFF + + mutex wasm ON: .config accepts CONFIG_GALE_WASM_LTO_MUTEX=y, links (elf OK). +Both dedup-guard branches (sem-on / sem-off) exercised. PR #60 updated to "complete module". +Consumption verified: native unlock compiled out, synth_k_mutex_unlock_body + tramp linked, 501 cyc. + +## UPDATE 2026-06-13 20:1x — PR #60 mutex module FAULTS in full mutex_api (silicon) -> draft + +No release. synth 2h29m; loom 7h42m (no reminder). #209 no VCR PR (passive). Ran the REAL consume +path (not just link): tests/kernel/mutex/mutex_api on G474RE w/ CONFIG_GALE_WASM_LTO_MUTEX=y -> +USAGE FAULT on test_complex_inversion. Pinned: faulting insn body+0xc = 0xfac8 0100 = UNDEFINED; +working body has `movw r1,#0` (R_ARM_MOVW_ABS_NC __synth_globals). The mutex dissolved body refs +wasm STATICS (__synth_globals @.data+0x10008, __synth_wasm_data) via MOVW_ABS/MOVT_ABS relocs + a +~64KB .data section; the Zephyr link corrupts those movw->undefined. Localized: + - SEM .o has ZERO MOVW_ABS relocs (no wasm statics) -> #59 works in-kernel, mutex doesn't. + - No-waiter microbench links the SAME .o clean (501 cyc) -> .o fine; Zephyr-link consume path + mis-applies the relocs (flag/placement of 64KB .data, e.g. --no-relax). +Converted PR #60 -> DRAFT, posted characterization (comment 4699667490). The build-pipeline+shim +parts sound; consumption of a wasm-statics-bearing module is the gap. Also 64KB .data on 128KB RAM +is itself wrong (synth emits full linmem; decide uses little) -> raise synth-side separately. +KEY: caught by running the FULL test on hardware — link-only + no-waiter microbench both passed and +masked it. Owed next: root-cause the MOVW_ABS corruption (linker flag vs synth reloc) + the 64KB .data. + +## UPDATE 2026-06-13 20:4x — PR#60 mutex fault: ruled out objcopy + synth-reloc; it's link-context/64KB-.data + +No release. synth 3h0m; loom 8h12m (no reminder). #209 no response. Owed root-cause advanced: + - RULED OUT my objcopy change: --keep-global-symbol vs --localize-symbol -> MOVW_ABS/MOVT_ABS + reloc tables + .data size BYTE-IDENTICAL. Not the func_N-dedup objcopy. + - RULED OUT malformed synth reloc: the no-waiter microbench links the SAME .o and executes + body+0xc EVERY call without faulting -> that movw __synth_globals is VALID when linked there. + An undefined insn would fault unconditionally. So synth's reloc is well-formed. + => Corruption is LINK-CONTEXT-specific: mutex_api Zephyr image's MOVW_ABS_NC __synth_globals + application yields 0xfac8 (undefined); microbench image links the identical reloc fine. + Distinguishing factor = the ~64KB .data (full wasm linmem, __synth_globals @.data+0x10008) + and where it lands in the larger image. +DEEPER LEVER (the real fix): the dissolved object shouldn't carry 64KB wasm linmem for a decide +using a few constants — that's both the abs-reloc source AND a non-starter on 128KB RAM. Trimming +emitted linmem to what the decide references (synth-side) removes the reloc shape (like sem, which +has none). Posted to PR#60 (4699721494); held draft. Owed: raise the 64KB-linmem with synth + +the bfd/.data-placement angle. + +## UPDATE 2026-06-13 21:1x — PR#60 ROOT CAUSE pinned: decide struct-return -> sret/linmem (fix = pack u64 like sem) + +No release. synth 3h30m; loom 8h42m (no reminder). #209 no response. Definitively root-caused the +PR#60 mutex link-corruption to the DECIDE RETURN ABI: + - gale_k_mutex_unlock_decide returns a 12-byte struct {ret,action,new_lock_count} -> clang/wasm32 + lowers via SRET -> wasm needs a linmem stack frame: (memory 2) + (global $__stack_pointer + i32.const 65536), 12 mem ops. synth emits that as the 64KB .data (__synth_wasm_data) + + __synth_globals (stack ptr) -> MOVW_ABS relocs the Zephyr link mangles -> undefined insn -> fault. + - gale_k_sem_give_decide returns PACKED u64 -> (param i32 i32 i32)(result i64), register return, + ZERO MOVW_ABS, no linmem. That's why sem is a clean drop-in and mutex isn't. +FIX (gale-side, mirrors sem): pack gale_k_mutex_unlock_decide's return into a u64 (no struct) -> +no sret -> no 64KB linmem -> no abs-relocs -> drop-in like sem. Touches FFI decide + Verus proof + +wasm shim decode + native gale_mutex.c decode. Posted to PR#60 (4699802546). This is the unblock. +Also kills the 64KB-RAM cost (non-starter on 128KB). PR#60 held draft until the decide is repacked. + +## UPDATE 2026-06-13 22:0x — PR#60: u64-repack hypothesis TESTED on scratch -> promising-but-partial (corrected) + +No release. synth 4h0m (reminder channels open, VCR maintainer-owned -> no nudge); loom 9h12m (no +reminder). Owed item: implement the packed-u64 mutex decide. Before committing, prototyped FFI+shim +repack on SCRATCH + rebuilt the wasm object to TEST the "drop-in like sem" claim. RESULT (corrected +my over-claim): + - Repack REMOVED all __synth_globals relocs (the sret/stack-pointer frame). The faulting body+0xc + movw was __synth_globals -> that specific reloc class is eliminated. Real progress. + - BUT 64KB .data + 6 __synth_wasm_data MOVW_ABS relocs PERSIST in the body (MOVW_ABS 10->6, not 0); + wasm still declares (memory 2)+(global $__stack_pointer). So NOT drop-in like sem (sem=0 such relocs). + => u64 ABI is necessary-not-sufficient. Reverted scratch (incomplete: breaks native gale_mutex.c). + Posted correction to PR#60 (4699931960). The deeper issue = synth emitting full wasm linmem + + __synth_wasm_data refs for a body touching few bytes; trimming that (synth-side) is the real + sem-shape fix. The full u64-repack (FFI+6 kani harnesses+header+native+tests, re-verified + + SILICON mutex_api re-test) remains worth doing but must be CONFIRMED on hardware, not assumed. +DISCIPLINE: tested the fix at artifact level before committing -> caught the over-claim. PR#60 draft. + +## UPDATE 2026-06-13 22:2x — filed synth#345 (mutex-module fix lever) + issue-hunt pass + +No release. synth 4h44m / loom 9h56m (both reminder channels non-null -> no reminder). +ISSUE-HUNT: synth#313 CLOSED (if/else-result fix, ARM, v0.11.41 — aligned, our bodies verified); +synth#343 NEW (rv32 split of #313, synth-owned, passive); rivet#514 NEW (variant init/check/validate +schema disagreement) -> gale hits a RELATED manifestation (validate mis-parses artifacts/variants/ +bindings.yaml as a single-variant config -> benign 'missing field name' warning) -> posted honest +corroboration (4699969065). Watermark advanced. +WASM-OPT step3 (owed): filed synth#345 — dissolved --relocatable objects emit the full 64KB wasm +linmem .data + absolute MOVW relocs (root of PR#60's link corruption + 128KB-RAM non-starter); sem +has none (packed-u64 decide). Asks: emit only referenced data (.bss the zero-init linmem) + avoid +abs MOVW for kernel-linkable objects. Kill-criterion = mutex_api links+runs on G474RE no-fault, +.data bounded. Linked to PR#60 (held draft pending #345). This is the real sem-shape fix lever, +now tracked upstream w/ the maintainer. + +## UPDATE 2026-06-13 22:3x — controller_step re-measured v0.11.41 + flag-fold/spill PARTITION -> #209; sem headline 907->860 fix + +No release. synth 4h59m / loom 10h12m (channels non-null -> no reminder). #345/#209 no maintainer +response yet (passive). MEASURE: controller_step re-measured on G474RE at v0.11.41 = 150/61 = 2.46x, +SELFCHECK 0x05e33e81 MATCH (down from 169 @ v0.11.30). Body 99 insns: 6 flag-fold round-trips, only +3 spills -> FLAG-FOLD-dominated. Completes v0.11.41 silicon set. +DELIVERED to #209 (4699999657): the flag-fold-vs-spill PARTITION across all 4 bodies — + control_step 113i/6-fold/6-spill 151; controller 99i/6-fold/3-spill 150 -> FLAG-FOLD-bound (algos); + sem 165i/3-fold/35-spill(21%) 860; mutex 269i/5-fold/86-spill(31%) 501 -> SPILL-bound (primitives). + => VCR-SEL-004 owns the algos (isolated, low spill confound -> fast win, 151->~127/150->~126); + VCR-RA owns the primitives. Clean non-overlapping partition for sequencing. +HYGIENE: fixed the stale RESULTS-SUMMARY headline 907 -> 860 (the SOUND re-baseline: faithful v4.4.0 +shim, v0.11.37, n=148, drops=0, ADC bypassed; 907 was unsound NULL-wait_q/skewed-layout). Wrote +controller RESULT-2026-06-13-v0.11.41, updated controller footnote. + +## UPDATE 2026-06-13 23:0x — v0.11.42 installed + body-of-work regression-clean + +synth v0.11.42 RELEASED (PR#342, #313 if/else-with-result reconciliation fix) -> built from main +(ff4e843/7e02115), installed, clock reset. Tested against body of work: +- testbed run_testbed.sh: ALL GREEN (algos + u64 3-way lane + primitives lane), no regression. +- BYTE-DIFF (loop rule): sem 20/230/6/284 IDENTICAL to v0.11.41 (-> 860 holds); controller 296B + IDENTICAL (-> 150); control_step 354B/113insn IDENTICAL (-> 151). No thumb-2 codegen change for + our bodies -> NO reflash needed; silicon numbers hold. +- #342 (if/else-WITH-RESULT) is orthogonal to our select-based clamp/saturation bodies (they use + wasm `select`, not `if (result)`), so no codegen delta expected or observed. +=> v0.11.42 regression-clean. Current-toolchain silicon picture unchanged: sem 860, control_step + 151, controller 150, flat_flight 241, macro-algo 157/1.11x; mutex blocked on synth#345. +synth#345 (dissolved-object 64KB .data/.bss + PC-rel): BOTH asks accepted, maintainer building +.bss-first, next on-target after v0.11.42; I'm the on-silicon gate (re-test mutex_api when it lands). +#209 VCR-SEL-004/VCR-RA: partition delivered (algos=flag-fold, primitives=spill), awaiting PR. + +## UPDATE 2026-06-13 23:1x — expand-roadmap survey: FFI decide ABIs (5 u64-shaped / 51 struct) -> #345 blast radius + +No release (v0.11.42 latest). synth 0h28m / loom 11h12m (no reminder). #345/#209 no new maintainer +move (just my ack echo). All optimize threads maintainer-side. EXPAND step (non-blocked): surveyed +all 56 FFI *_decide return ABIs: + - 5 u64-shaped (no-sret, drop-in-ready): sem_give, sem_take, pipe_write, pipe_read, fatal. + - 51 struct-return (GaleXxxDecision): mutex/msgq/stack/timer/mem_slab/event/fifo/lifo/queue/mbox/ + poll/thread/work/... -> share the mutex sret->linmem path (#345 family). +=> #345 isn't mutex-specific: fixing it unblocks shipping the WHOLE struct-return family as wasm + modules. Posted blast-radius to #345 (honest scope: mutex confirmed, 50 others share ABI/likely + same, not individually verified). NEXT drop-in candidate = pipe (u64-shaped like sem; verify the + shim body avoids a linmem stack frame when built — mutex u64-repack showed shim complexity can + reintroduce linmem even with a u64 decide). Roadmap: #345 -> struct family; pipe -> shim-gated only. + +## UPDATE 2026-06-14 00:0x — maintainer registered #345 blast radius (building .bss-first); roadmap refined (pipe gate-2) + +No release (v0.11.42). synth clock reset on maintainer #345 reply (registered the 5-u64/51-struct +blast radius, ELEVATED #345 to "gates the whole struct-return family" = priority driver; plan +.bss-first then PC-rel; my G474RE mutex_api link-test = their kill-criterion; will ping on (1)). +loom 11h42m (no reminder). All threads maintainer-side. +ROADMAP REFINED (corrects last firing's "pipe is next drop-in"): drop-in-readiness needs TWO gates: + - gate1 = u64 decide (no sret): 5 pass (sem give/take, pipe write/read, fatal). + - gate2 = shim body stays in registers (no linmem stack frame): sem give PROVEN pass (ships clean); + mutex PROVEN fail (linmem even after u64-repack scratch — union decode + multi-field stores + + 5 calls); pipe LIKELY fail (ring-memcpy + dual reader/writer wait queues, hot path >= mutex + complexity, untested). So pipe is NOT a clean pre-#345 win. +=> #345 (.bss/PC-rel) is the UNIVERSAL unblock (fixes linmem regardless of gate2) -> unblocks ALL + 51 struct primitives AND the gate2-failing u64 ones (pipe). Only sem-family (give shipped, take + likely gate2-pass) is pre-#345-clean. No clean non-blocked module-build right now -> wait for #345 + (maintainer building, will ping) then build modules across the family. Did NOT 4th-comment #345 + (maintainer's "whole family" framing already captures it). + +## UPDATE 2026-06-14 00:4x — ruled out the --native-pointer-abi-drop workaround on hardware (#345) + +No release. Investigated the #345 linmem mechanism + tested a gale-side workaround. PINNED: +--native-pointer-abi is the SOLE trigger of the 64KB .data + MOVW_ABS (with flag: 65548B/11 relocs; +WITHOUT: 0B/0 relocs, sem-shaped). Both wasm modules declare (memory 2) identically -> the .data +emission is a synth WITH-flag-path decision, not the shim. HARDWARE-tested dropping the flag +(mutex_api on G474RE): + - WITH flag: test_complex_inversion USAGE FAULT (MOVW_ABS link-corruption). + - WITHOUT flag: test_complex_inversion PASSES (no .data to corrupt) BUT test_mutex_recursive MPU + FAULT (PC in body, r2=0x01030180 wild addr -> deref wrong without the flag; the synth#237 scenario). +=> Flag REQUIRED for correct host-pointer deref; dropping it trades link-corruption for deref-fault. + NO gale-side workaround -> #345 (.bss + PC-rel in the WITH-flag path) is the only correct route. + Posted to #345 (the with/without table). Validates the maintainer's scope. Re-test on (1) landing. + +## UPDATE 2026-06-14 01:1x — dry-ran the #345 harness on v0.11.42 (validated + bug re-confirmed) + +No release. synth 1h24m / loom 13h12m (no reminder). All threads maintainer-building. Dry-ran the +staged verify_mutex_module_silicon.sh on v0.11.42 (from feat/wasm-mutex-module): build -> flash -> +capture -> verdict all WORK end-to-end. Output: module shape .data=65548B / 11 MOVW_ABS (the +with-flag shape #345 fixes); mutex_api -> USAGE FAULT -> "KILL-CRITERION NOT MET: still reproduces". +=> (1) harness mechanics validated -> #345 ping = instant one-command verdict; (2) the mutex +link-corruption STILL reproduces on v0.11.42 (v0.11.42 was the if/else-result fix #313, NOT the +linmem fix) -> #345 still needed, not coincidentally resolved. No #345 comment (maintainer building +the fix; already 5 comments there). Harness ready for the ping. + +## UPDATE 2026-06-14 02:0x — sem_take VERIFIED sem-shaped (gate-2 pass) = next pre-#345 module + +No release. synth 1h54m / loom 13h42m (no reminder). All threads maintainer-building. EXPAND +(non-blocked): wrote a scratch sem_take shim (mirrors sem_give + the take hot path: spin_lock -> +u64 decide -> ACQUIRED/WOULD_BLOCK/z_pend_curr) and dissolved it -> .data=0, MOVW_ABS=0 = SEM-SHAPED +(gate-2 PASS). Notably the k_timeout_t (8-byte struct) BY-VALUE arg did NOT force linmem (clang +passed it in registers) -> refines the 2-gate model: struct-by-value ARGS are fine; only struct +RETURNS (sret) + complex-shim register-pressure trigger the linmem. +=> sem_take is a genuinely DROP-IN-READY next module (no #345 needed), proving the wasm surface CAN + expand pre-#345 for sem-family primitives. Pre-#345-buildable set: sem_give (shipped), sem_take + (verified ready), likely fatal. pipe fails gate-2 (complex hot path); mutex + 51 struct-decides + need #345. Building the full sem_take module (shim->dist->Kconfig->CMakeLists->measure) is a + queued increment (modest shipping value — give is the measured hot path; do it if take coverage + wanted). This firing = grounded gate-2 verification. + +## UPDATE 2026-06-14 03:0x — sem_take gate-2 RE-VERIFIED with faithful 2-arg decide (corrected prior error) + +No release (v0.11.42). synth 2h54m / loom 14h42m (no reminder). All threads maintainer-building. +Caught a correctness error: last firing's sem_take gate-2 scratch used a WRONG 3-arg decide +(count,limit,no_wait); the real FFI gale_k_sem_take_decide is 2-arg (count, is_no_wait) per +gale_sem.c. Re-verified with the FAITHFUL 2-arg shim (correct k_sem layout + the gale_sem.c take +hot path: spin_lock -> u64 decide -> ACQUIRED/WOULD_BLOCK/z_pend_curr): dissolved = .data=0, +MOVW_ABS=0, seam folded (0 decide relocs) = SEM-SHAPED. So sem_take IS faithfully drop-in-ready +(no #345). The shape result held across the signature fix (it's structural), but the build is now +faithful. Full sem_take module (gale/zephyr/wasm shim+tramp + dist + Kconfig + CMakeLists + +gale_sem.c guard + PR) remains a QUEUED increment — modest value (give is the measured hot path), +not opening a 2nd module PR while #60 is blocked + maintainer heads-down on #345/#209/#275. Build +it when take-coverage is wanted or post-#345 (when the whole struct family unblocks). + +## UPDATE 2026-06-14 04:5x — sem_take module precisely scoped (5 files incl shared wrapper); deferred w/ fuller scope + +No release (v0.11.42; gh release briefly net-timed-out, retried clean). synth 4h55m / loom 16h43m +(both >4h, reminder_open non-null, synth maintainer-active, loom#142 non-blocking+diagnosed -> no +reminder). No synth PR/activity. Scoped the sem_take module build (the one non-blocked, MERGEABLE +sem-shaped expand): requires (1) gale/zephyr/wasm/sem_take_shim.c [production, faithful 2-arg decide, +union {action;pad[3];new_count}], (2) gale_wasm_sem_take_tramp.S [r11=0 -> synth_k_sem_take_body], +(3) NEW gale_w_pend_curr wrapper in the SHARED gale_wasm_wrappers.c [z_pend_curr is take-specific, +not in existing wrappers], (4) build-wasm-dist build_module stanza, (5) Kconfig CONFIG_GALE_WASM_LTO_ +SEM_TAKE + CMakeLists consume + gale_sem.c take-guard. So it's a 5-file production change touching a +SHARED file, for modest value (give is the measured hot path). DEFERRED (consistent reasoning): not +spending a firing on modest-value multi-file production work touching shared wrappers while #345 is +mid-flight + #60 blocked. Turnkey scope recorded. Build when take-coverage wanted OR post-#345 +(family unblocks together -> batch the modules). sem_take drop-in-readiness already verified. + +## UPDATE 2026-06-14 06:5x — loom#142 FIXED (#216, diagnosis confirmed); rivet#518/#514 closed; gale follow-ups + +loom#142 CLOSED/COMPLETED — resolved in loom #216 (release.yml rewrite), EXACTLY the diagnosed root +cause (wasm32-wasip2 rayon/__wasi_init_tp link failure gated the `release` job). v1.1.13 NOW ships +per-OS loom binaries (aarch64/x86_64-darwin, x86_64-linux-gnu, windows + SHA256SUMS/cosign) — verified +live, where before it had only the compliance tarball. Posted consumer-confirmation (4700980365). +rivet#518 (colon-corruption/REQ-198) + #514 (variant-config schema) also CLOSED/COMPLETED (both gale +corroborated). GALE FOLLOW-UPS (low priority, non-urgent): (1) loom binaries now ship -> gale can +retire build-loom-from-source + consume the released binary (build-from-source works fine, optional); +(2) rivet 0.15.0 -> 0.16.0+ upgrade brings #518 dup-id-guard + (once tagged) #514 variant-schema fix +-> clears the benign bindings.yaml validate warning (validate is green, not urgent). synth #345 .bss +fix still building (no PR yet); harness staged. + +## UPDATE 2026-06-14 07:35 — synth 0.11.42 tested (no change for us); #345 STEP 1 landed (.bss), reflash HELD for step 2 + +**Step 1 of loop — synth v0.11.42 (the #313 if/else-result miscompile fix) vs our body of work:** +- Codegen lane (`primitives_codegen_check.sh`) GREEN on 0.11.42 (TRUE_EXIT=0, re-run w/o tail-pipe): + sem + mutex both compile + seam-folded; mutex arg0-home #0x68 WRITE-ONCE (#331 signature absent). +- `control_step` rebuilt on 0.11.42 = **354 bytes code size — byte-identical to the recorded + 0.11.40/41 baseline (354B / 113 insn)**. No thumb-2 codegen change → **151 cyc HOLDS, no reflash**. +- Rationale (measure-don't-guess): #313 only changes code that was *miscompiled*; control_step's + SELFCHECK was already correct (2165333==native) on 0.11.40, so it was never affected. 0.11.42 is a + no-op for our dissolved bodies. → step-1 satisfied without a gratuitous reflash. + +**synth#345 (the .bss/abs-reloc fix that blocks PR#60) — STEP 1 LANDED (synth PR #347, auto-merge):** +| section | before | after | +|---|---|---| +| `.data` | 65548 | **4** | +| `.bss` (NOBITS) | 0 | **65544** | + +The 64KB zero-init linmem reservation now rides SHT_NOBITS `.bss` (Zephyr loader zeroes it). BUT the +**22 MOVW/MOVT_ABS relocs are UNCHANGED** — those are the link-fragility that USAGE-FAULTed +`test_complex_inversion`. So **step 1 alone won't make `mutex_api` pass**; the no-fault result needs +**STEP 2 (PC-relative relocs)** — the next synth PR. Maintainer will **bundle a release so we +re-measure once BOTH land**. Per their explicit flag: **NOT doing a step-1-only reflash** (would just +hit the same fault). `verify_mutex_module_silicon.sh` stays staged; PR #60 stays draft-blocked. +#347 is not yet in a tagged release (0.11.42 = #313); will test when the bundled step-1+step-2 ships. + +## UPDATE 2026-06-14 08:07 — pipe is the 2nd clean u64-shaped drop-in (gate-2 VERIFIED, #345-independent) + +Expansion step: built the `k_pipe_write` shim and dissolved it (clang wasm32 → wasm-ld+ffi → +loom inline → synth 0.11.42 cortex-m4f, NO `--native-pointer-abi` — sem-class). Answers the +maintainer's open question (synth#345 blast-radius thread: "pipe is the next likely drop-in-ready +module … a complex shim body can still allocate a linmem frame; I'll verify pipe's when I build it"). + +**Gate-1 (decide ABI):** `gale_k_pipe_write_decide` + `_read_decide` both return packed `u64` +(`#[repr(C)] GalePipeWriteDecision{action:u8, actual_bytes:u32}` transmuted to u64, asserted ==8B). +No sret → no decide-forced linmem. Same shape as sem (one of the 5 u64 decides; the other 51 are +`#[repr(C)]`-struct → sret → linmem, gated on #345). + +**Gate-2 (shim body shape) — the new result:** despite a more complex 5-action body +(WRITE_OK / WAKE_READER / WRITE_PEND / ERROR_EPIPE / ERROR_ECANCELED) reading more state +(ring_buf used+size, flags, reader probe) than sem's 2-action body, the dissolved object is +**SEM-SHAPED**: +- `.text` 1290 B, **`.data` = 0** (no 64KB linmem blob) +- **0 `R_ARM_MOVW_ABS`/`MOVT_ABS`** (no link-fragility — the #345 fault signature is absent) +- **seam folded** (0 relocs to `gale_k_pipe_write_decide` — loom inlined it) +- 12 relocs = all import-call (THM_CALL to kernel APIs), resolved at Zephyr link — the sem pattern. + +→ **pipe's write body stays in registers; it's a clean drop-in, NOT blocked by synth#345.** sem + pipe +are now the two confirmed-clean u64 primitives; the 51 struct-return ones still wait on #345 step 2. + +**Wired into the permanent gate:** `primitives_codegen_check.sh` now has a `k_pipe_write` lane with +the gate-2 shape assertions (.data==0, abs-relocs==0, seam-folded). Lane GREEN on 0.11.42 +(TRUE_EXIT=0, re-run w/o tail-pipe). POC shim: `boards/nucleo_g474re/wasm_pipe_write_shim_poc.c`. +NOT silicon-measured yet (shape gate only); next step = a pipe microbench + reflash for a cycle number, +or promote to a full gale pipe module (PR, like #60) when pipe ships. gale main untouched this pass. + +## UPDATE 2026-06-14 08:33 — pipe_read gate-2 also clean → pipe verified clean BOTH directions + +Completed the static pipe verification (shipping pipe needs both directions): built the +`k_pipe_read` shim (mirror of write; `has_writer`, wakes a writer on WAKE_WRITER) and dissolved it +(synth 0.11.42, no `--native-pointer-abi`). Gate-2 **sem-shaped**: `.data=0`, 0 MOVW/MOVT_ABS, +seam folded. Added a `k_pipe_read` lane to `primitives_codegen_check.sh`; full lane GREEN +(sem_give, pipe_write, pipe_read, mutex_unlock — TRUE_EXIT=0, re-run w/o tail-pipe). POC shim: +`boards/nucleo_g474re/wasm_pipe_read_shim_poc.c`. So the clean-u64 partition now has **sem + pipe +(both directions)** statically verified drop-in-ready, #345-independent; the 51 struct-return decides +remain gated on #345 step 2. Did NOT re-comment on synth#345 (write result posted at 08:07; will +report pipe consolidated with a silicon number or at module-promotion). Board IS connected +(2× /dev/cu.usbmodem*, openocd present) → a pipe silicon microbench is feasible next, but a faithful +on-target pipe cycle measurement = building the production pipe module (override+tramp+CMake), which +is the "promote to gale module" step, not a one-firing probe. Shape gate is the drop-in criterion; +that's met for pipe. + +## UPDATE 2026-06-14 09:03 — sem_take gate-2 clean → sem primitive COMPLETE (give+take) for wasm-cross-LTO + +#59 ships only k_sem_give (the handoff half). Built the k_sem_take shim (the blocking-acquire half — +faithful z_impl_k_sem_take: count>0 acquire/count--; K_NO_WAIT → -EBUSY; else z_pend_curr; uses +k_spin_unlock not z_reschedule, unlike give) and dissolved it (synth 0.11.42, no --native-pointer-abi). +Gate-2 **sem-shaped**: `.data=0`, 0 MOVW/MOVT_ABS, seam folded (3 actions ACQUIRED/WOULD_BLOCK/PEND). +Added a `k_sem_take` lane; codegen gate now GREEN across **5 primitives** (sem_give, sem_take, +pipe_write, pipe_read, mutex_unlock — TRUE_EXIT=0, re-run w/o tail-pipe). POC shim: +`boards/nucleo_g474re/wasm_sem_take_shim_poc.c`. + +So the **sem primitive is now fully wasm-cross-LTO drop-in-verified (give + take)** — the v0.1.0 release +target's kernel surface dissolves cleanly. clean-u64 partition status: 4/5 of the maintainer's named +u64-shaped set verified clean (sem_give, sem_take, pipe_write, pipe_read); only `k_fatal` unchecked. +The 51 struct-return decides remain gated on synth#345 step 2. Did NOT re-comment on synth#345 (no +maintainer activity since my 08:11 pipe report; sem_take is gale-internal completion). Silicon cycle +numbers for take/pipe still pending the module-promotion step (shape is the drop-in gate; that's met). + +## UPDATE 2026-06-14 09:46 — #345 VERIFIED FIXED on silicon; new gale finding: mutex shim omits prio-inheritance + +synth **v0.11.43** (SHA-verified install) bundles #345 step1+step2. Rebuilt dissolved k_mutex_unlock: +reloc shape flipped — **MOVW/MOVT_ABS 22->0, R_ARM_ABS32 0->11, .data 65548->4, .bss 65536**. Ran the +staged kill-criterion (full mutex_api on G474RE, CONFIG_GALE_WASM_LTO_MUTEX=y, --native-pointer-abi): +- `test_complex_inversion` **PASS** (was USAGE FAULT) ; `test_mutex_recursive` **PASS** (was MPU FAULT). +- **#345 link-corruption fault is GONE — verified on hardware.** Posted the verdict to synth#345. + +BUT the link fault was masking a deeper bug: **`test_mutex_priority_inheritance` FAILS on the wasm-LTO +module (0.520s, fails fast) while PASSING on the native gale mutex (6.001s, full suite PASS)** — +measured both on G474RE (CONFIG_GALE_WASM_LTO_MUTEX=y vs =n). Localized: the dissolved +`mutex_unlock_shim.c` UNLOCKED path **omits `adjust_owner_prio(mutex, owner_orig_prio)` + `owner`/ +`owner_orig_prio` management** that the real z_impl_k_mutex_unlock does → unlocking thread keeps its +inherited prio boost. Filed **gale#62**. PR#60 stays draft — gated on gale#62 now, NOT on #345 (done). +Fix needs a gale_w_* wrapper for the priority-set (adjust_owner_prio is static in kernel/mutex.c). + +## UPDATE 2026-06-14 10:05 — gale#62 FIXED + verified on silicon → mutex module passes FULL suite + +Fixed the dissolved mutex_unlock shim's missing priority-inheritance restoration (gale#62). Added two +`gale_w_*` wrappers (k_thread opaque to the shim): `gale_w_adjust_thread_prio` (z_thread_prio_set if +changed) + `gale_w_thread_prio` (read base.prio). Shim UNLOCKED path now restores `cur` to +owner_orig_prio BEFORE handoff (mutex->owner still == cur there) + records new owner's orig prio. + +Verified on G474RE (synth v0.11.43, CONFIG_GALE_WASM_LTO_MUTEX=y), full upstream mutex_api: +- `test_mutex_priority_inheritance`: **FAIL (0.520s) → PASS (6.001s)** — matches native. +- `mutex_api` 4/4 + `mutex_api_1cpu` **5/5** PASS. **KILL-CRITERION PASS, no fault.** +- Module shape unchanged (.data=4, MOVW_ABS=0; prio wrappers add only import-call relocs). + +**The wasm-cross-LTO mutex module now passes the COMPLETE upstream mutex_api suite on silicon** — +both blockers resolved: synth#345 (link survivability, v0.11.43) + gale#62 (shim prio restoration). +Committed to feat/wasm-mutex-module (PR#60, "Closes #62"). PR#60 is silicon-verified-correct; next = +confirm CI green on the v0.11.43 toolchain, then flip draft→ready. mutex JOINS sem(give+take) + +pipe(rd/wr) as a verified-correct dissolved primitive (mutex now full-suite on HW, not just shape). + +## UPDATE 2026-06-14 11:05 — mutex_unlock re-measured on v0.11.43: 501→472 cyc (−5.8%), #209 still the lever + +PR#60 merged (mutex module in gale main). Re-measured k_mutex_unlock cycles on the current toolchain +(synth v0.11.43, remeasure_wasm_lto.sh, G474RE DWT min/200 uncontended): **472 cyc** (was 501 on +v0.11.41) — **−29 cyc / −5.8%** across 0.11.41→0.11.43 (#313 if/else-result fix v0.11.42 + #345 +.bss/PC-relative v0.11.43). SELFCHECK rc=0 owner=0 OK. Ratio vs native 124 = **3.81×** (was 4.04×). +Re-measured the dissolved body spill density on v0.11.43: **167 insns, 56 (34%) [sp] spills** (method: +objdump z_impl body isolation) — still ~a third spills, consistent with v0.11.41's ~31% → **synth#209 +(spill reduction) remains the dominant lever**, now the worst-ratio primitive in the suite. RESULTS +mutex line updated; RESULT-2026-06-14-g474re-v0.11.43.txt saved. Posted the updated #209 baseline. + +## UPDATE 2026-06-14 11:34 — sem .o byte-diff on v0.11.43: IDENTICAL → 860 holds (no reflash) + +Loop step-1 byte-diff of the sem .o on the current toolchain (synth v0.11.43, post #313+#345). Rebuilt +the dissolved sem_give .o: **Total 540 B, 4 funcs 20/230/6/284, z_impl_k_sem_give=284 B, seam-folded +(0 decide relocs)** — **byte-structurally IDENTICAL to the recorded 0.11.40 baseline (line ~1626: +540B, 20/230/6/284, 165 insns)**. So no thumb-2 codegen change for sem across 0.11.40→0.11.43 → +**k_sem_give handoff = 860 cyc HOLDS, no reflash needed**. (Caught a self-trap: an awk that isolated +only the z_impl body counted 83 insns and looked like a change vs the recorded "165" — but that 165 is +a different/total count; the authoritative per-function byte sizes 20/230/6/284 match exactly, so the +.o is identical. Verified against the recorded sizes before any reflash — measure, don't guess.) + +Current-toolchain (v0.11.43) silicon perf pair: **sem_give 860 (stable, byte-identical), mutex_unlock +472 (re-measured, −5.8% from 501)**. The #313 if/else-result fix did NOT alter sem's give/wake branch +codegen (byte-identical confirms it). Spill density unchanged (same bytes) → synth#209 still the lever. + +## UPDATE 2026-06-14 12:03 — k_fatal gate-2 clean → u64-clean partition 5/5 COMPLETE + +Built the k_fatal shim (dissolved k_sys_fatal_error_handler policy: gale_k_fatal_decide(reason,is_isr, +test_mode)->u64, actions ABORT_THREAD/HALT/IGNORE; esf not deref'd → sem-class, no --native-pointer-abi). +Dissolved on synth v0.11.43: gate-2 **sem-shaped** — .text 524B, **.data=0, 0 MOVW/MOVT_ABS, seam folded**. +Added a `k_fatal` lane to primitives_codegen_check.sh; full lane GREEN across **6 primitives** (sem_give, +sem_take, pipe_write, pipe_read, fatal, mutex_unlock — TRUE_EXIT=0). POC: wasm_fatal_shim_poc.c. + +**The maintainer's u64-shaped clean decide partition is now 5/5 statically verified:** sem_give, sem_take, +pipe_write, pipe_read, fatal — all sem-shaped (.data=0, 0 abs-relocs, seam-folded), drop-in-ready, +#345-independent. The struct-return family (51, incl mutex) is separately UNBLOCKED now that #345 is +fixed+merged (mutex proved it end-to-end on silicon: full mutex_api 9/9). So the wasm-cross-LTO surface +status: u64-clean set fully verified (shape); mutex shipped (full-suite-correct on HW); the rest of the +struct-return family is the open expansion frontier (each needs a faithful shim + correctness pass like +gale#62's priority-inheritance work). + +## UPDATE 2026-06-14 12:33 — full v0.11.43 byte-diff sweep: perf table confirmed CURRENT + +Loop step-1 byte-diff sweep of the algo microbenches on the merged toolchain (synth v0.11.43): +- control_step = **354B** → IDENTICAL (151 cyc holds) +- controller = **296B** → IDENTICAL (150 cyc holds) +- flat_flight = **526B** → IDENTICAL to v0.11.35/40 baseline (241 cyc holds; RESULT note "560→526B" @v0.11.35) +- sem_give = 540B (20/230/6/284) → IDENTICAL (860 holds, confirmed 11:34) + +So **the entire perf table is current on v0.11.43 with no reflash** — every value-in/value-out algo + +sem is byte-identical; the #313 if/else-result fix + #345 reloc change touched NONE of them. The only +primitive that moved is **mutex_unlock: 501 (v0.11.41) → 472 (v0.11.43)** (re-measured on HW). Coherent +current-toolchain (v0.11.43 + loom 1.1.13) silicon table: + +| primitive | wasm-cross-LTO | native/ref | LLVM-LTO | ratio | +|---|---|---|---|---| +| k_sem_give handoff | 860 | — | 471 | 1.83× vs LLVM-LTO | +| k_mutex_unlock | 472 | 124 | — | 3.81× (worst; 34% [sp] spills → #209) | +| control_step | 151 | 67 | — | 2.25× | +| controller_step | 150 | 61 | — | 2.46× | +| flat_flight | 241 | 103 | — | 2.34× | +| flight_control macro algo | 157 | 141 | — | 1.11× (in-context) | + +#209 (regalloc spill reduction) remains the single retargetable lever; I'm the on-silicon gate (baselines above). + +## UPDATE 2026-06-14 13:06 — struct-return family NOT uniformly clean: stack_push hits synth#350 (ARM ADD-imm bug) + +Tried k_stack_push as a 2nd struct-return primitive (to substantiate "#345 generalizes the family" + +de-risk the gale#63 component epic). Built the faithful shim, dissolved, and synth FAILED: +`gale_k_stack_push_decide` → "ARM encoding failed: ADD immediate too large for single instruction"; +body then skipped ("branch-resolve size probe"). **Nothing emitted — empty object.** + +**Discipline catch:** the empty object's zero .data/.bss/relocs FIRST looked "sem-shaped clean" in my +ad-hoc shape check — but re-running with full synth output showed `no functions compiled (2 skipped)`. +An empty object is not a clean object. (The codegen lane's build_primitive guards this via the +"skipping function" grep → rc=2; my inline check didn't, so I verified before recording. Never read a +zero-reloc object as clean without confirming the compile succeeded.) + +**Filed synth#350.** Characterized: repros on 0.11.42 AND 0.11.43 (pre-existing, not a regression), +with AND without --native-pointer-abi (flag not implicated) → an ARM-backend bug lowering an +out-of-range ADD immediate. Frozen repro: `wasm-testbed/repro-synth-stack-add-imm/` (stack_push.loom.wasm ++ shim + ERROR). **Refines the partition:** it's NOT simply "5 u64 clean / 51 struct-return need #345" — +some struct-return decides (stack_push) additionally hit ARM-encoding bugs that block them entirely. +Verified-clean set stays: sem give+take, pipe rd+wr, fatal (u64) + mutex_unlock (struct-return, shipped). +stack_push BLOCKED on synth#350. Codegen lane unchanged (stays 6-green; stack_push not added until #350 fixed). + +## UPDATE 2026-06-14 13:33 — synth#350 blast radius: stack + msgq only (bounded-buffer decides) + +Decide-only survey (no shims; wasm-ld --export each decide + --gc-sections -> loom -> synth 0.11.43): +- ❌ ADD-imm (#350): stack_push, stack_pop, msgq_put, msgq_get (the bounded-buffer arithmetic ones) +- ✓ OK: sem_give(256B), mutex_unlock(308B), event_post(18B)/wait(110B), queue_insert(14B)/get(30B), mbox_put/get(30B) +synth#350 is NARROW — stack+msgq, not the whole struct-return family. Likely root: a capacity/byte-span +constant (msgq max_msgs*msg_size, stack top-base span) overflowing Thumb-2 modified-immediate range. +Posted the table + bisect suggestion (stack_pop = smallest failing decide) to synth#350. +Refined drop-in map: u64 set (sem/pipe/fatal) + mutex + event/queue/mbox = synth-compilable; stack+msgq +blocked on #350. (Note: the OK struct-return decides still need shim+gate-2+silicon to be true drop-ins; +this survey only establishes synth CAN compile them.) + +## UPDATE 2026-06-14 14:33 — synth#350 fix landing (PR#351 merged + #352 follow-up); struct-return map clarified + +synth#350 fix: **PR#351 MERGED** (lower out-of-range ADD #imm to MOVW/MOVT+ADD); **PR#352 OPEN** — +fix-forward for a CI fuzz red #351 introduced (`debug_assert!(scratch != rn_bits)` R12-alias when +rd==rn==R12). So the kill-criterion release must bundle **#351 AND #352** (not bare #351; #351-only has +the R12-alias follow-up bug). No v0.11.44 tag yet. Staged re-survey (resurvey_struct_return_decides.sh) +ready; will run on the bundled release. Did NOT build the stale local ../synth clone to #351-only — +testing an incomplete fix isn't a clean measurement. + +**Struct-return drop-in map clarified (sret threshold):** only decides returning a struct >8 bytes hit +the sret→wasm-linmem path: +- ≥12B sret: **mutex_unlock** (GaleMutexUnlockDecision 12B) — VERIFIED+shipped; **stack** (12B) + + **msgq** — #350-gated (ADD-imm, fix landing). +- ≤8B register-return (NOT sret, trivially clean): event_post (GaleEventPostDecision = u32, 4B), + queue/mbox (small) — no linmem path, no value in shimming for the drop-in question. +So the meaningful sret expansion is mutex (done) + stack/msgq (#350-gated); the small-struct primitives +need no separate verification. No high-value non-#350-gated primitive step remains — surface is at a +verified resting state pending the #350 release (then stack/msgq) and synth#209 (spill). + +## UPDATE 2026-06-14 15:0x — synth#350 VERIFIED FIXED on v0.11.44; stack/msgq now compile but hit synth#354 (64KB .data) + +v0.11.44 published (SHA-verified install). Ran staged resurvey_struct_return_decides.sh → **GREEN**: +stack_push/pop + msgq_put/get all COMPILE now (were ADD-imm FAIL); controls OK. **#350 fix verified on +the real gale decides.** No regression: 6-primitive codegen lane GREEN on v0.11.44, sem .o byte-identical +(540B). Reported verified-fixed to synth#350 (closed loop). + +NEW finding — **stack_push compiles but dissolves to a 64KB PROGBITS .data** (filed synth#354). From the +loom.wasm: a 12-byte .rodata init segment at linmem offset 65536 (`\f4\ff\ff\ff` = -12 = -ENOMEM, the +stack-full const) drags the `[0,65536)` zero gap into PROGBITS .data instead of .bss. #345 handled +pure-zero-init (mutex → all .bss); this is the mixed case (high-offset init segment). Link-survivable +(ABS32=6, MOVW_ABS=0, seam-folded) but MCU-unshippable (64KB flash). Fix = per-region .data/.bss split. +So: #350 (compile) cleared → #354 (64KB .data) is the NEXT blocker for shipping stack/msgq as wasm-LTO +modules. mutex remains the only shippable struct-return primitive; stack/msgq gated on #354 now. +Updated struct-return map: stack/msgq COMPILE (v0.11.44) but not shippable until #354. + +## UPDATE 2026-06-14 15:33 — synth#354 blast radius: stack + msgq (2-page linmem w/ high-offset const); msgq at decide level + +Decide-only survey (v0.11.44, --native-pointer-abi): mutex_unlock = 1 linmem page, .data=0 (clean). +stack_push/pop = 2 pages, decide-alone .data=0 but FULL shim 65552B. msgq_put/get = 2 pages, decide-alone +ALREADY .data=65556 (64KB). Pattern: bounded-buffer decides request 2 linmem pages (128KB) with a +.rodata const at offset 65536 -> zero-fill gap -> 64KB PROGBITS .data (#354). #354 gates stack+msgq (same +set as #350); mutex/event/queue/mbox unaffected. Posted the table to synth#354. msgq is worse (decide-level). + +## UPDATE 2026-06-14 16:3x — BIGGER TESTBED: flight_control bench now runs dissolved algo + dissolved sem on G474RE + +Expanded the flight_control bench (Phase 5) into a composed dissolved testbed: built the shipped sem +module (build-wasm-dist.sh -> gale-wasm-sem-f5fa4cd-cortex-m4f.o, synth 0.11.44) and west-built the bench +with **GALE_FC_WASM_LTO=ON (algo) + CONFIG_GALE_WASM_LTO_SEM=y (dissolved sem module)** + +-DGALE_WASM_LTO_OBJ_DIR. Builds clean (zephyr.elf 722KB; only benign .meld_import_table orphan-section +warnings). Flashed G474RE, ran the full 5-step sweep. + +**Functionally equivalent to native (measure-don't-guess: ran the native-sem comparison to interpret):** +| | native-sem | dissolved-sem | +|---|---|---| +| sweep pattern (drain_timeouts steps 1/2/3/5; 2/3/4 emit) | — | IDENTICAL | +| dissolved algo | 157 | 157 | +| in-bench handoff | 1374 | **1661 (+287, +21%)** | + +The drain_timeouts are **bench-inherent** (present in BOTH variants, same steps) — NOT a dissolved-sem +regression. So the composed dissolved testbed (algo+sem) builds + boots + runs the full sweep on real +silicon, no fault, functionally == native. **Measured composed-context cost of dissolving sem_give = ++287 cyc / +21% on the handoff** (1374->1661) — relevant to synth#209 (spill reduction is what would +shrink this). Next: add the dissolved mutex module too (CONFIG_GALE_WASM_LTO_MUTEX=y) for algo+sem+mutex. + +## UPDATE 2026-06-14 17:0x — BIGGER TESTBED complete: flight_control runs algo+sem+MUTEX all dissolved on G474RE + +Extended the composed dissolved testbed to all three: GALE_FC_WASM_LTO=ON (algo) + CONFIG_GALE_WASM_LTO_SEM=y ++ CONFIG_GALE_WASM_LTO_MUTEX=y. Built sem + mutex modules into OBJ_DIR (VER 4654734), west-built (clean; +benign .meld_import_table orphan warnings), flashed G474RE. **Full 5-step sweep, NO FAULT** — all three +primitives dissolved, running composed. In-bench costs (E-row algo/handoff/t_lock): +| in-bench | native | dissolved | +|---|---|---| +| handoff (sem) | 1374 | ~1719 | +| t_lock (mutex) | 486 | **887 (+401, +82%)** | +| algo | 157 | ~146-157 (in-bench variance; isolated control_step 151 unchanged) | +Dissolved mutex's +82% in-bench lock cost tracks its worst-in-suite isolated ratio (3.81x); the +401/+287 +deltas are exactly what synth#209 (spill reduction) would shrink. drain_timeouts bench-inherent. The +"bigger testbed for functionality + optimization" is now fully composed (algo+sem+mutex) on real silicon. + +NOTE: local gale main was STALE (f5fa4cd, pre-#60/#61) — `git pull --ff-only` synced it to 4654734 +(mutex shim + CMake mutex consume + nightly fix). Surfaced by the missing mutex_unlock_shim.c; fixed. + +## UPDATE 2026-06-14 18:0x — synth#354 VERIFIED FIXED on v0.11.45 → stack+msgq SHIPPABLE; all 4 synth bugs cleared + +v0.11.45 published (SHA-verified, 90s). Ran staged DUAL-gate re-survey → **GREEN (EXIT=0)**: +- #350 (compile): stack_push/pop + msgq_put/get all OK. +- #354 (.data bounded): msgq .data 65556→**20**, stack_push shim 65552→**16** — per-region .bss split works, + 64KB blob gone (only the -ENOMEM/-EAGAIN init consts in .data; zero gap in .bss). +No regression: 6-primitive codegen lane GREEN, sem .o byte-identical (540B). Reported verified to synth#354. + +**stack + msgq are now MCU-shippable wasm-cross-LTO modules.** The four synth bugs I surfaced this session +are ALL cleared: #331 (spill-slot collision, v0.11.41) → #345 (.bss+PC-relative, v0.11.43) → #350 (ADD-imm +lowering, v0.11.44) → #354 (per-region .bss/.data split, v0.11.45). Struct-return drop-in map: sem/pipe/ +mutex/stack/msgq all synth-shippable; event/queue/mbox small-struct register-return (trivially clean). +Updated gale#63 msgq row (dissolved impl now shippable for the kernel-primitives WIT world — no synth +blockers left). Next: shim+silicon stack/msgq end-to-end (full module like mutex) when wanted, or the +gale#63 component model (jess-led). + +## UPDATE 2026-06-14 18:36 — OPTIMIZE: filed loom#219 (seam-SROA) — the path to LLVM-LTO parity + +Researched the wasm-cross-LTO→LLVM-LTO gap (sem 860 vs 471 = 1.83×) at the codegen level. Root: loom +inlines the seam but doesn't DISSOLVE it — the decide's u64-packed return ABI survives as a pack- +immediately-unpack round-trip. wasm-IR evidence (sem.loom.wasm): `i64.extend/shl/or` (pack {action, +new_count}) -> `i64.and/shr_u` (unpack), with a dead `(local i64)`. synth ARM cost: 83-insn body, 23% +[sp] traffic (ptr reloaded 5x), 11 movw/movt, the u64 round-trip spilled to [sp,#0x8/0xc]. + +Filed **loom#219** with 3 ranked wasm-IR passes (benefit ARM+RISC-V, complement synth#209 backend +regalloc): (1) SROA/scalar-forwarding through the inline = kills the u64 pack/unpack ["inlined -> dissolved"]; +(2) wasm-local mem2reg/coalesce = kills the reload churn; (3) const dedup/hoist. Parity read: bit-exact +1.0x unlikely, within ~20% achievable, in-context already +11%; #1+#2 should take sem 83->~55-60 insns. +Frozen repro: repro-loom-seam-sroa/ (sem.loom.wasm + shim). Kill-criterion: no i64 pack/unpack in the +dissolved body, ARM body <~70 insns. I'm the on-silicon gate (will re-measure sem/mutex + composed +deltas when a build lands). diff --git a/benches/engine_control/silicon/boards/nucleo_g474re/control_step_constcse_157cyc.txt b/benches/engine_control/silicon/boards/nucleo_g474re/control_step_constcse_157cyc.txt new file mode 100644 index 00000000..c6718c3f --- /dev/null +++ b/benches/engine_control/silicon/boards/nucleo_g474re/control_step_constcse_157cyc.txt @@ -0,0 +1,4 @@ +*** Booting Zephyr OS build v4.4.0-7-g719cc4890346 *** +SELFCHECK synth=2165333 native=2165333 exp=2165333 OK +E,control_step,synth=157,native=67 +=== END === diff --git a/benches/engine_control/silicon/boards/nucleo_g474re/controller_pr250_168cyc.txt b/benches/engine_control/silicon/boards/nucleo_g474re/controller_pr250_168cyc.txt new file mode 100644 index 00000000..fb710f89 --- /dev/null +++ b/benches/engine_control/silicon/boards/nucleo_g474re/controller_pr250_168cyc.txt @@ -0,0 +1,5 @@ +*** Booting Zephyr OS build v4.4.0-7-g719cc4890346 *** +SELFCHECK synth=0x05e33e81 native=0x05e33e81 MATCH +E,controller_step,synth=168,native=61 +SINK=856795536 ovh=1 +=== END === diff --git a/benches/engine_control/silicon/boards/nucleo_g474re/flat_flight_262clampfold_255cyc.txt b/benches/engine_control/silicon/boards/nucleo_g474re/flat_flight_262clampfold_255cyc.txt new file mode 100644 index 00000000..c8c08e83 --- /dev/null +++ b/benches/engine_control/silicon/boards/nucleo_g474re/flat_flight_262clampfold_255cyc.txt @@ -0,0 +1,5 @@ +*** Booting Zephyr OS build v4.4.0-7-g719cc4890346 *** +SELFCHECK synth=0x07fdf307 native=0x07fdf307 exp=0x07fdf307 OK +E,flat_flight,synth=255,native=103 (ovh=1) +SINK=2093726448 +=== END === diff --git a/benches/engine_control/silicon/boards/nucleo_g474re/flat_flight_274mla_257cyc_REGRESSION.txt b/benches/engine_control/silicon/boards/nucleo_g474re/flat_flight_274mla_257cyc_REGRESSION.txt new file mode 100644 index 00000000..0b76fe47 --- /dev/null +++ b/benches/engine_control/silicon/boards/nucleo_g474re/flat_flight_274mla_257cyc_REGRESSION.txt @@ -0,0 +1,5 @@ +*** Booting Zephyr OS build v4.4.0-7-g719cc4890346 *** +SELFCHECK synth=0x07fdf307 native=0x07fdf307 exp=0x07fdf307 OK +E,flat_flight,synth=257,native=103 (ovh=1) +SINK=2093726448 +=== END === diff --git a/benches/engine_control/silicon/boards/nucleo_g474re/flat_flight_pr250_261cyc.txt b/benches/engine_control/silicon/boards/nucleo_g474re/flat_flight_pr250_261cyc.txt new file mode 100644 index 00000000..96b30045 --- /dev/null +++ b/benches/engine_control/silicon/boards/nucleo_g474re/flat_flight_pr250_261cyc.txt @@ -0,0 +1,5 @@ +*** Booting Zephyr OS build v4.4.0-7-g719cc4890346 *** +SELFCHECK synth=0x07fdf307 native=0x07fdf307 exp=0x07fdf307 OK +E,flat_flight,synth=261,native=103 (ovh=1) +SINK=2093726448 +=== END === diff --git a/benches/engine_control/silicon/boards/nucleo_g474re/m.loom.wasm b/benches/engine_control/silicon/boards/nucleo_g474re/m.loom.wasm new file mode 100644 index 00000000..8dfe14f2 Binary files /dev/null and b/benches/engine_control/silicon/boards/nucleo_g474re/m.loom.wasm differ diff --git a/benches/engine_control/silicon/boards/nucleo_g474re/mutex_fault.o b/benches/engine_control/silicon/boards/nucleo_g474re/mutex_fault.o new file mode 100644 index 00000000..61f8c014 Binary files /dev/null and b/benches/engine_control/silicon/boards/nucleo_g474re/mutex_fault.o differ diff --git a/benches/engine_control/silicon/boards/nucleo_g474re/mutex_m.loom.wasm b/benches/engine_control/silicon/boards/nucleo_g474re/mutex_m.loom.wasm new file mode 100644 index 00000000..8dfe14f2 Binary files /dev/null and b/benches/engine_control/silicon/boards/nucleo_g474re/mutex_m.loom.wasm differ diff --git a/benches/engine_control/silicon/boards/nucleo_g474re/mutex_v0.11.29_bss_still_faults.o b/benches/engine_control/silicon/boards/nucleo_g474re/mutex_v0.11.29_bss_still_faults.o new file mode 100644 index 00000000..61f8c014 Binary files /dev/null and b/benches/engine_control/silicon/boards/nucleo_g474re/mutex_v0.11.29_bss_still_faults.o differ diff --git a/benches/engine_control/silicon/boards/nucleo_g474re/mutex_v0.11.29_npabi.o b/benches/engine_control/silicon/boards/nucleo_g474re/mutex_v0.11.29_npabi.o new file mode 100644 index 00000000..61f8c014 Binary files /dev/null and b/benches/engine_control/silicon/boards/nucleo_g474re/mutex_v0.11.29_npabi.o differ diff --git a/benches/engine_control/silicon/boards/nucleo_g474re/mutex_v0.11.30_pr240_bss64k.o b/benches/engine_control/silicon/boards/nucleo_g474re/mutex_v0.11.30_pr240_bss64k.o new file mode 100644 index 00000000..78496e23 Binary files /dev/null and b/benches/engine_control/silicon/boards/nucleo_g474re/mutex_v0.11.30_pr240_bss64k.o differ diff --git a/benches/engine_control/silicon/boards/nucleo_g474re/mutex_v0.11.30_pr240_busfault.txt b/benches/engine_control/silicon/boards/nucleo_g474re/mutex_v0.11.30_pr240_busfault.txt new file mode 100644 index 00000000..0b7420b4 --- /dev/null +++ b/benches/engine_control/silicon/boards/nucleo_g474re/mutex_v0.11.30_pr240_busfault.txt @@ -0,0 +1,7 @@ +*** Booting Zephyr OS build v4.4.0-7-g719cc4890346 *** +***** BUS FAULT ***** + Imprecise data bus error +r0/a1: 0x00000000 r1/a2: 0x00000001 r2/a3: 0xffffffff +r3/a4: 0x200101a8 r12/ip: 0xfffffffc r14/lr: 0x08000233 + xpsr: 0xa1000000 +Faulting instruction address (r15/pc): 0x080004e4 diff --git a/benches/engine_control/silicon/boards/nucleo_g474re/mutex_v0.11.30_pr240_full.o b/benches/engine_control/silicon/boards/nucleo_g474re/mutex_v0.11.30_pr240_full.o new file mode 100644 index 00000000..5b584059 Binary files /dev/null and b/benches/engine_control/silicon/boards/nucleo_g474re/mutex_v0.11.30_pr240_full.o differ diff --git a/benches/engine_control/silicon/boards/nucleo_g474re/prj-lto-no-isr-local.conf b/benches/engine_control/silicon/boards/nucleo_g474re/prj-lto-no-isr-local.conf new file mode 100644 index 00000000..560f2e2a --- /dev/null +++ b/benches/engine_control/silicon/boards/nucleo_g474re/prj-lto-no-isr-local.conf @@ -0,0 +1,15 @@ +# LTO Kconfig overlay tuned for nucleo_g474re silicon-anchor builds. +# +# The upstream zephyr/gale_lto_overlay.conf includes +# CONFIG_ISR_TABLES_LOCAL_DECLARATION=y, which empirically prevents the +# LLVM linker plugin from registering the ADC1_2 IRQ-18 vector handler +# during whole-program LTO link on STM32G4 silicon. The chip then takes +# a spurious IRQ 18 during boot and halts in arch_system_halt +# (see silicon/boards/nucleo_g474re/NOTES-llvm-lto-crash.md). +# +# This overlay enables the same LTO settings WITHOUT the LOCAL_DECLARATION +# bit, restoring the conventional Zephyr ISR-table layout that the LLVM +# linker plugin handles correctly. + +CONFIG_LTO=y +CONFIG_LLVM_USE_LLD=y diff --git a/benches/engine_control/silicon/boards/nucleo_g474re/wasm_fatal_shim_poc.c b/benches/engine_control/silicon/boards/nucleo_g474re/wasm_fatal_shim_poc.c new file mode 100644 index 00000000..53e19f29 --- /dev/null +++ b/benches/engine_control/silicon/boards/nucleo_g474re/wasm_fatal_shim_poc.c @@ -0,0 +1,60 @@ +/* + * Minimal wasm-side host of k_sys_fatal_error_handler (the dissolved fatal-policy path). + * + * The 5th and last of the maintainer's u64-shaped clean decide set + * (sem_give, sem_take, pipe_write, pipe_read, fatal). Closes the u64-clean + * partition. Same construction as sem_give_shim.c: kernel APIs are externs + * (wasm imports), the verified Rust decide (gale_k_fatal_decide) rides the + * bundle so loom inlines the seam. Pure scalar-in/u64-out decide → sem-class, + * NOT --native-pointer-abi (the esf pointer is not dereferenced by the policy). + * + * Zephyr hook: k_sys_fatal_error_handler(reason, esf) is __weak — gale overrides + * it. The decide classifies reason → ABORT_THREAD (return, z_fatal_error aborts + * the faulting thread) / HALT (k_fatal_halt, no return) / IGNORE (return, continue). + */ + +#include + +struct arch_esf; /* opaque — the policy never derefs it */ + +/* Kernel API externs → wasm imports → native bl after synth-emit. */ +extern uint32_t gale_w_in_isr(void); /* arch_is_in_isr(), out-of-line */ +extern void k_fatal_halt(unsigned int reason); /* FUNC_NORETURN */ + +/* The verified Rust decide — same wasm module after merge; loom inlines it. */ +extern uint64_t gale_k_fatal_decide(uint32_t reason, uint32_t is_isr, uint32_t test_mode); + +/* AAPCS-packed decision: matches #[repr(C)] GaleFatalDecision (8 bytes). */ +union gale_fatal_decision_u { + uint64_t raw; + struct { + uint8_t action; + uint8_t pad[3]; + int32_t ret; + } dec; +}; + +#define GALE_FATAL_ACTION_ABORT_THREAD 0 +#define GALE_FATAL_ACTION_HALT 1 +#define GALE_FATAL_ACTION_IGNORE 2 + +/* The dissolved fatal-policy hook. THIS IS THE FFI SEAM. */ +void k_sys_fatal_error_handler(unsigned int reason, const struct arch_esf *esf) +{ + (void)esf; /* policy is reason-driven; arch layer owns the esf */ + + union gale_fatal_decision_u du; + du.raw = gale_k_fatal_decide(reason, gale_w_in_isr() ? 1U : 0U, 0U); + + switch (du.dec.action) { + case GALE_FATAL_ACTION_HALT: + k_fatal_halt(reason); /* never returns */ + break; + case GALE_FATAL_ACTION_ABORT_THREAD: + case GALE_FATAL_ACTION_IGNORE: + default: + /* return to z_fatal_error: ABORT_THREAD → it aborts the faulting + * thread; IGNORE → execution continues. */ + break; + } +} diff --git a/benches/engine_control/silicon/boards/nucleo_g474re/wasm_host_shim_poc.c b/benches/engine_control/silicon/boards/nucleo_g474re/wasm_host_shim_poc.c new file mode 100644 index 00000000..2105d4dd --- /dev/null +++ b/benches/engine_control/silicon/boards/nucleo_g474re/wasm_host_shim_poc.c @@ -0,0 +1,94 @@ +/* + * Minimal wasm-side host of z_impl_k_sem_give. + * + * Replicates the hot-path structure of gale-smart-data's gale_sem.c + * but with kernel APIs as externs (which become wasm imports), so the + * shim itself compiles to wasm32-unknown-unknown without pulling in + * Zephyr headers. This puts the C ↔ Rust seam INSIDE the wasm bundle — + * meld/wasm-ld merges it with gale-ffi.wasm, loom inlines through it, + * synth produces ARM with the seam dissolved. + * + * The published silicon-LTO recovery for handoff cycles was 471 (-10.8% + * vs baseline 528) at ADC=n, or 558 (vs baseline 506) at ADC=y. If the + * loom→synth output matches LLVM-LTO's inlined-into-z_impl_k_sem_give + * shape (no `bl gale_k_sem_give_decide`, decision logic merged into + * z_impl_k_sem_give's body), we have evidence that the verified-Rust + * route is at parity with LTO at the codegen level. + */ + +#include + +/* Opaque k_thread — we never deref this in the shim, kernel does. */ +struct k_thread; +/* k_spinlock has a non-zero size in Zephyr; give it one byte so the + * static instance below is a complete type. The kernel's k_spin_lock + * etc. take a pointer; they don't care about our internal size. */ +struct k_spinlock { uint8_t lock_internal; }; + +/* Match gale-smart-data layout — count + limit are the first two u32s + * in a k_sem. We don't touch the rest. */ +/* Faithful mirror of Zephyr v4.4.0 struct k_sem with CONFIG_POLL=n, + * CONFIG_WAITQ_SCALABLE=n: _wait_q_t == sys_dlist_t == {head, tail}. + * The earlier 2-field {count,limit} shape skewed count/limit by 8 bytes + * against the REAL k_sem the bench passes in, and the NULL wait_q below + * made z_unpend_first_thread read the vector table — MPU fault on + * zephyr v4.4.0 final (and semantically-unsound wakes before that). */ +struct k_sem { + void *wq_head; + void *wq_tail; + uint32_t count; + uint32_t limit; +}; + +typedef struct { uint32_t key; } k_spinlock_key_t; + +/* Kernel API externs — wasm imports at link time, native bl at synth-emit. */ +extern k_spinlock_key_t k_spin_lock(struct k_spinlock *); +extern void k_spin_unlock(struct k_spinlock *, k_spinlock_key_t); +extern struct k_thread * z_unpend_first_thread(void *wait_q); +extern void z_ready_thread(struct k_thread *); +extern void arch_thread_return_value_set(struct k_thread *, uint32_t); +extern int z_reschedule(struct k_spinlock *, k_spinlock_key_t); + +/* The verified Rust function — same wasm module after wasm-ld merge, + * so loom can inline. */ +extern uint64_t gale_k_sem_give_decide(uint32_t count, uint32_t limit, + uint32_t has_waiter); + +/* AAPCS-packed decision struct — matches gale-smart-data's layout. */ +union gale_sem_give_decision_u { + uint64_t raw; + struct { + uint8_t action; + uint8_t pad[3]; + uint32_t new_count; + } dec; +}; + +#define GALE_SEM_ACTION_WAKE 1 + +/* The shim spinlock — kept simple, kernel handles real one. */ +static struct k_spinlock shim_lock_raw; + +/* The hot path. THIS IS THE FFI SEAM. */ +void z_impl_k_sem_give(struct k_sem *sem) { + k_spinlock_key_t key = k_spin_lock(&shim_lock_raw); + + /* Extract: try to unpend first waiter (kernel side effect). */ + struct k_thread *thread = z_unpend_first_thread((void *)sem); /* wait_q is k_sem\x27s first member */ + + /* Decide: Rust determines action via 8-byte u64-packed decision. */ + union gale_sem_give_decision_u du; + du.raw = gale_k_sem_give_decide(sem->count, sem->limit, + thread != (struct k_thread *)0 ? 1U : 0U); + + /* Apply: execute the decision. */ + if (du.dec.action == GALE_SEM_ACTION_WAKE) { + arch_thread_return_value_set(thread, 0U); + z_ready_thread(thread); + } else { + sem->count = du.dec.new_count; + } + + z_reschedule(&shim_lock_raw, key); +} diff --git a/benches/engine_control/silicon/boards/nucleo_g474re/wasm_mutex_shim_poc.c b/benches/engine_control/silicon/boards/nucleo_g474re/wasm_mutex_shim_poc.c new file mode 100644 index 00000000..dd7f1fbf --- /dev/null +++ b/benches/engine_control/silicon/boards/nucleo_g474re/wasm_mutex_shim_poc.c @@ -0,0 +1,84 @@ +/* + * Minimal wasm-side host of z_impl_k_mutex_unlock — the mutex analogue of + * wasm_host_shim_poc.c (sem). Replicates gale_mutex.c's unlock hot path with + * kernel APIs as externs (wasm imports), so it compiles to wasm32 without + * Zephyr headers. Puts the C<->Rust seam (gale_k_mutex_unlock_decide) INSIDE + * the wasm bundle; wasm-ld merges it with gale-ffi.wasm, loom inlines through + * it, synth emits ARM with the seam dissolved (no `bl gale_k_mutex_unlock_decide`). + * This is the dissolvability proof for the mutex primitive (2nd after sem 907cyc). + */ +#include + +struct k_thread; +struct k_spinlock { uint8_t lock_internal; }; +typedef struct { uint32_t key; } k_spinlock_key_t; + +/* k_mutex hot-path fields (layout-compatible prefix; kernel owns the rest). */ +/* Faithful mirror of Zephyr v4.4.0 struct k_mutex (CONFIG_POLL=n, + * CONFIG_WAITQ_SCALABLE=n): _wait_q_t == sys_dlist_t == {head, tail} — + * TWO pointers. The earlier single-pointer wait_q skewed owner/count by + * 4 bytes (owner read the dlist tail -> always "not current" -> -EPERM; + * observed on silicon as SELFCHECK rc=-1 owner=). Same + * unfaithful-shim class as the sem shim's 2026-06-10 fix. + */ +struct k_mutex { + void *wq_head; + void *wq_tail; + struct k_thread *owner; + uint32_t lock_count; + int owner_orig_prio; +}; + +/* Kernel API externs -> wasm imports -> native bl after synth-emit. */ +extern k_spinlock_key_t k_spin_lock(struct k_spinlock *); +extern void k_spin_unlock(struct k_spinlock *, k_spinlock_key_t); +extern struct k_thread * z_unpend_first_thread(void *wait_q); +extern void z_ready_thread(struct k_thread *); +extern void arch_thread_return_value_set(struct k_thread *, uint32_t); +extern int z_reschedule(struct k_spinlock *, k_spinlock_key_t); +extern struct k_thread * gale_w_current(void); /* _current, out-of-line */ + +/* The verified Rust decision — same wasm module after merge, loom inlines it. */ +struct gale_mutex_unlock_decision { int32_t ret; uint8_t action; uint32_t new_lock_count; }; +extern struct gale_mutex_unlock_decision gale_k_mutex_unlock_decide( + uint32_t lock_count, uint32_t owner_is_null, uint32_t owner_is_current); + +#define GALE_MUTEX_UNLOCK_RELEASED 0 +#define GALE_MUTEX_UNLOCK_UNLOCKED 1 +#define GALE_MUTEX_UNLOCK_ERROR 2 + +static struct k_spinlock lock; + +int z_impl_k_mutex_unlock(struct k_mutex *mutex) +{ + k_spinlock_key_t key = k_spin_lock(&lock); + struct k_thread *cur = gale_w_current(); + + struct gale_mutex_unlock_decision d = gale_k_mutex_unlock_decide( + mutex->lock_count, + (mutex->owner == (struct k_thread *)0) ? 1U : 0U, + (mutex->owner == cur) ? 1U : 0U); + + if (d.action == GALE_MUTEX_UNLOCK_ERROR) { + k_spin_unlock(&lock, key); + return d.ret; + } + if (d.action == GALE_MUTEX_UNLOCK_RELEASED) { + mutex->lock_count = d.new_lock_count; /* reentrant: still held */ + k_spin_unlock(&lock, key); + return 0; + } + /* UNLOCKED: hand off to the highest-priority waiter, if any. */ + struct k_thread *new_owner = z_unpend_first_thread((void *)mutex); /* wait_q is k_mutex\x27s first member */ + mutex->owner = new_owner; + if (new_owner != (struct k_thread *)0) { + mutex->lock_count = 1U; + arch_thread_return_value_set(new_owner, 0); + z_ready_thread(new_owner); + z_reschedule(&lock, key); + } else { + mutex->lock_count = 0U; + k_spin_unlock(&lock, key); + } + return 0; +} diff --git a/benches/engine_control/silicon/boards/nucleo_g474re/wasm_pipe_read_shim_poc.c b/benches/engine_control/silicon/boards/nucleo_g474re/wasm_pipe_read_shim_poc.c new file mode 100644 index 00000000..25bf4bf3 --- /dev/null +++ b/benches/engine_control/silicon/boards/nucleo_g474re/wasm_pipe_read_shim_poc.c @@ -0,0 +1,108 @@ +/* + * Minimal wasm-side host of z_impl_k_pipe_read (the dissolved read path). + * + * Companion to wasm_pipe_write_shim_poc.c — same construction as + * sem_give_shim.c: kernel APIs are externs (wasm imports), the verified Rust + * decide (gale_k_pipe_read_decide) rides the same wasm module so loom inlines + * the C↔Rust seam and synth emits ARM with it dissolved. Shipping the `pipe` + * primitive needs BOTH directions clean; this is the read half of the gate-2 + * (shim-body-stays-in-registers) check. NOT --native-pointer-abi (u64 decide, + * sem-class; not gated on synth#345). + * + * Faithful Zephyr v4.4.0 layout (identical to the write shim). + */ + +#include + +struct k_thread; +struct k_spinlock { uint8_t lock_internal; }; +typedef struct { uint32_t key; } k_spinlock_key_t; + +struct ring_buf_index { uint32_t head; uint32_t tail; uint32_t base; }; +struct ring_buf { + uint8_t *buffer; + struct ring_buf_index put; + struct ring_buf_index get; + uint32_t size; +}; + +struct k_pipe { + uint32_t waiting; + struct ring_buf buf; + struct k_spinlock lock; + void *data_wq_head; /* readers */ + void *data_wq_tail; + void *space_wq_head; /* writers */ + void *space_wq_tail; + uint8_t flags; +}; + +extern k_spinlock_key_t k_spin_lock(struct k_spinlock *); +extern void k_spin_unlock(struct k_spinlock *, k_spinlock_key_t); +extern uint32_t ring_buf_size_get(struct ring_buf *); +extern struct k_thread * z_unpend_first_thread(void *wait_q); +extern void z_ready_thread(struct k_thread *); +extern void arch_thread_return_value_set(struct k_thread *, uint32_t); +extern int z_pend_curr(struct k_spinlock *, k_spinlock_key_t, + void *wait_q, uint64_t timeout_ticks); +extern int z_reschedule(struct k_spinlock *, k_spinlock_key_t); + +extern uint64_t gale_k_pipe_read_decide(uint32_t used, uint32_t size, + uint8_t flags, uint32_t request_len, + uint32_t has_writer); + +union gale_pipe_read_decision_u { + uint64_t raw; + struct { + uint8_t action; + uint8_t pad[3]; + uint32_t actual_bytes; + } dec; +}; + +#define GALE_PIPE_ACTION_READ_OK 0 +#define GALE_PIPE_ACTION_WAKE_WRITER 1 +#define GALE_PIPE_ACTION_READ_PEND 2 +#define GALE_PIPE_ACTION_READ_ERROR_ECANCELED 3 +#define GALE_PIPE_ACTION_READ_ERROR_EPIPE 4 + +#define GALE_EPIPE (-32) +#define GALE_ECANCELED (-125) + +/* The hot path. THIS IS THE FFI SEAM. */ +int z_impl_k_pipe_read(struct k_pipe *pipe, uint8_t *data, uint32_t len) { + (void)data; /* kernel does the ring-buffer copy after the decision */ + k_spinlock_key_t key = k_spin_lock(&pipe->lock); + + uint32_t used = ring_buf_size_get(&pipe->buf); + uint32_t size = pipe->buf.size; + struct k_thread *writer = z_unpend_first_thread((void *)&pipe->space_wq_head); + + union gale_pipe_read_decision_u du; + du.raw = gale_k_pipe_read_decide(used, size, pipe->flags, len, + writer != (struct k_thread *)0 ? 1U : 0U); + + int ret; + switch (du.dec.action) { + case GALE_PIPE_ACTION_WAKE_WRITER: + arch_thread_return_value_set(writer, du.dec.actual_bytes); + z_ready_thread(writer); + ret = (int)du.dec.actual_bytes; + break; + case GALE_PIPE_ACTION_READ_PEND: + return z_pend_curr(&pipe->lock, key, (void *)&pipe->data_wq_head, len); + case GALE_PIPE_ACTION_READ_ERROR_EPIPE: + ret = GALE_EPIPE; + break; + case GALE_PIPE_ACTION_READ_ERROR_ECANCELED: + ret = GALE_ECANCELED; + break; + case GALE_PIPE_ACTION_READ_OK: + default: + ret = (int)du.dec.actual_bytes; + break; + } + + z_reschedule(&pipe->lock, key); + return ret; +} diff --git a/benches/engine_control/silicon/boards/nucleo_g474re/wasm_pipe_write_shim_poc.c b/benches/engine_control/silicon/boards/nucleo_g474re/wasm_pipe_write_shim_poc.c new file mode 100644 index 00000000..a0413ddf --- /dev/null +++ b/benches/engine_control/silicon/boards/nucleo_g474re/wasm_pipe_write_shim_poc.c @@ -0,0 +1,122 @@ +/* + * Minimal wasm-side host of z_impl_k_pipe_write (the dissolved write path). + * + * Same construction as sem_give_shim.c: kernel APIs are externs (become wasm + * imports), the verified Rust decide (gale_k_pipe_write_decide) is in the same + * wasm module after wasm-ld merge, so loom inlines through the C↔Rust seam and + * synth emits ARM with the seam dissolved. Pipe is the second u64-shaped + * primitive (after sem): its decide returns a packed u64 (no sret), so unlike + * the 51 struct-return decides it does NOT need --native-pointer-abi and is not + * gated on synth#345. The open question this shim answers is gate-2: does the + * (more complex, 5-action) write body stay in registers, or spill to a wasm + * linmem stack frame? sem's body is simple enough to stay in registers; this + * is the empirical check for pipe. + * + * Faithful Zephyr v4.4.0 layout: k_pipe { size_t waiting; struct ring_buf buf; + * k_spinlock lock; _wait_q_t data; _wait_q_t space; uint8_t flags; }. + */ + +#include + +struct k_thread; +struct k_spinlock { uint8_t lock_internal; }; +typedef struct { uint32_t key; } k_spinlock_key_t; + +/* Faithful struct ring_buf (v4.4.0): buffer ptr + two 3-word indices + size. */ +struct ring_buf_index { uint32_t head; uint32_t tail; uint32_t base; }; +struct ring_buf { + uint8_t *buffer; + struct ring_buf_index put; + struct ring_buf_index get; + uint32_t size; +}; + +/* Faithful struct k_pipe (v4.4.0, CONFIG_POLL=n / WAITQ_SCALABLE=n: + * _wait_q_t == sys_dlist_t == {head, tail}). */ +struct k_pipe { + uint32_t waiting; /* size_t on 32-bit ARM */ + struct ring_buf buf; + struct k_spinlock lock; + void *data_wq_head; /* _wait_q_t data (readers) */ + void *data_wq_tail; + void *space_wq_head; /* _wait_q_t space (writers) */ + void *space_wq_tail; + uint8_t flags; +}; + +/* Kernel API externs — wasm imports at link time, native bl at synth-emit. */ +extern k_spinlock_key_t k_spin_lock(struct k_spinlock *); +extern void k_spin_unlock(struct k_spinlock *, k_spinlock_key_t); +extern uint32_t ring_buf_size_get(struct ring_buf *); +extern struct k_thread * z_unpend_first_thread(void *wait_q); +extern void z_ready_thread(struct k_thread *); +extern void arch_thread_return_value_set(struct k_thread *, uint32_t); +extern int z_pend_curr(struct k_spinlock *, k_spinlock_key_t, + void *wait_q, uint64_t timeout_ticks); +extern int z_reschedule(struct k_spinlock *, k_spinlock_key_t); + +/* The verified Rust decide — same wasm module after wasm-ld merge. */ +extern uint64_t gale_k_pipe_write_decide(uint32_t used, uint32_t size, + uint8_t flags, uint32_t request_len, + uint32_t has_reader); + +/* AAPCS-packed decision: matches #[repr(C)] GalePipeWriteDecision (8 bytes). */ +union gale_pipe_write_decision_u { + uint64_t raw; + struct { + uint8_t action; + uint8_t pad[3]; + uint32_t actual_bytes; + } dec; +}; + +#define GALE_PIPE_ACTION_WRITE_OK 0 +#define GALE_PIPE_ACTION_WAKE_READER 1 +#define GALE_PIPE_ACTION_WRITE_PEND 2 +#define GALE_PIPE_ACTION_WRITE_ERROR_ECANCELED 3 +#define GALE_PIPE_ACTION_WRITE_ERROR_EPIPE 4 + +#define GALE_EPIPE (-32) +#define GALE_ECANCELED (-125) + +/* The hot path. THIS IS THE FFI SEAM. */ +int z_impl_k_pipe_write(struct k_pipe *pipe, const uint8_t *data, uint32_t len) { + (void)data; /* kernel does the ring-buffer copy after the decision */ + k_spinlock_key_t key = k_spin_lock(&pipe->lock); + + /* Extract: current fill + capacity + a waiting reader (kernel side effect). */ + uint32_t used = ring_buf_size_get(&pipe->buf); + uint32_t size = pipe->buf.size; + struct k_thread *reader = z_unpend_first_thread((void *)&pipe->data_wq_head); + + /* Decide: Rust packs the action + writable byte count into a u64. */ + union gale_pipe_write_decision_u du; + du.raw = gale_k_pipe_write_decide(used, size, pipe->flags, len, + reader != (struct k_thread *)0 ? 1U : 0U); + + /* Apply. */ + int ret; + switch (du.dec.action) { + case GALE_PIPE_ACTION_WAKE_READER: + arch_thread_return_value_set(reader, du.dec.actual_bytes); + z_ready_thread(reader); + ret = (int)du.dec.actual_bytes; + break; + case GALE_PIPE_ACTION_WRITE_PEND: + /* z_pend_curr releases the lock and blocks the caller. */ + return z_pend_curr(&pipe->lock, key, (void *)&pipe->space_wq_head, len); + case GALE_PIPE_ACTION_WRITE_ERROR_EPIPE: + ret = GALE_EPIPE; + break; + case GALE_PIPE_ACTION_WRITE_ERROR_ECANCELED: + ret = GALE_ECANCELED; + break; + case GALE_PIPE_ACTION_WRITE_OK: + default: + ret = (int)du.dec.actual_bytes; + break; + } + + z_reschedule(&pipe->lock, key); + return ret; +} diff --git a/benches/engine_control/silicon/boards/nucleo_g474re/wasm_sem_take_shim_poc.c b/benches/engine_control/silicon/boards/nucleo_g474re/wasm_sem_take_shim_poc.c new file mode 100644 index 00000000..86408895 --- /dev/null +++ b/benches/engine_control/silicon/boards/nucleo_g474re/wasm_sem_take_shim_poc.c @@ -0,0 +1,84 @@ +/* + * Minimal wasm-side host of z_impl_k_sem_take (the dissolved blocking-acquire path). + * + * Completes the sem primitive for wasm-cross-LTO: #59 ships k_sem_give (the + * give/handoff half); this is k_sem_take (the acquire/block half), so the full + * v0.1.0 sem primitive can dissolve, not just give. Same construction as + * sem_give_shim.c (kernel APIs as wasm imports, the verified Rust decide rides + * the bundle so loom inlines the seam). u64 decide → sem-class, NOT + * --native-pointer-abi, NOT gated on synth#345. + * + * Faithful to the fork's z_impl_k_sem_take: count>0 → acquire (count--, unlock); + * K_NO_WAIT → -EBUSY (unlock); else z_pend_curr(&lock,key,&sem->wait_q,timeout). + * Unlike give, the acquire/nowait paths use k_spin_unlock (no reschedule); the + * block path hands off to z_pend_curr (which releases the lock and blocks). + */ + +#include + +struct k_thread; +struct k_spinlock { uint8_t lock_internal; }; +typedef struct { uint32_t key; } k_spinlock_key_t; +typedef struct { int64_t ticks; } k_timeout_t; /* K_NO_WAIT == {0} */ + +/* Faithful Zephyr v4.4.0 k_sem (CONFIG_POLL=n / WAITQ_SCALABLE=n). */ +struct k_sem { + void *wq_head; + void *wq_tail; + uint32_t count; + uint32_t limit; +}; + +extern k_spinlock_key_t k_spin_lock(struct k_spinlock *); +extern void k_spin_unlock(struct k_spinlock *, k_spinlock_key_t); +extern int z_pend_curr(struct k_spinlock *, k_spinlock_key_t, + void *wait_q, k_timeout_t timeout); + +extern uint64_t gale_k_sem_take_decide(uint32_t count, uint32_t is_no_wait); + +/* AAPCS-packed decision: matches #[repr(C)] GaleSemTakeDecision (8 bytes). */ +union gale_sem_take_decision_u { + uint64_t raw; + struct { + uint8_t action; + uint8_t pad[3]; + uint32_t new_count; + } dec; +}; + +#define GALE_SEM_TAKE_ACQUIRED 0 +#define GALE_SEM_TAKE_WOULD_BLOCK 1 +#define GALE_SEM_TAKE_PEND 2 +#define GALE_EBUSY (-16) + +static struct k_spinlock shim_lock_raw; + +/* The hot path. THIS IS THE FFI SEAM. */ +int z_impl_k_sem_take(struct k_sem *sem, k_timeout_t timeout) { + k_spinlock_key_t key = k_spin_lock(&shim_lock_raw); + + uint32_t is_no_wait = (timeout.ticks == 0) ? 1U : 0U; + + union gale_sem_take_decision_u du; + du.raw = gale_k_sem_take_decide(sem->count, is_no_wait); + + int ret; + switch (du.dec.action) { + case GALE_SEM_TAKE_ACQUIRED: + sem->count = du.dec.new_count; + k_spin_unlock(&shim_lock_raw, key); + ret = 0; + break; + case GALE_SEM_TAKE_WOULD_BLOCK: + k_spin_unlock(&shim_lock_raw, key); + ret = GALE_EBUSY; + break; + case GALE_SEM_TAKE_PEND: + default: + /* z_pend_curr releases the lock and blocks the caller; wait_q is + * k_sem's first member. */ + ret = z_pend_curr(&shim_lock_raw, key, (void *)sem, timeout); + break; + } + return ret; +} diff --git a/benches/engine_control/silicon/boards/nucleo_g474re/wasm_stack_push_shim_poc.c b/benches/engine_control/silicon/boards/nucleo_g474re/wasm_stack_push_shim_poc.c new file mode 100644 index 00000000..6ca58feb --- /dev/null +++ b/benches/engine_control/silicon/boards/nucleo_g474re/wasm_stack_push_shim_poc.c @@ -0,0 +1,77 @@ +/* + * Minimal wasm-side host of z_impl_k_stack_push — a 2nd struct-return primitive + * (after mutex) to confirm synth#345 (.bss + PC-relative) generalizes the whole + * struct-return decide family, and to de-risk the gale#63 component epic (which + * will dissolve many struct-return primitives via the kernel-primitives WIT world). + * + * gale_k_stack_push_decide returns GaleStackPushDecision (12-byte #[repr(C)]: + * ret i32 / new_count u32 / action u8) BY VALUE → sret → linmem-frame path, the + * same shape that USAGE-FAULTed mutex pre-#345. With v0.11.43 the expected shape + * is link-survivable: .data bounded (~4), .bss NOBITS, MOVW/MOVT_ABS=0, ABS32 pool + * words — the "mutex shape", NOT the old 64 KB .data blob. Built WITH + * --native-pointer-abi (host k_stack* stays base=0 via the r11=0 trampoline). + * + * Faithful Zephyr v4.4.0 struct k_stack: wait_q first (so &stack == &stack->wait_q). + */ + +#include + +typedef uintptr_t stack_data_t; +struct k_thread; +struct k_spinlock { uint8_t lock_internal; }; +typedef struct { uint32_t key; } k_spinlock_key_t; + +struct k_stack { + void *wq_head; /* _wait_q_t wait_q (head,tail) */ + void *wq_tail; + struct k_spinlock lock; + stack_data_t *base; + stack_data_t *next; + stack_data_t *top; + uint8_t flags; +}; + +extern k_spinlock_key_t k_spin_lock(struct k_spinlock *); +extern void k_spin_unlock(struct k_spinlock *, k_spinlock_key_t); +extern struct k_thread * z_unpend_first_thread(void *wait_q); +extern void z_ready_thread(struct k_thread *); +extern void z_thread_return_value_set_with_data(struct k_thread *, unsigned int, void *); +extern int z_reschedule(struct k_spinlock *, k_spinlock_key_t); + +/* #[repr(C)] GaleStackPushDecision — 12 bytes, returned by value (sret). */ +struct gale_stack_push_decision { int32_t ret; uint32_t new_count; uint8_t action; }; +extern struct gale_stack_push_decision gale_k_stack_push_decide( + uint32_t count, uint32_t capacity, uint32_t has_waiter); + +#define GALE_STACK_PUSH_STORE 0 +#define GALE_STACK_PUSH_WAKE 1 +#define GALE_STACK_PUSH_FULL 2 + +int z_impl_k_stack_push(struct k_stack *stack, stack_data_t data) +{ + k_spinlock_key_t key = k_spin_lock(&stack->lock); + + uint32_t capacity = (uint32_t)(stack->top - stack->base); + uint32_t count = (uint32_t)(stack->next - stack->base); + struct k_thread *waiter = z_unpend_first_thread((void *)stack); /* wait_q is first member */ + + struct gale_stack_push_decision d = + gale_k_stack_push_decide(count, capacity, waiter != (struct k_thread *)0 ? 1U : 0U); + + switch (d.action) { + case GALE_STACK_PUSH_WAKE: + z_thread_return_value_set_with_data(waiter, 0U, (void *)data); + z_ready_thread(waiter); + z_reschedule(&stack->lock, key); + return d.ret; + case GALE_STACK_PUSH_FULL: + k_spin_unlock(&stack->lock, key); + return d.ret; /* -ENOMEM */ + case GALE_STACK_PUSH_STORE: + default: + *(stack->next) = data; + stack->next++; + k_spin_unlock(&stack->lock, key); + return d.ret; + } +} diff --git a/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-NATIVE-baseline-3fns/manifest.txt b/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-NATIVE-baseline-3fns/manifest.txt new file mode 100644 index 00000000..78f09c06 --- /dev/null +++ b/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-NATIVE-baseline-3fns/manifest.txt @@ -0,0 +1,8 @@ +RISC-V NATIVE baseline, 3 functions (qemu_riscv32 virt -icount, instruction-count proxy NOT silicon cycles). +riscv64-zephyr-elf-gcc -march=rv32imac_zicsr -mabi=ilp32 -O2, synth riscv-runtime startup/linker, mcycle CSR. + filter_axis : 17 (correct) + control_step : 62 (chk=2165333 = fuel 2645, correct) + flat_flight : 75 (chk=0x07fdf307, correct) [composed filter+controller, fully inlined] +All functionally CORRECT on RV32. These are the native baselines for synth-rv32 comparison (pending synth#218 +fix in v0.11.21). Caveat: icount = instruction count; real RV silicon cycles later via ESP32-C3/Renode. +Harness /tmp/rv-bench/ reusable: swap native obj for `synth -b riscv -t rv32imac` output. diff --git a/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-NATIVE-baseline-3fns/output.txt b/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-NATIVE-baseline-3fns/output.txt new file mode 100644 index 00000000..9f444838 --- /dev/null +++ b/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-NATIVE-baseline-3fns/output.txt @@ -0,0 +1,6 @@ +RV-NATIVE rv32imac (qemu -icount proxy) +E,filter_axis,cyc=17 +E,control_step,cyc=62,chk=2165333 (exp 2165333) +E,flat_flight,cyc=75,chk=0x07fdf307 (exp 0x07fdf307) +=== END === +qemu-system-riscv32: terminating on signal 15 from pid 43019 () diff --git a/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-control_step-SYNTH-v0.11.23/manifest.txt b/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-control_step-SYNTH-v0.11.23/manifest.txt new file mode 100644 index 00000000..e562bbd3 --- /dev/null +++ b/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-control_step-SYNTH-v0.11.23/manifest.txt @@ -0,0 +1,6 @@ +synth-rv32 control_step (v0.11.23 -b riscv -t rv32imac), qemu_riscv32 -icount. Tables via s11 trampoline +(s11=&gale_tables-0x10000; synth reads [s11+0x10000+idx]; #220-fix excludes s11 so synth preserves it). +CORRECT: synth=2165333 == native == expected (fuel 2645, 0x00210a55). synth_rv32=141 (incl ~6-cyc s11 tramp) +vs native_rv32=62 => ~2.27x (core ~2.18x). Confirms the maintainer's control_step_riscv_differential on real qemu. +Cross-target: control_step ARM 2.07x ~ RISC-V 2.27x; filter_axis ARM 2.42x ~ RISC-V 2.18x -> ~2x gap is general +codegen (regalloc/spill = Opt3), arch-independent. (icount proxy; real RV cycles via ESP/Renode later.) diff --git a/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-control_step-SYNTH-v0.11.23/output.txt b/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-control_step-SYNTH-v0.11.23/output.txt new file mode 100644 index 00000000..67d0b6d1 --- /dev/null +++ b/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-control_step-SYNTH-v0.11.23/output.txt @@ -0,0 +1,4 @@ +SYNTH-RV32 control_step=2165333 native=2165333 (exp 2165333) +E,control_step,synth_rv32=141 (incl ~6-cyc s11 tramp),native_rv32=62 +=== END === +qemu-system-riscv32: terminating on signal 15 from pid 46183 () diff --git a/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-controller_step-SYNTH-v0.11.25/manifest.txt b/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-controller_step-SYNTH-v0.11.25/manifest.txt new file mode 100644 index 00000000..60a6363c --- /dev/null +++ b/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-controller_step-SYNTH-v0.11.25/manifest.txt @@ -0,0 +1 @@ +synth-rv32 controller_step v0.11.25 (#226 fixed): synth=114 native=49 = 2.33x, CORRECT. qemu_riscv32 -icount proxy. diff --git a/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-controller_step-SYNTH-v0.11.25/output.txt b/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-controller_step-SYNTH-v0.11.25/output.txt new file mode 100644 index 00000000..4ddd2348 --- /dev/null +++ b/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-controller_step-SYNTH-v0.11.25/output.txt @@ -0,0 +1,4 @@ +SYNTH-RV32 controller=0x05ce7f9c native=0x05ce7f9c (exp 0x05ce7f9c) +E,controller_step,synth_rv32=114,native_rv32=49 +=== END === +qemu-system-riscv32: terminating on signal 15 from pid 47851 () diff --git a/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-filter_axis-NATIVE-baseline/manifest.txt b/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-filter_axis-NATIVE-baseline/manifest.txt new file mode 100644 index 00000000..7b8255e6 --- /dev/null +++ b/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-filter_axis-NATIVE-baseline/manifest.txt @@ -0,0 +1,11 @@ +RISC-V NATIVE baseline (the "build it yourself native first" step). filter_axis on RV32. +Toolchain: riscv64-zephyr-elf-gcc -march=rv32imac_zicsr -mabi=ilp32 -O2. Runtime: synth riscv-runtime +(startup.c+linker.ld, flash@0x80000000 ram@0x80010000 linmem=4K stack=8K). Harness: main.c reads mcycle CSR +around filter_axis, NS16550 UART @0x10000000. Emulator: qemu-system-riscv32 -machine virt -icount shift=0. +RESULT: filter_axis_native_rv32 = 14 (icount proxy), ovh=1. Functionally CORRECT (selfcheck 1088 / -1917). +CAVEAT: qemu -icount = INSTRUCTION COUNT (1 insn = 1 "cycle"), NOT silicon cycles — a relative/structural +proxy. Valid for native-vs-synth RISC-V comparison ON THE SAME emulator; real RISC-V silicon cycles come +later from ESP32-C3 / Renode. (ARM filter_axis native was 19 real M4 cyc via DWT — different core/unit, not +directly comparable; the meaningful RISC-V comparison is synth-rv32 vs native-rv32 on qemu, pending synth#218.) +Design fact: RISC-V linear-memory base = s11 (riscv-runtime _reset: la s11, __linear_memory_base) — RV analogue of ARM r11. +Harness dir: /tmp/rv-bench/ (reusable: swap filter_native.o for synth -b riscv .o once #218 lands). diff --git a/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-filter_axis-NATIVE-baseline/output.txt b/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-filter_axis-NATIVE-baseline/output.txt new file mode 100644 index 00000000..756de4a1 --- /dev/null +++ b/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-filter_axis-NATIVE-baseline/output.txt @@ -0,0 +1,4 @@ +RV SELFCHECK filter_axis(1000,100,500)=1088 (exp 1088) (-2000,50,-300)=-1917 (exp -1917) +E,filter_axis_native_rv32,cyc=14,ovh=1 +=== END === +qemu-system-riscv32: terminating on signal 15 from pid 42710 () diff --git a/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-filter_axis-SYNTH-v0.11.21/manifest.txt b/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-filter_axis-SYNTH-v0.11.21/manifest.txt new file mode 100644 index 00000000..5c12e65e --- /dev/null +++ b/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-filter_axis-SYNTH-v0.11.21/manifest.txt @@ -0,0 +1,6 @@ +synth-rv32 wasm-cross-LTO filter_axis (synth v0.11.21 -b riscv -t rv32imac), qemu_riscv32 -icount. +FUNCTIONALLY CORRECT: selfcheck 1088 / -1917 (== native + ARM). The wasm->loom->synth -b riscv->RV32 path +runs end-to-end. cyc=50 incl ~24-cyc s-register-preserving trampoline (workaround for synth#220: riscv +backend clobbers callee-saved s1-s6 w/o prologue/epilogue). Core ~26 icount vs native rv32 17. Clean number +pending #220 fix (drop the trampoline). synth's riscv codegen for the arithmetic/division is correct; only +the ABI register-preservation is broken. diff --git a/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-filter_axis-SYNTH-v0.11.21/output.txt b/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-filter_axis-SYNTH-v0.11.21/output.txt new file mode 100644 index 00000000..5f067c83 --- /dev/null +++ b/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-filter_axis-SYNTH-v0.11.21/output.txt @@ -0,0 +1,4 @@ +SYNTH-RV32 filter_axis(1000,100,500)=1088 (exp 1088) (-2000,50,-300)=-1917 (exp -1917) +E,filter_axis_SYNTH_rv32,cyc=50 (incl ~24-cyc s-save/restore tramp workaround for #220) +=== END === +qemu-system-riscv32: terminating on signal 15 from pid 44304 () diff --git a/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-filter_axis-SYNTH-v0.11.22-CLEAN/manifest.txt b/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-filter_axis-SYNTH-v0.11.22-CLEAN/manifest.txt new file mode 100644 index 00000000..76001101 --- /dev/null +++ b/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-filter_axis-SYNTH-v0.11.22-CLEAN/manifest.txt @@ -0,0 +1,7 @@ +synth-rv32 filter_axis, v0.11.22 (#220 callee-saved ABI fix), CLEAN — no trampoline, direct call. +qemu_riscv32 -icount. filter_axis SYNTH-rv32 = 37 icount vs NATIVE rv32 17 = 2.18x. Correct (selfcheck 1088/-1917 +verified earlier). Gap source: v0.11.22 added the s-reg save/restore prologue (addi sp,-32; sw s1-s6; lw s1-s6 ~15 cyc) +because synth spills into callee-saved s1-s6 where native gcc uses caller-saved/fewer regs -> the RISC-V analogue +of ARM Opt 3 (regalloc/spill). Cross-target: synth ~2.18x (RV32) vs 2.42x (ARM) for filter_axis -> the ~2x gap is +general codegen, NOT arch-specific. (icount proxy, not silicon cycles; real RV cycles later via ESP/Renode.) +control_step/flat_flight here are NATIVE (62/75) baselines; their synth-rv32 awaits v0.11.23 (#223 Select/locals). diff --git a/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-filter_axis-SYNTH-v0.11.22-CLEAN/output.txt b/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-filter_axis-SYNTH-v0.11.22-CLEAN/output.txt new file mode 100644 index 00000000..a46fbc53 --- /dev/null +++ b/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-filter_axis-SYNTH-v0.11.22-CLEAN/output.txt @@ -0,0 +1,6 @@ +RV-NATIVE rv32imac (qemu -icount proxy) +E,filter_axis,cyc=37 +E,control_step,cyc=62,chk=2165333 (exp 2165333) +E,flat_flight,cyc=75,chk=0x07fdf307 (exp 0x07fdf307) +=== END === +qemu-system-riscv32: terminating on signal 15 from pid 45464 () diff --git a/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-flat_flight-SYNTH-v0.11.25/manifest.txt b/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-flat_flight-SYNTH-v0.11.25/manifest.txt new file mode 100644 index 00000000..e7e00516 --- /dev/null +++ b/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-flat_flight-SYNTH-v0.11.25/manifest.txt @@ -0,0 +1 @@ +synth-rv32 flat_flight v0.11.25 (#226 fixed): synth=193 native=75 = 2.57x, CORRECT. qemu_riscv32 -icount proxy. diff --git a/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-flat_flight-SYNTH-v0.11.25/output.txt b/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-flat_flight-SYNTH-v0.11.25/output.txt new file mode 100644 index 00000000..4ad7db57 --- /dev/null +++ b/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-flat_flight-SYNTH-v0.11.25/output.txt @@ -0,0 +1,3 @@ +E,flat_flight,synth_rv32=193 (incl ~6-cyc s11=0 tramp),native_rv32=75 +=== END === +qemu-system-riscv32: terminating on signal 15 from pid 47993 () diff --git a/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-v0.11.27-opt3-leafalloc-remeasure/filter_controller_output.txt b/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-v0.11.27-opt3-leafalloc-remeasure/filter_controller_output.txt new file mode 100644 index 00000000..f725659f --- /dev/null +++ b/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-v0.11.27-opt3-leafalloc-remeasure/filter_controller_output.txt @@ -0,0 +1,6 @@ +filter synth=1088 native=1088 (exp 1088) +controller synth=97419164 native=97419164 (exp 97419164) +E,filter,synth=23,native=17 +E,controller,synth=100,native=49 +=== END === +qemu-system-riscv32: terminating on signal 15 from pid 65958 () diff --git a/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-v0.11.27-opt3-leafalloc-remeasure/flat_flight_output.txt b/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-v0.11.27-opt3-leafalloc-remeasure/flat_flight_output.txt new file mode 100644 index 00000000..f548b64e --- /dev/null +++ b/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-v0.11.27-opt3-leafalloc-remeasure/flat_flight_output.txt @@ -0,0 +1,3 @@ +E,flat_flight,synth_rv32=181 (incl ~6-cyc s11=0 tramp),native_rv32=75 +=== END === +qemu-system-riscv32: terminating on signal 15 from pid 66147 () diff --git a/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-v0.11.27-opt3-leafalloc-remeasure/manifest.txt b/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-v0.11.27-opt3-leafalloc-remeasure/manifest.txt new file mode 100644 index 00000000..7ad53450 --- /dev/null +++ b/benches/engine_control/silicon/runs-riscv/2026-06-03-qemu_riscv32-v0.11.27-opt3-leafalloc-remeasure/manifest.txt @@ -0,0 +1,14 @@ +v0.11.27 re-measure — RV32 leaf re-allocation (Opt3 increment #1: caller-saved preference) + #232 signed-div fix. +synth v0.11.27 (merged #231 lowest-free alloc + #233 div-guard fix), loom v1.1.10, qemu_riscv32 -icount shift=0 (proxy, not silicon). +All four leaves FUNCTIONALLY CORRECT; all now spill 0 callee-saved registers (were s1-s6). + +leaf v0.11.25 v0.11.27 native ratio v25->v27 correct +filter_axis 37 23 17 2.18x -> 1.35x 1088 +control_step 141 129 62 2.27x -> 2.08x 2165333 (incl ~6-cyc s11 table tramp) +controller_step 114 100 49 2.33x -> 2.04x 97419164 +flat_flight 193 181 75 2.57x -> 2.41x 0x07fdf307 (composed; benefits least) + +Leaves move most (filter ~halves overhead: tiny body was almost all prologue spill). Composed flat_flight +moves least -> next lever is const-CSE + cross-statement local promotion (Opt3 increment #2), maintainer agrees. +NOTE: filter_axis + flat_flight were BROKEN on v0.11.26 (#232 i32.div_s dividend-clobber); restored here. +Caught by the new testbed RV32 funccheck lane (arch/riscv/run_rv_funccheck.sh). diff --git a/benches/engine_control/silicon/runs-riscv/2026-06-10-qemu_riscv32-v0.11.35-rebaseline/controller_output.txt b/benches/engine_control/silicon/runs-riscv/2026-06-10-qemu_riscv32-v0.11.35-rebaseline/controller_output.txt new file mode 100644 index 00000000..93c1c5ee --- /dev/null +++ b/benches/engine_control/silicon/runs-riscv/2026-06-10-qemu_riscv32-v0.11.35-rebaseline/controller_output.txt @@ -0,0 +1,3 @@ +E,controller_step,cyc=100,chk=97419164 (exp 97419164) +=== END === +qemu-system-riscv32: terminating on signal 15 from pid 88145 () diff --git a/benches/engine_control/silicon/runs-riscv/2026-06-10-qemu_riscv32-v0.11.35-rebaseline/filter_flatflight_output.txt b/benches/engine_control/silicon/runs-riscv/2026-06-10-qemu_riscv32-v0.11.35-rebaseline/filter_flatflight_output.txt new file mode 100644 index 00000000..68634c9c --- /dev/null +++ b/benches/engine_control/silicon/runs-riscv/2026-06-10-qemu_riscv32-v0.11.35-rebaseline/filter_flatflight_output.txt @@ -0,0 +1,5 @@ +RV-NATIVE rv32imac (qemu -icount proxy) +E,filter_axis,cyc=23 +E,flat_flight,cyc=172,chk=0x07fdf307 (exp 0x07fdf307) +=== END === +qemu-system-riscv32: terminating on signal 15 from pid 85172 () diff --git a/benches/engine_control/silicon/runs-riscv/2026-06-10-qemu_riscv32-v0.11.35-rebaseline/manifest.txt b/benches/engine_control/silicon/runs-riscv/2026-06-10-qemu_riscv32-v0.11.35-rebaseline/manifest.txt new file mode 100644 index 00000000..bfa6274d --- /dev/null +++ b/benches/engine_control/silicon/runs-riscv/2026-06-10-qemu_riscv32-v0.11.35-rebaseline/manifest.txt @@ -0,0 +1,13 @@ +v0.11.35 RV32 re-baseline (loom 1.1.11), qemu_riscv32 -icount shift=0 (proxy, not silicon). +RV32 funccheck lane: ALL GREEN (all 4 leaves correct). + +leaf v0.11.27 v0.11.35 native ratio +filter_axis 23 23 17 1.35x (unchanged) +control_step 129 129 62 2.08x (unchanged; incl ~6-cyc s11 tramp) +flat_flight 181 *172* 75 2.41x -> 2.29x (chk=0x07fdf307 correct) +controller_step 100 100 49 2.04x (unchanged; chk=97419164 correct) + +flat_flight -9: the v0.11.28-35 codegen work (const-CSE remat-avoidance, in-place select, Chaitin +spill-cost) moved the COMPOSED RV32 path where ARM flat_flight stayed flat (241) — the allocator levers +fire on RV32's register pressure. Harness: arch/riscv (in-repo), pointer leaves via s11=0 startup variant, +control_step via run_synth.sh s11-table trampoline. diff --git a/benches/engine_control/silicon/runs/2026-05-09-nucleo_g474re-06515098-baseline-systick/events.csv b/benches/engine_control/silicon/runs/2026-05-09-nucleo_g474re-06515098-baseline-systick/events.csv new file mode 100644 index 00000000..07fbb5cc --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-05-09-nucleo_g474re-06515098-baseline-systick/events.csv @@ -0,0 +1,3372 @@ +Rsilicon-2026-05-09,baseline,E,12,0,500,250,549 +Rsilicon-2026-05-09,baseline,E,13,0,500,250,549 +Rsilicon-2026-05-09,baseline,E,14,0,500,250,549 +Rsilicon-2026-05-09,baseline,E,15,0,500,250,549 +Rsilicon-2026-05-09,baseline,E,16,0,500,250,549 +Rsilicon-2026-05-09,baseline,E,17,0,500,250,549 +Rsilicon-2026-05-09,baseline,E,18,0,500,250,549 +Rsilicon-2026-05-09,baseline,E,19,0,500,250,549 +Rsilicon-2026-05-09,baseline,E,20,0,500,250,549 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+# Rsilicon-2026-05-09 baseline: step 1/13 rpm=500 period_us=333 ints=500 count=355 +Rsilicon-2026-05-09,baseline,D,step_1,116761444,29,145,187,182,91 +Rsilicon-2026-05-09,baseline,H,step_1,176546,24160,0 +Rsilicon-2026-05-09,baseline,E,500,1,1000,250,1309 +Rsilicon-2026-05-09,baseline,E,501,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,502,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,503,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,504,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,505,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,506,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,507,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,508,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,509,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,510,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,511,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,512,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,513,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,514,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,515,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,516,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,517,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,518,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,519,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,520,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,521,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,522,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,523,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,524,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,525,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,526,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,527,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,528,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,529,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,530,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,531,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,532,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,533,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,534,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,535,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,536,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,537,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,538,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,539,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,540,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,541,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,542,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,543,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,544,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,545,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,546,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,547,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,548,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,549,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,550,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,551,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,552,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,553,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,554,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,555,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,556,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,557,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,558,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,559,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,560,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,561,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,562,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,563,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,564,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,565,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,566,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,567,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,568,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,569,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,570,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,571,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,572,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,573,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,574,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,575,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,576,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,577,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,578,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,579,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,580,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,581,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,582,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,583,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,584,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,585,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,586,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,587,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,588,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,589,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,590,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,591,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,592,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,593,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,594,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,595,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,596,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,597,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,598,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,599,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,600,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,601,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,602,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,603,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,604,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,605,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,606,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,607,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,608,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,609,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,610,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,611,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,612,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,613,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,614,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,615,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,616,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,617,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,618,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,619,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,620,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,621,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,622,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,623,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,624,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,625,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,626,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,627,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,628,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,629,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,630,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,631,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,632,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,633,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,634,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,635,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,636,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,637,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,638,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,639,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,640,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,641,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,642,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,643,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,644,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,645,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,646,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,647,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,648,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,649,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,650,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,651,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,652,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,653,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,654,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,655,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,656,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,657,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,658,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,659,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,660,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,661,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,662,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,663,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,664,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,665,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,666,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,667,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,668,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,669,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,670,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,671,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,672,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,673,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,674,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,675,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,676,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,677,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,678,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,679,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,680,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,681,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,682,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,683,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,684,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,685,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,686,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,687,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,688,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,689,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,690,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,691,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,692,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,693,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,694,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,695,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,696,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,697,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,698,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,699,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,700,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,701,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,702,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,703,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,704,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,705,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,706,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,707,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,708,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,709,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,710,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,711,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,712,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,713,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,714,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,715,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,716,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,717,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,718,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,719,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,720,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,721,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,722,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,723,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,724,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,725,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,726,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,727,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,728,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,729,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,730,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,731,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,732,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,733,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,734,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,735,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,736,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,737,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,738,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,739,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,740,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,741,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,742,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,743,1,1000,250,293 +Rsilicon-2026-05-09,baseline,E,744,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,745,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,746,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,747,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,748,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,749,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,750,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,751,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,752,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,753,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,754,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,755,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,756,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,757,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,758,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,759,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,760,1,1000,250,549 +Rsilicon-2026-05-09,baseline,E,761,1,1000,250,549 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+Rsilicon-2026-05-09,baseline,E,1262,2,1500,250,549 +Rsilicon-2026-05-09,baseline,E,1263,2,1500,250,549 +Rsilicon-2026-05-09,baseline,E,1264,2,1500,250,549 +Rsilicon-2026-05-09,baseline,E,1265,2,1500,250,549 +Rsilicon-2026-05-09,baseline,E,1266,2,1500,250,549 +Rsilicon-2026-05-09,baseline,E,1267,2,1500,250,549 +Rsilicon-2026-05-09,baseline,E,1268,2,1500,250,549 +Rsilicon-2026-05-09,baseline,E,1269,2,1500,250,549 +Rsilicon-2026-05-09,baseline,E,1270,2,1500,250,549 +Rsilicon-2026-05-09,baseline,E,1271,2,1500,250,549 +Rsilicon-2026-05-09,baseline,E,1276,2,1500,250,549 +Rsilicon-2026-05-09,baseline,E,1293,2,1500,250,549 +Rsilicon-2026-05-09,baseline,E,1309,2,1500,250,549 +Rsilicon-2026-05-09,baseline,E,1326,2,1500,250,549 +Rsilicon-2026-05-09,baseline,E,1342,2,1500,250,549 +Rsilicon-2026-05-09,baseline,E,1359,2,1500,250,549 +Rsilicon-2026-05-09,baseline,E,1376,2,1500,250,549 +Rsilicon-2026-05-09,baseline,E,1392,2,1500,250,549 +Rsilicon-2026-05-09,baseline,E,1409,2,1500,250,549 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+Rsilicon-2026-05-09,baseline,E,1943,3,2000,250,293 +Rsilicon-2026-05-09,baseline,E,1965,3,2000,250,293 +Rsilicon-2026-05-09,baseline,E,1987,3,2000,250,293 +Rsilicon-2026-05-09,baseline,E,2009,3,2000,250,293 +Rsilicon-2026-05-09,baseline,E,2032,3,2000,250,293 +Rsilicon-2026-05-09,baseline,E,2054,3,2000,250,293 +Rsilicon-2026-05-09,baseline,E,2076,3,2000,250,293 +Rsilicon-2026-05-09,baseline,E,2098,3,2000,250,293 +Rsilicon-2026-05-09,baseline,E,2120,3,2000,250,293 +Rsilicon-2026-05-09,baseline,E,2142,3,2000,250,293 +Rsilicon-2026-05-09,baseline,E,2164,3,2000,250,293 +Rsilicon-2026-05-09,baseline,E,2186,3,2000,250,293 +Rsilicon-2026-05-09,baseline,E,2209,3,2000,250,293 +Rsilicon-2026-05-09,baseline,E,2231,3,2000,250,293 +Rsilicon-2026-05-09,baseline,E,2253,3,2000,250,549 +Rsilicon-2026-05-09,baseline,E,2275,3,2000,250,549 +Rsilicon-2026-05-09,baseline,E,2297,3,2000,250,549 +Rsilicon-2026-05-09,baseline,E,2319,3,2000,250,549 +Rsilicon-2026-05-09,baseline,E,2341,3,2000,250,549 +Rsilicon-2026-05-09,baseline,E,2363,3,2000,250,549 +Rsilicon-2026-05-09,baseline,E,2386,3,2000,250,549 +Rsilicon-2026-05-09,baseline,E,2408,3,2000,250,549 +Rsilicon-2026-05-09,baseline,E,2430,3,2000,250,549 +Rsilicon-2026-05-09,baseline,E,2452,3,2000,250,549 +Rsilicon-2026-05-09,baseline,E,2474,3,2000,250,549 +Rsilicon-2026-05-09,baseline,E,2496,3,2000,250,549 +# Rsilicon-2026-05-09 baseline: step 4/13 rpm=2000 period_us=83 ints=1000 count=1244 +Rsilicon-2026-05-09,baseline,D,step_4,419704758,90,159,254,136,71 +Rsilicon-2026-05-09,baseline,H,step_4,181051,24397,0 +Rsilicon-2026-05-09,baseline,E,2500,4,2500,250,1309 +Rsilicon-2026-05-09,baseline,E,2501,4,2500,250,549 +Rsilicon-2026-05-09,baseline,E,2502,4,2500,250,549 +Rsilicon-2026-05-09,baseline,E,2503,4,2500,250,549 +Rsilicon-2026-05-09,baseline,E,2504,4,2500,250,549 +Rsilicon-2026-05-09,baseline,E,2505,4,2500,250,549 +Rsilicon-2026-05-09,baseline,E,2506,4,2500,250,549 +Rsilicon-2026-05-09,baseline,E,2507,4,2500,250,549 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ints=1000 count=1536 +Rsilicon-2026-05-09,baseline,D,step_5,520706537,175,46,59,230,172 +Rsilicon-2026-05-09,baseline,H,step_5,181651,25654,0 +Rsilicon-2026-05-09,baseline,E,3500,5,3000,250,1309 +Rsilicon-2026-05-09,baseline,E,3501,5,3000,250,549 +Rsilicon-2026-05-09,baseline,E,3502,5,3000,250,549 +Rsilicon-2026-05-09,baseline,E,3503,5,3000,250,549 +Rsilicon-2026-05-09,baseline,E,3504,5,3000,250,549 +Rsilicon-2026-05-09,baseline,E,3505,5,3000,250,549 +Rsilicon-2026-05-09,baseline,E,3506,5,3000,250,549 +Rsilicon-2026-05-09,baseline,E,3507,5,3000,250,549 +Rsilicon-2026-05-09,baseline,E,3508,5,3000,250,293 +Rsilicon-2026-05-09,baseline,E,3509,5,3000,250,293 +Rsilicon-2026-05-09,baseline,E,3510,5,3000,250,549 +Rsilicon-2026-05-09,baseline,E,3511,5,3000,250,293 +Rsilicon-2026-05-09,baseline,E,3512,5,3000,250,293 +Rsilicon-2026-05-09,baseline,E,3513,5,3000,250,293 +Rsilicon-2026-05-09,baseline,E,3514,5,3000,250,293 +Rsilicon-2026-05-09,baseline,E,3515,5,3000,250,293 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+Rsilicon-2026-05-09,baseline,E,3763,5,3000,250,293 +Rsilicon-2026-05-09,baseline,E,3766,5,3000,250,293 +Rsilicon-2026-05-09,baseline,E,3799,5,3000,250,293 +Rsilicon-2026-05-09,baseline,E,3832,5,3000,250,293 +Rsilicon-2026-05-09,baseline,E,3866,5,3000,250,293 +Rsilicon-2026-05-09,baseline,E,3899,5,3000,250,293 +Rsilicon-2026-05-09,baseline,E,3932,5,3000,250,293 +Rsilicon-2026-05-09,baseline,E,3965,5,3000,250,293 +Rsilicon-2026-05-09,baseline,E,3998,5,3000,250,293 +Rsilicon-2026-05-09,baseline,E,4031,5,3000,250,293 +Rsilicon-2026-05-09,baseline,E,4064,5,3000,250,293 +Rsilicon-2026-05-09,baseline,E,4098,5,3000,250,293 +Rsilicon-2026-05-09,baseline,E,4131,5,3000,250,293 +Rsilicon-2026-05-09,baseline,E,4164,5,3000,250,293 +Rsilicon-2026-05-09,baseline,E,4197,5,3000,250,293 +Rsilicon-2026-05-09,baseline,E,4230,5,3000,250,293 +Rsilicon-2026-05-09,baseline,E,4263,5,3000,250,549 +Rsilicon-2026-05-09,baseline,E,4297,5,3000,250,549 +Rsilicon-2026-05-09,baseline,E,4330,5,3000,250,549 +Rsilicon-2026-05-09,baseline,E,4363,5,3000,250,549 +Rsilicon-2026-05-09,baseline,E,4396,5,3000,250,549 +Rsilicon-2026-05-09,baseline,E,4429,5,3000,250,549 +Rsilicon-2026-05-09,baseline,E,4462,5,3000,250,549 +Rsilicon-2026-05-09,baseline,E,4495,5,3000,250,549 +# Rsilicon-2026-05-09 baseline: step 6/13 rpm=3000 period_us=55 ints=1000 count=1823 +Rsilicon-2026-05-09,baseline,D,step_6,619994716,128,185,168,187,54 +Rsilicon-2026-05-09,baseline,H,step_6,180450,24761,0 +Rsilicon-2026-05-09,baseline,E,4500,6,4000,250,1309 +Rsilicon-2026-05-09,baseline,E,4501,6,4000,250,549 +Rsilicon-2026-05-09,baseline,E,4502,6,4000,250,549 +Rsilicon-2026-05-09,baseline,E,4503,6,4000,250,549 +Rsilicon-2026-05-09,baseline,E,4504,6,4000,250,549 +Rsilicon-2026-05-09,baseline,E,4505,6,4000,250,549 +Rsilicon-2026-05-09,baseline,E,4506,6,4000,250,549 +Rsilicon-2026-05-09,baseline,E,4507,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4508,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4509,6,4000,250,293 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+Rsilicon-2026-05-09,baseline,E,4548,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4549,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4550,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4551,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4552,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4553,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4554,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4555,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4556,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4557,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4558,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4559,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4560,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4561,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4562,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4563,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4564,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4565,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4566,6,4000,250,293 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+Rsilicon-2026-05-09,baseline,E,4586,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4587,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4588,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4589,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4590,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4591,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4592,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4593,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4594,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4595,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4596,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4597,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4598,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4599,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4600,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4601,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4602,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4603,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4604,6,4000,250,293 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+Rsilicon-2026-05-09,baseline,E,4624,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4625,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4626,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4627,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4628,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4629,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4630,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4631,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4632,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4633,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4634,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4635,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4636,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4637,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4638,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4639,6,4000,250,296 +Rsilicon-2026-05-09,baseline,E,4640,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4641,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4642,6,4000,250,293 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+Rsilicon-2026-05-09,baseline,E,4757,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4758,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4759,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4760,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4761,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4762,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4779,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4819,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4859,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4899,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4939,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,4978,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,5018,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,5058,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,5098,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,5137,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,5177,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,5217,6,4000,250,293 +Rsilicon-2026-05-09,baseline,E,5257,6,4000,250,549 +Rsilicon-2026-05-09,baseline,E,5296,6,4000,250,549 +Rsilicon-2026-05-09,baseline,E,5336,6,4000,250,549 +Rsilicon-2026-05-09,baseline,E,5376,6,4000,250,549 +Rsilicon-2026-05-09,baseline,E,5416,6,4000,250,549 +Rsilicon-2026-05-09,baseline,E,5455,6,4000,250,549 +Rsilicon-2026-05-09,baseline,E,5495,6,4000,250,549 +# Rsilicon-2026-05-09 baseline: step 7/13 rpm=4000 period_us=41 ints=1000 count=2105 +Rsilicon-2026-05-09,baseline,D,step_7,717590158,101,120,70,193,73 +Rsilicon-2026-05-09,baseline,H,step_7,188558,26194,0 +Rsilicon-2026-05-09,baseline,E,5500,7,5000,250,1309 +Rsilicon-2026-05-09,baseline,E,5501,7,5000,250,549 +Rsilicon-2026-05-09,baseline,E,5502,7,5000,250,549 +Rsilicon-2026-05-09,baseline,E,5503,7,5000,250,549 +Rsilicon-2026-05-09,baseline,E,5504,7,5000,250,549 +Rsilicon-2026-05-09,baseline,E,5505,7,5000,250,549 +Rsilicon-2026-05-09,baseline,E,5506,7,5000,250,293 +Rsilicon-2026-05-09,baseline,E,5507,7,5000,250,293 +Rsilicon-2026-05-09,baseline,E,5508,7,5000,250,293 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+Rsilicon-2026-05-09,baseline,E,6445,7,5000,250,549 +Rsilicon-2026-05-09,baseline,E,6494,7,5000,250,549 +# Rsilicon-2026-05-09 baseline: step 8/13 rpm=5000 period_us=33 ints=1000 count=2382 +Rsilicon-2026-05-09,baseline,D,step_8,813451137,125,147,27,235,29 +Rsilicon-2026-05-09,baseline,H,step_8,186456,25921,0 +Rsilicon-2026-05-09,baseline,E,6500,8,6000,250,1309 +Rsilicon-2026-05-09,baseline,E,6501,8,6000,250,549 +Rsilicon-2026-05-09,baseline,E,6502,8,6000,250,549 +Rsilicon-2026-05-09,baseline,E,6503,8,6000,250,549 +Rsilicon-2026-05-09,baseline,E,6504,8,6000,250,293 +Rsilicon-2026-05-09,baseline,E,6505,8,6000,250,293 +Rsilicon-2026-05-09,baseline,E,6506,8,6000,250,293 +Rsilicon-2026-05-09,baseline,E,6507,8,6000,250,293 +Rsilicon-2026-05-09,baseline,E,6508,8,6000,250,293 +Rsilicon-2026-05-09,baseline,E,6509,8,6000,250,293 +Rsilicon-2026-05-09,baseline,E,6510,8,6000,250,549 +Rsilicon-2026-05-09,baseline,E,6511,8,6000,250,293 +Rsilicon-2026-05-09,baseline,E,6512,8,6000,250,293 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+Rsilicon-2026-05-09,baseline,E,7474,10,8000,250,552 +Rsilicon-2026-05-09,baseline,E,7475,10,8000,250,549 +Rsilicon-2026-05-09,baseline,E,7476,10,8000,250,549 +Rsilicon-2026-05-09,baseline,E,7477,10,8000,250,552 +Rsilicon-2026-05-09,baseline,E,7478,10,8000,250,552 +Rsilicon-2026-05-09,baseline,E,7479,10,8000,250,552 +Rsilicon-2026-05-09,baseline,E,7480,10,8000,250,549 +Rsilicon-2026-05-09,baseline,E,7481,10,8000,250,549 +Rsilicon-2026-05-09,baseline,E,7482,10,8000,250,552 +Rsilicon-2026-05-09,baseline,E,7483,10,8000,250,552 +Rsilicon-2026-05-09,baseline,E,7484,10,8000,250,552 +Rsilicon-2026-05-09,baseline,E,7485,10,8000,250,549 +Rsilicon-2026-05-09,baseline,E,7486,10,8000,250,549 +Rsilicon-2026-05-09,baseline,E,7487,10,8000,250,552 +Rsilicon-2026-05-09,baseline,E,7488,10,8000,250,552 +Rsilicon-2026-05-09,baseline,E,7489,10,8000,250,549 +Rsilicon-2026-05-09,baseline,E,7490,10,8000,250,549 +Rsilicon-2026-05-09,baseline,E,7491,10,8000,250,552 +Rsilicon-2026-05-09,baseline,E,7492,10,8000,250,552 +Rsilicon-2026-05-09,baseline,E,7493,10,8000,250,552 +Rsilicon-2026-05-09,baseline,E,7494,10,8000,250,549 +Rsilicon-2026-05-09,baseline,E,7495,10,8000,250,549 +Rsilicon-2026-05-09,baseline,E,7496,10,8000,250,552 +Rsilicon-2026-05-09,baseline,E,7497,10,8000,250,552 +Rsilicon-2026-05-09,baseline,E,7498,10,8000,250,552 +Rsilicon-2026-05-09,baseline,E,7499,10,8000,250,549 +# Rsilicon-2026-05-09 baseline: step 11/13 rpm=8000 period_us=20 ints=200 count=3107 +Rsilicon-2026-05-09,baseline,D,step_11,1068426189,94,185,139,161,217 +Rsilicon-2026-05-09,baseline,H,step_11,167237,25136,0 +Rsilicon-2026-05-09,baseline,E,7500,11,9000,250,1309 +Rsilicon-2026-05-09,baseline,E,7501,11,9000,250,549 +Rsilicon-2026-05-09,baseline,E,7502,11,9000,250,549 +Rsilicon-2026-05-09,baseline,E,7503,11,9000,250,549 +Rsilicon-2026-05-09,baseline,E,7504,11,9000,250,552 +Rsilicon-2026-05-09,baseline,E,7505,11,9000,250,552 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+Rsilicon-2026-05-09,baseline,E,7596,11,9000,250,552 +Rsilicon-2026-05-09,baseline,E,7597,11,9000,250,552 +Rsilicon-2026-05-09,baseline,E,7598,11,9000,250,549 +Rsilicon-2026-05-09,baseline,E,7599,11,9000,250,549 +Rsilicon-2026-05-09,baseline,E,7600,11,9000,250,552 +Rsilicon-2026-05-09,baseline,E,7601,11,9000,250,552 +Rsilicon-2026-05-09,baseline,E,7602,11,9000,250,552 +Rsilicon-2026-05-09,baseline,E,7603,11,9000,250,549 +Rsilicon-2026-05-09,baseline,E,7604,11,9000,250,549 +Rsilicon-2026-05-09,baseline,E,7605,11,9000,250,552 +Rsilicon-2026-05-09,baseline,E,7606,11,9000,250,552 +Rsilicon-2026-05-09,baseline,E,7607,11,9000,250,549 +Rsilicon-2026-05-09,baseline,E,7608,11,9000,250,549 +Rsilicon-2026-05-09,baseline,E,7609,11,9000,250,552 +Rsilicon-2026-05-09,baseline,E,7610,11,9000,250,552 +Rsilicon-2026-05-09,baseline,E,7611,11,9000,250,552 +Rsilicon-2026-05-09,baseline,E,7612,11,9000,250,549 +Rsilicon-2026-05-09,baseline,E,7613,11,9000,250,549 +Rsilicon-2026-05-09,baseline,E,7614,11,9000,250,552 +Rsilicon-2026-05-09,baseline,E,7615,11,9000,250,552 +Rsilicon-2026-05-09,baseline,E,7616,11,9000,250,549 +Rsilicon-2026-05-09,baseline,E,7617,11,9000,250,549 +Rsilicon-2026-05-09,baseline,E,7618,11,9000,250,552 +Rsilicon-2026-05-09,baseline,E,7619,11,9000,250,552 +Rsilicon-2026-05-09,baseline,E,7620,11,9000,250,552 +Rsilicon-2026-05-09,baseline,E,7621,11,9000,250,549 +Rsilicon-2026-05-09,baseline,E,7622,11,9000,250,549 +Rsilicon-2026-05-09,baseline,E,7623,11,9000,250,552 +Rsilicon-2026-05-09,baseline,E,7624,11,9000,250,552 +Rsilicon-2026-05-09,baseline,E,7625,11,9000,250,552 +Rsilicon-2026-05-09,baseline,E,7626,11,9000,250,549 +Rsilicon-2026-05-09,baseline,E,7627,11,9000,250,549 +Rsilicon-2026-05-09,baseline,E,7628,11,9000,250,552 +Rsilicon-2026-05-09,baseline,E,7629,11,9000,250,552 +Rsilicon-2026-05-09,baseline,E,7630,11,9000,250,552 +Rsilicon-2026-05-09,baseline,E,7631,11,9000,250,549 +Rsilicon-2026-05-09,baseline,E,7632,11,9000,250,549 +Rsilicon-2026-05-09,baseline,E,7633,11,9000,250,552 +Rsilicon-2026-05-09,baseline,E,7634,11,9000,250,552 +Rsilicon-2026-05-09,baseline,E,7635,11,9000,250,552 +Rsilicon-2026-05-09,baseline,E,7636,11,9000,250,549 +Rsilicon-2026-05-09,baseline,E,7637,11,9000,250,549 +Rsilicon-2026-05-09,baseline,E,7638,11,9000,250,552 +Rsilicon-2026-05-09,baseline,E,7639,11,9000,250,552 +Rsilicon-2026-05-09,baseline,E,7640,11,9000,250,552 +Rsilicon-2026-05-09,baseline,E,7641,11,9000,250,549 +Rsilicon-2026-05-09,baseline,E,7642,11,9000,250,549 +Rsilicon-2026-05-09,baseline,E,7643,11,9000,250,552 +Rsilicon-2026-05-09,baseline,E,7644,11,9000,250,552 +Rsilicon-2026-05-09,baseline,E,7645,11,9000,250,552 +Rsilicon-2026-05-09,baseline,E,7646,11,9000,250,549 +Rsilicon-2026-05-09,baseline,E,7647,11,9000,250,549 +Rsilicon-2026-05-09,baseline,E,7648,11,9000,250,552 +Rsilicon-2026-05-09,baseline,E,7649,11,9000,2# step 12/13 rpm=9000 period_us=18 ints=150 count=3256 +Rsilicon-2026-05-09,baseline,D,step_12,1123263028,119,201,206,51,27 +Rsilicon-2026-05-09,baseline,H,step_12,151621,25263,0 +Rsilicon-2026-05-09,baseline,E,7650,12,10000,250,549 +Rsilicon-2026-05-09,baseline,E,7651,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7652,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7653,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7654,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7655,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7656,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7657,12,10000,250,549 +Rsilicon-2026-05-09,baseline,E,7658,12,10000,250,549 +Rsilicon-2026-05-09,baseline,E,7659,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7660,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7661,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7662,12,10000,250,549 +Rsilicon-2026-05-09,baseline,E,7663,12,10000,250,549 +Rsilicon-2026-05-09,baseline,E,7664,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7665,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7666,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7667,12,10000,250,549 +Rsilicon-2026-05-09,baseline,E,7668,12,10000,250,549 +Rsilicon-2026-05-09,baseline,E,7669,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7670,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7671,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7672,12,10000,250,549 +Rsilicon-2026-05-09,baseline,E,7673,12,10000,250,549 +Rsilicon-2026-05-09,baseline,E,7674,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7675,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7676,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7677,12,10000,250,549 +Rsilicon-2026-05-09,baseline,E,7678,12,10000,250,549 +Rsilicon-2026-05-09,baseline,E,7679,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7680,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7681,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7682,12,10000,250,549 +Rsilicon-2026-05-09,baseline,E,7683,12,10000,250,549 +Rsilicon-2026-05-09,baseline,E,7684,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7685,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7686,12,10000,250,549 +Rsilicon-2026-05-09,baseline,E,7687,12,10000,250,549 +Rsilicon-2026-05-09,baseline,E,7688,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7689,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7690,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7691,12,10000,250,549 +Rsilicon-2026-05-09,baseline,E,7692,12,10000,250,549 +Rsilicon-2026-05-09,baseline,E,7693,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7694,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7695,12,10000,250,549 +Rsilicon-2026-05-09,baseline,E,7696,12,10000,250,549 +Rsilicon-2026-05-09,baseline,E,7697,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7698,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7699,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7700,12,10000,250,549 +Rsilicon-2026-05-09,baseline,E,7701,12,10000,250,549 +Rsilicon-2026-05-09,baseline,E,7702,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7703,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7704,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7705,12,10000,250,549 +Rsilicon-2026-05-09,baseline,E,7706,12,10000,250,549 +Rsilicon-2026-05-09,baseline,E,7707,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7708,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7709,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7710,12,10000,250,549 +Rsilicon-2026-05-09,baseline,E,7711,12,10000,250,549 +Rsilicon-2026-05-09,baseline,E,7712,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7713,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7714,12,10000,250,549 +Rsilicon-2026-05-09,baseline,E,7715,12,10000,250,549 +Rsilicon-2026-05-09,baseline,E,7716,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7717,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7718,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7719,12,10000,250,549 +Rsilicon-2026-05-09,baseline,E,7720,12,10000,250,556 +Rsilicon-2026-05-09,baseline,E,7721,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7722,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7723,12,10000,250,549 +Rsilicon-2026-05-09,baseline,E,7724,12,10000,250,549 +Rsilicon-2026-05-09,baseline,E,7725,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7726,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7727,12,10000,250,549 +Rsilicon-2026-05-09,baseline,E,7728,12,10000,250,549 +Rsilicon-2026-05-09,baseline,E,7729,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7730,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7731,12,10000,250,549 +Rsilicon-2026-05-09,baseline,E,7732,12,10000,250,549 +Rsilicon-2026-05-09,baseline,E,7733,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7734,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7735,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7736,12,10000,250,549 +Rsilicon-2026-05-09,baseline,E,7737,12,10000,250,549 +Rsilicon-2026-05-09,baseline,E,7738,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7739,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7740,12,10000,250,549 +Rsilicon-2026-05-09,baseline,E,7741,12,10000,250,549 +Rsilicon-2026-05-09,baseline,E,7742,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7743,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7744,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7745,12,10000,250,549 +Rsilicon-2026-05-09,baseline,E,7746,12,10000,250,549 +Rsilicon-2026-05-09,baseline,E,7747,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7748,12,10000,250,552 +Rsilicon-2026-05-09,baseline,E,7749,12# step 13/13 rpm=10000 period_us=16 ints=100 count=3356 +Rsilicon-2026-05-09,baseline,D,step_13,1161852462,9,43,206,1,193 +Rsilicon-2026-05-09,baseline,H,step_13,124294,26614,0 +Rsilicon-2026-05-09,baseline,D,end,1163017821,109,215,206,39,126 +Rsilicon-2026-05-09,baseline,H,end,30000,29276,0 +M,Rsilicon-2026-05-09,baseline,drops,4393 +M,Rsilicon-2026-05-09,baseline,samples,3357 +M,Rsilicon-2026-05-09,baseline,END diff --git a/benches/engine_control/silicon/runs/2026-05-09-nucleo_g474re-06515098-baseline-systick/firmware.elf b/benches/engine_control/silicon/runs/2026-05-09-nucleo_g474re-06515098-baseline-systick/firmware.elf new file mode 100755 index 00000000..77a2ffcf Binary files /dev/null and b/benches/engine_control/silicon/runs/2026-05-09-nucleo_g474re-06515098-baseline-systick/firmware.elf differ diff --git a/benches/engine_control/silicon/runs/2026-05-09-nucleo_g474re-06515098-baseline-systick/firmware.elf.sha256 b/benches/engine_control/silicon/runs/2026-05-09-nucleo_g474re-06515098-baseline-systick/firmware.elf.sha256 new file mode 100644 index 00000000..ab1432e6 --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-05-09-nucleo_g474re-06515098-baseline-systick/firmware.elf.sha256 @@ -0,0 +1 @@ +aa43d889ae6fbcb17dc66ecf6296fe9d1cdcb5617fc236e7a093f0fdd6ddedbf firmware.elf diff --git a/benches/engine_control/silicon/runs/2026-05-09-nucleo_g474re-06515098-baseline-systick/manifest.txt b/benches/engine_control/silicon/runs/2026-05-09-nucleo_g474re-06515098-baseline-systick/manifest.txt new file mode 100644 index 00000000..5e0bdd95 --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-05-09-nucleo_g474re-06515098-baseline-systick/manifest.txt @@ -0,0 +1,23 @@ +# Silicon-anchor manifest +# Produced by benches/engine_control/silicon/capture.sh +captured_at: 2026-05-09T19:56:37Z +board: nucleo_g474re +variant: baseline +tick_source: systick +sweep: long +flash_runner: openocd +gale_sha: 06515098b9813fde77dd250e30f9dd998ccf5be9 +gale_status: 3 uncommitted file(s) +host: Darwin 25.3.0 arm64 +rustc: rustc 1.94.1 (e408947bf 2026-03-25) +cargo: cargo 1.94.1 (29ea6fb6a 2026-03-24) +west: West version: v1.5.0 +zephyr_base: /Volumes/Home/git/pulseengine/zephyr +zephyr_sha: fc4d89c118fc1d0ff0ad31906a4fa4bd252c9ced +sdk_dir: /Volumes/Home/zephyr-sdk/zephyr-sdk-1.0.1 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+E,803,1,1000,250,549 +E,814,1,1000,250,549 +E,826,1,1000,250,549 +E,837,1,1000,250,549 +E,848,1,1000,250,549 +E,859,1,1000,250,549 +E,870,1,1000,250,549 +E,882,1,1000,250,549 +E,893,1,1000,250,549 +E,904,1,1000,250,549 +E,915,1,1000,250,549 +E,926,1,1000,250,549 +E,938,1,1000,250,549 +E,949,1,1000,250,549 +E,960,1,1000,250,549 +E,971,1,1000,250,549 +E,983,1,1000,250,549 +E,994,1# step 2/13 rpm=1000 period_us=166 ints=500 count=655 +D,step_2,216021134,220,123,42,58,230 +H,step_2,172042,23927,0 +,1000,250,549 +E,1000,2,1500,250,549 +E,1001,2,1500,250,549 +E,1002,2,1500,250,549 +E,1003,2,1500,250,549 +E,1004,2,1500,250,549 +E,1005,2,1500,250,549 +E,1006,2,1500,250,549 +E,1007,2,1500,250,549 +E,1008,2,1500,250,549 +E,1009,2,1500,250,549 +E,1010,2,1500,250,549 +E,1011,2,1500,250,549 +E,1012,2,1500,250,549 +E,1013,2,1500,250,549 +E,1014,2,1500,250,549 +E,1015,2,1500,250,549 +E,1016,2,1500,250,293 +E,1017,2,1500,250,293 +E,1018,2,1500,250,293 +E,1019,2,1500,250,293 +E,1020,2,1500,250,549 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+E,3744,5,3000,250,293 +E,3745,5,3000,250,293 +E,3746,5,3000,250,293 +E,3747,5,3000,250,293 +E,3748,5,3000,250,293 +E,3749,5,3000,250,293 +E,3750,5,3000,250,293 +E,3751,5,3000,250,549 +E,3752,5,3000,250,293 +E,3753,5,3000,250,293 +E,3754,5,3000,250,293 +E,3755,5,3000,250,293 +E,3756,5,3000,250,293 +E,3757,5,3000,250,293 +E,3758,5,3000,250,293 +E,3759,5,3000,250,293 +E,3760,5,3000,250,293 +E,3761,5,3000,250,293 +E,3762,5,3000,250,293 +E,3763,5,3000,250,293 +E,3766,5,3000,250,293 +E,3799,5,3000,250,293 +E,3832,5,3000,250,293 +E,3866,5,3000,250,293 +E,3899,5,3000,250,293 +E,3932,5,3000,250,293 +E,3965,5,3000,250,293 +E,3998,5,3000,250,293 +E,4031,5,3000,250,293 +E,4064,5,3000,250,293 +E,4098,5,3000,250,293 +E,4131,5,3000,250,293 +E,4164,5,3000,250,293 +E,4197,5,3000,250,293 +E,4230,5,3000,250,293 +E,4263,5,3000,250,549 +E,4297,5,3000,250,549 +E,4330,5,3000,250,549 +E,4363,5,3000,250,549 +E,4396,5,3000,250,549 +E,4429,5,3000,250,549 +E,4462,5,3000,250,549 +E,4495,5,3000,250,549 +# step 6/13 rpm=3000 period_us=55 ints=1000 count=1823 +D,step_6,619994716,128,185,168,187,54 +H,step_6,180450,24761,0 +E,4500,6,4000,250,1309 +E,4501,6,4000,250,549 +E,4502,6,4000,250,549 +E,4503,6,4000,250,549 +E,4504,6,4000,250,549 +E,4505,6,4000,250,549 +E,4506,6,4000,250,549 +E,4507,6,4000,250,293 +E,4508,6,4000,250,293 +E,4509,6,4000,250,293 +E,4510,6,4000,250,293 +E,4511,6,4000,250,293 +E,4512,6,4000,250,293 +E,4513,6,4000,250,293 +E,4514,6,4000,250,293 +E,4515,6,4000,250,293 +E,4516,6,4000,250,293 +E,4517,6,4000,250,293 +E,4518,6,4000,250,293 +E,4519,6,4000,250,293 +E,4520,6,4000,250,293 +E,4521,6,4000,250,293 +E,4522,6,4000,250,293 +E,4523,6,4000,250,293 +E,4524,6,4000,250,293 +E,4525,6,4000,250,293 +E,4526,6,4000,250,293 +E,4527,6,4000,250,293 +E,4528,6,4000,250,549 +E,4529,6,4000,250,293 +E,4530,6,4000,250,293 +E,4531,6,4000,250,293 +E,4532,6,4000,250,293 +E,4533,6,4000,250,293 +E,4534,6,4000,250,293 +E,4535,6,4000,250,293 +E,4536,6,4000,250,293 +E,4537,6,4000,250,293 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+E,4710,6,4000,250,293 +E,4711,6,4000,250,293 +E,4712,6,4000,250,293 +E,4713,6,4000,250,293 +E,4714,6,4000,250,293 +E,4715,6,4000,250,293 +E,4716,6,4000,250,293 +E,4717,6,4000,250,293 +E,4718,6,4000,250,293 +E,4719,6,4000,250,293 +E,4720,6,4000,250,293 +E,4721,6,4000,250,293 +E,4722,6,4000,250,293 +E,4723,6,4000,250,293 +E,4724,6,4000,250,293 +E,4725,6,4000,250,293 +E,4726,6,4000,250,293 +E,4727,6,4000,250,549 +E,4728,6,4000,250,293 +E,4729,6,4000,250,293 +E,4730,6,4000,250,293 +E,4731,6,4000,250,293 +E,4732,6,4000,250,293 +E,4733,6,4000,250,293 +E,4734,6,4000,250,293 +E,4735,6,4000,250,293 +E,4736,6,4000,250,293 +E,4737,6,4000,250,293 +E,4738,6,4000,250,293 +E,4739,6,4000,250,293 +E,4740,6,4000,250,293 +E,4741,6,4000,250,293 +E,4742,6,4000,250,293 +E,4743,6,4000,250,293 +E,4744,6,4000,250,293 +E,4745,6,4000,250,549 +E,4746,6,4000,250,293 +E,4747,6,4000,250,293 +E,4748,6,4000,250,293 +E,4749,6,4000,250,293 +E,4750,6,4000,250,293 +E,4751,6,4000,250,293 +E,4752,6,4000,250,293 +E,4753,6,4000,250,293 +E,4754,6,4000,250,293 +E,4755,6,4000,250,293 +E,4756,6,4000,250,293 +E,4757,6,4000,250,293 +E,4758,6,4000,250,293 +E,4759,6,4000,250,293 +E,4760,6,4000,250,293 +E,4761,6,4000,250,293 +E,4762,6,4000,250,293 +E,4779,6,4000,250,293 +E,4819,6,4000,250,293 +E,4859,6,4000,250,293 +E,4899,6,4000,250,293 +E,4939,6,4000,250,293 +E,4978,6,4000,250,293 +E,5018,6,4000,250,293 +E,5058,6,4000,250,293 +E,5098,6,4000,250,293 +E,5137,6,4000,250,293 +E,5177,6,4000,250,293 +E,5217,6,4000,250,293 +E,5257,6,4000,250,549 +E,5296,6,4000,250,549 +E,5336,6,4000,250,549 +E,5376,6,4000,250,549 +E,5416,6,4000,250,549 +E,5455,6,4000,250,549 +E,5495,6,4000,250,549 +# step 7/13 rpm=4000 period_us=41 ints=1000 count=2105 +D,step_7,717590158,101,120,70,193,73 +H,step_7,188558,26194,0 +E,5500,7,5000,250,1309 +E,5501,7,5000,250,549 +E,5502,7,5000,250,549 +E,5503,7,5000,250,549 +E,5504,7,5000,250,549 +E,5505,7,5000,250,549 +E,5506,7,5000,250,293 +E,5507,7,5000,250,293 +E,5508,7,5000,250,293 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+E,5724,7,5000,250,293 +E,5725,7,5000,250,293 +E,5726,7,5000,250,549 +E,5727,7,5000,250,293 +E,5728,7,5000,250,293 +E,5729,7,5000,250,293 +E,5730,7,5000,250,293 +E,5731,7,5000,250,293 +E,5732,7,5000,250,293 +E,5733,7,5000,250,293 +E,5734,7,5000,250,549 +E,5735,7,5000,250,293 +E,5736,7,5000,250,293 +E,5737,7,5000,250,293 +E,5738,7,5000,250,293 +E,5739,7,5000,250,293 +E,5740,7,5000,250,293 +E,5741,7,5000,250,293 +E,5742,7,5000,250,293 +E,5743,7,5000,250,293 +E,5744,7,5000,250,293 +E,5745,7,5000,250,293 +E,5746,7,5000,250,293 +E,5747,7,5000,250,293 +E,5748,7,5000,250,293 +E,5749,7,5000,250,293 +E,5750,7,5000,250,293 +E,5751,7,5000,250,293 +E,5752,7,5000,250,293 +E,5753,7,5000,250,293 +E,5754,7,5000,250,293 +E,5755,7,5000,250,293 +E,5756,7,5000,250,293 +E,5757,7,5000,250,293 +E,5758,7,5000,250,293 +E,5759,7,5000,250,293 +E,5760,7,5000,250,293 +E,5761,7,5000,250,293 +E,5799,7,5000,250,293 +E,5849,7,5000,250,293 +E,5899,7,5000,250,293 +E,5948,7,5000,250,293 +E,5998,7,5000,250,293 +E,6048,7,5000,250,293 +E,6097,7,5000,250,293 +E,6147,7,5000,250,293 +E,6196,7,5000,250,293 +E,6246,7,5000,250,549 +E,6296,7,5000,250,549 +E,6345,7,5000,250,549 +E,6395,7,5000,250,549 +E,6445,7,5000,250,549 +E,6494,7,5000,250,549 +# step 8/13 rpm=5000 period_us=33 ints=1000 count=2382 +D,step_8,813451137,125,147,27,235,29 +H,step_8,186456,25921,0 +E,6500,8,6000,250,1309 +E,6501,8,6000,250,549 +E,6502,8,6000,250,549 +E,6503,8,6000,250,549 +E,6504,8,6000,250,293 +E,6505,8,6000,250,293 +E,6506,8,6000,250,293 +E,6507,8,6000,250,293 +E,6508,8,6000,250,293 +E,6509,8,6000,250,293 +E,6510,8,6000,250,549 +E,6511,8,6000,250,293 +E,6512,8,6000,250,293 +E,6513,8,6000,250,293 +E,6514,8,6000,250,293 +E,6515,8,6000,250,293 +E,6516,8,6000,250,293 +E,6517,8,6000,250,293 +E,6518,8,6000,250,293 +E,6519,8,6000,250,293 +E,6520,8,6000,250,293 +E,6521,8,6000,250,293 +E,6522,8,6000,250,293 +E,6523,8,6000,250,293 +E,6524,8,6000,250,293 +E,6525,8,6000,250,293 +E,6526,8,6000,250,293 +E,6527,8,6000,250,293 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+E,6571,8,6000,250,293 +E,6572,8,6000,250,293 +E,6573,8,6000,250,293 +E,6574,8,6000,250,293 +E,6575,8,6000,250,293 +E,6576,8,6000,250,549 +E,6577,8,6000,250,293 +E,6578,8,6000,250,293 +E,6579,8,6000,250,293 +E,6580,8,6000,250,293 +E,6581,8,6000,250,293 +E,6582,8,6000,250,293 +E,6583,8,6000,250,293 +E,6584,8,6000,250,293 +E,6585,8,6000,250,293 +E,6586,8,6000,250,293 +E,6587,8,6000,250,293 +E,6588,8,6000,250,293 +E,6589,8,6000,250,293 +E,6590,8,6000,250,293 +E,6591,8,6000,250,293 +E,6592,8,6000,250,293 +E,6593,8,6000,250,293 +E,6594,8,6000,250,293 +E,6595,8,6000,250,293 +E,6596,8,6000,250,293 +E,6597,8,6000,250,293 +E,6598,8,6000,250,293 +E,6599,8,6000,250,293 +E,6600,8,6000,250,293 +E,6601,8,6000,250,293 +E,6602,8,6000,250,293 +E,6603,8,6000,250,293 +E,6604,8,6000,250,293 +E,6605,8,6000,250,293 +E,6606,8,6000,250,293 +E,6607,8,6000,250,293 +E,6608,8,6000,250,293 +E,6609,8,6000,250,293 +E,6610,8,6000,250,293 +E,6611,8,6000,250,293 +E,6612,8,6000,250,293 +E,6613,8,6000,250,293 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+E,6700,8,6000,250,293 +E,6701,8,6000,250,293 +E,6702,8,6000,250,293 +E,6703,8,6000,250,293 +E,6704,8,6000,250,293 +E,6705,8,6000,250,293 +E,6706,8,6000,250,293 +E,6707,8,6000,250,293 +E,6708,8,6000,250,293 +E,6709,8,6000,250,549 +E,6710,8,6000,250,293 +E,6711,8,6000,250,293 +E,6712,8,6000,250,293 +E,6713,8,6000,250,293 +E,6714,8,6000,250,293 +E,6715,8,6000,250,293 +E,6716,8,6000,250,293 +E,6717,8,6000,250,293 +E,6718,8,6000,250,293 +E,6719,8,6000,250,293 +E,6720,8,6000,250,293 +E,6721,8,6000,250,293 +E,6722,8,6000,250,293 +E,6723,8,6000,250,293 +E,6724,8,6000,250,293 +E,6725,8,6000,250,293 +E,6726,8,6000,250,293 +E,6727,8,6000,250,293 +E,6728,8,6000,250,293 +E,6729,8,6000,250,293 +E,6730,8,6000,250,293 +E,6731,8,6000,250,293 +E,6732,8,6000,250,293 +E,6733,8,6000,250,293 +E,6734,8,6000,250,293 +E,6735,8,6000,250,293 +E,6736,8,6000,250,293 +E,6737,8,6000,250,293 +E,6738,8,6000,250,293 +E,6739,8,6000,250,293 +E,6740,8,6000,250,293 +E,6741,8,6000,250,293 +E,6742,8,6000,250,293 +E,6743,8,6000,250,293 +E,6744,8,6000,250,549 +E,6745,8,6000,250,549 +E,6746,8,6000,250,549 +E,6747,8,6000,250,549 +E,6748,8,6000,250,549 +E,6749,8,6000,250,549 +E,6750,8,6000,250,549 +E,6751,8,6000,250,549 +E,6752,8,6000,250,549 +E,6753,8,6000,250,549 +E,6754,8,6000,250,549 +E,6755,8,6000,250,549 +E,6756,8,6000,250,549 +E,6757,8,6000,250,549 +E,6758,8,6000,250,549 +E,6759,8,6000,250,549 +E,6766,8,6000,250,549 +E,6832,8,6000,250,549 +E,6899,8,6000,250,549 +E,6965,8,6000,250,549 +# step 9/13 rpm=6000 period_us=27 ints=500 count=2646 +D,step_9,904991388,204,195,214,50,199 +H,step_9,178648,25921,0 +E,7000,9,7000,250,1309 +E,7001,9,7000,250,549 +E,7002,9,7000,250,549 +E,7003,9,7000,250,549 +E,7004,9,7000,250,293 +E,7005,9,7000,250,293 +E,7006,9,7000,250,293 +E,7007,9,7000,250,293 +E,7008,9,7000,250,293 +E,7009,9,7000,250,293 +E,7010,9,7000,250,549 +E,7011,9,7000,250,293 +E,7012,9,7000,250,293 +E,7013,9,7000,250,293 +E,7014,9,7000,250,293 +E,7015,9,7000,250,293 +E,7016,9,7000,250,293 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+E,7232,9,7000,250,549 +E,7233,9,7000,250,549 +E,7234,9,7000,250,549 +E,7235,9,7000,250,549 +E,7236,9,7000,250,549 +E,7237,9,7000,250,549 +E,7238,9,7000,250,549 +E,7239,9,7000,250,549 +E,7240,9,7000,250,549 +E,7241,9,7000,250,549 +E,7242,9,7000,250,549 +E,7243,9,7000,250,549 +E,7244,9,7000,250,549 +E,7245,9,7000,250,549 +E,7246,9,7000,250,549 +E,7247,9,7000,250,549 +E,7248,9,7000,250,549 +E,7249,9,7000,250,549 +E,7250,9,7000,250,549 +E,7251,9,7000,250,549 +E,7252,9,7000,250,549 +E,7253,9,7000,250,549 +E,7254,9,7000,250,549 +E,7255,9,7000,250,549 +E,7256,9,7000,250,549 +E,7257,9,7000,250,549 +E,7258,9,7000,250,549 +E,7259,9,7000,250,549 +E,7266,9,7000,250,549 +# step 10/13 rpm=7000 period_us=23 ints=300 count=2907 +D,step_10,995696938,29,38,36,152,52 +H,step_10,180750,26333,0 +E,7300,10,8000,250,1309 +E,7301,10,8000,250,552 +E,7302,10,8000,250,549 +E,7303,10,8000,250,549 +E,7304,10,8000,250,552 +E,7305,10,8000,250,552 +E,7306,10,8000,250,549 +E,7307,10,8000,250,549 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+E,7349,10,8000,250,549 +E,7350,10,8000,250,549 +E,7351,10,8000,250,552 +E,7352,10,8000,250,552 +E,7353,10,8000,250,552 +E,7354,10,8000,250,549 +E,7355,10,8000,250,549 +E,7356,10,8000,250,552 +E,7357,10,8000,250,552 +E,7358,10,8000,250,552 +E,7359,10,8000,250,549 +E,7360,10,8000,250,549 +E,7361,10,8000,250,552 +E,7362,10,8000,250,552 +E,7363,10,8000,250,552 +E,7364,10,8000,250,549 +E,7365,10,8000,250,549 +E,7366,10,8000,250,552 +E,7367,10,8000,250,552 +E,7368,10,8000,250,552 +E,7369,10,8000,250,549 +E,7370,10,8000,250,549 +E,7371,10,8000,250,552 +E,7372,10,8000,250,552 +E,7373,10,8000,250,552 +E,7374,10,8000,250,549 +E,7375,10,8000,250,549 +E,7376,10,8000,250,552 +E,7377,10,8000,250,552 +E,7378,10,8000,250,552 +E,7379,10,8000,250,549 +E,7380,10,8000,250,549 +E,7381,10,8000,250,552 +E,7382,10,8000,250,552 +E,7383,10,8000,250,549 +E,7384,10,8000,250,549 +E,7385,10,8000,250,552 +E,7386,10,8000,250,552 +E,7387,10,8000,250,552 +E,7388,10,8000,250,549 +E,7389,10,8000,250,549 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+E,7431,10,8000,250,549 +E,7432,10,8000,250,549 +E,7433,10,8000,250,552 +E,7434,10,8000,250,552 +E,7435,10,8000,250,552 +E,7436,10,8000,250,549 +E,7437,10,8000,250,549 +E,7438,10,8000,250,552 +E,7439,10,8000,250,552 +E,7440,10,8000,250,552 +E,7441,10,8000,250,549 +E,7442,10,8000,250,549 +E,7443,10,8000,250,552 +E,7444,10,8000,250,552 +E,7445,10,8000,250,552 +E,7446,10,8000,250,549 +E,7447,10,8000,250,549 +E,7448,10,8000,250,552 +E,7449,10,8000,250,552 +E,7450,10,8000,250,549 +E,7451,10,8000,250,549 +E,7452,10,8000,250,552 +E,7453,10,8000,250,552 +E,7454,10,8000,250,552 +E,7455,10,8000,250,549 +E,7456,10,8000,250,549 +E,7457,10,8000,250,552 +E,7458,10,8000,250,552 +E,7459,10,8000,250,552 +E,7460,10,8000,250,549 +E,7461,10,8000,250,549 +E,7462,10,8000,250,552 +E,7463,10,8000,250,552 +E,7464,10,8000,250,559 +E,7465,10,8000,250,549 +E,7466,10,8000,250,549 +E,7467,10,8000,250,552 +E,7468,10,8000,250,552 +E,7469,10,8000,250,552 +E,7470,10,8000,250,549 +E,7471,10,8000,250,549 +E,7472,10,8000,250,552 +E,7473,10,8000,250,552 +E,7474,10,8000,250,552 +E,7475,10,8000,250,549 +E,7476,10,8000,250,549 +E,7477,10,8000,250,552 +E,7478,10,8000,250,552 +E,7479,10,8000,250,552 +E,7480,10,8000,250,549 +E,7481,10,8000,250,549 +E,7482,10,8000,250,552 +E,7483,10,8000,250,552 +E,7484,10,8000,250,552 +E,7485,10,8000,250,549 +E,7486,10,8000,250,549 +E,7487,10,8000,250,552 +E,7488,10,8000,250,552 +E,7489,10,8000,250,549 +E,7490,10,8000,250,549 +E,7491,10,8000,250,552 +E,7492,10,8000,250,552 +E,7493,10,8000,250,552 +E,7494,10,8000,250,549 +E,7495,10,8000,250,549 +E,7496,10,8000,250,552 +E,7497,10,8000,250,552 +E,7498,10,8000,250,552 +E,7499,10,8000,250,549 +# step 11/13 rpm=8000 period_us=20 ints=200 count=3107 +D,step_11,1068426189,94,185,139,161,217 +H,step_11,167237,25136,0 +E,7500,11,9000,250,1309 +E,7501,11,9000,250,549 +E,7502,11,9000,250,549 +E,7503,11,9000,250,549 +E,7504,11,9000,250,552 +E,7505,11,9000,250,552 +E,7506,11,9000,250,549 +E,7507,11,9000,250,549 +E,7508,11,9000,250,552 +E,7509,11,9000,250,552 +E,7510,11,9000,250,549 +E,7511,11,9000,250,549 +E,7512,11,9000,250,552 +E,7513,11,9000,250,552 +E,7514,11,9000,250,552 +E,7515,11,9000,250,549 +E,7516,11,9000,250,549 +E,7517,11,9000,250,552 +E,7518,11,9000,250,552 +E,7519,11,9000,250,552 +E,7520,11,9000,250,549 +E,7521,11,9000,250,549 +E,7522,11,9000,250,552 +E,7523,11,9000,250,552 +E,7524,11,9000,250,552 +E,7525,11,9000,250,549 +E,7526,11,9000,250,549 +E,7527,11,9000,250,552 +E,7528,11,9000,250,552 +E,7529,11,9000,250,552 +E,7530,11,9000,250,549 +E,7531,11,9000,250,549 +E,7532,11,9000,250,552 +E,7533,11,9000,250,552 +E,7534,11,9000,250,552 +E,7535,11,9000,250,549 +E,7536,11,9000,250,549 +E,7537,11,9000,250,552 +E,7538,11,9000,250,552 +E,7539,11,9000,250,552 +E,7540,11,9000,250,549 +E,7541,11,9000,250,549 +E,7542,11,9000,250,552 +E,7543,11,9000,250,552 +E,7544,11,9000,250,549 +E,7545,11,9000,250,549 +E,7546,11,9000,250,552 +E,7547,11,9000,250,552 +E,7548,11,9000,250,552 +E,7549,11,9000,250,549 +E,7550,11,9000,250,549 +E,7551,11,9000,250,552 +E,7552,11,9000,250,552 +E,7553,11,9000,250,552 +E,7554,11,9000,250,549 +E,7555,11,9000,250,549 +E,7556,11,9000,250,552 +E,7557,11,9000,250,552 +E,7558,11,9000,250,552 +E,7559,11,9000,250,549 +E,7560,11,9000,250,549 +E,7561,11,9000,250,552 +E,7562,11,9000,250,552 +E,7563,11,9000,250,552 +E,7564,11,9000,250,549 +E,7565,11,9000,250,549 +E,7566,11,9000,250,552 +E,7567,11,9000,250,552 +E,7568,11,9000,250,552 +E,7569,11,9000,250,549 +E,7570,11,9000,250,549 +E,7571,11,9000,250,552 +E,7572,11,9000,250,552 +E,7573,11,9000,250,552 +E,7574,11,9000,250,549 +E,7575,11,9000,250,549 +E,7576,11,9000,250,552 +E,7577,11,9000,250,552 +E,7578,11,9000,250,552 +E,7579,11,9000,250,549 +E,7580,11,9000,250,549 +E,7581,11,9000,250,552 +E,7582,11,9000,250,552 +E,7583,11,9000,250,549 +E,7584,11,9000,250,549 +E,7585,11,9000,250,552 +E,7586,11,9000,250,552 +E,7587,11,9000,250,552 +E,7588,11,9000,250,549 +E,7589,11,9000,250,549 +E,7590,11,9000,250,552 +E,7591,11,9000,250,552 +E,7592,11,9000,250,552 +E,7593,11,9000,250,549 +E,7594,11,9000,250,549 +E,7595,11,9000,250,552 +E,7596,11,9000,250,552 +E,7597,11,9000,250,552 +E,7598,11,9000,250,549 +E,7599,11,9000,250,549 +E,7600,11,9000,250,552 +E,7601,11,9000,250,552 +E,7602,11,9000,250,552 +E,7603,11,9000,250,549 +E,7604,11,9000,250,549 +E,7605,11,9000,250,552 +E,7606,11,9000,250,552 +E,7607,11,9000,250,549 +E,7608,11,9000,250,549 +E,7609,11,9000,250,552 +E,7610,11,9000,250,552 +E,7611,11,9000,250,552 +E,7612,11,9000,250,549 +E,7613,11,9000,250,549 +E,7614,11,9000,250,552 +E,7615,11,9000,250,552 +E,7616,11,9000,250,549 +E,7617,11,9000,250,549 +E,7618,11,9000,250,552 +E,7619,11,9000,250,552 +E,7620,11,9000,250,552 +E,7621,11,9000,250,549 +E,7622,11,9000,250,549 +E,7623,11,9000,250,552 +E,7624,11,9000,250,552 +E,7625,11,9000,250,552 +E,7626,11,9000,250,549 +E,7627,11,9000,250,549 +E,7628,11,9000,250,552 +E,7629,11,9000,250,552 +E,7630,11,9000,250,552 +E,7631,11,9000,250,549 +E,7632,11,9000,250,549 +E,7633,11,9000,250,552 +E,7634,11,9000,250,552 +E,7635,11,9000,250,552 +E,7636,11,9000,250,549 +E,7637,11,9000,250,549 +E,7638,11,9000,250,552 +E,7639,11,9000,250,552 +E,7640,11,9000,250,552 +E,7641,11,9000,250,549 +E,7642,11,9000,250,549 +E,7643,11,9000,250,552 +E,7644,11,9000,250,552 +E,7645,11,9000,250,552 +E,7646,11,9000,250,549 +E,7647,11,9000,250,549 +E,7648,11,9000,250,552 +E,7649,11,9000,2# step 12/13 rpm=9000 period_us=18 ints=150 count=3256 +D,step_12,1123263028,119,201,206,51,27 +H,step_12,151621,25263,0 +50,552 +E,7650,12,10000,250,549 +E,7651,12,10000,250,552 +E,7652,12,10000,250,552 +E,7653,12,10000,250,552 +E,7654,12,10000,250,552 +E,7655,12,10000,250,552 +E,7656,12,10000,250,552 +E,7657,12,10000,250,549 +E,7658,12,10000,250,549 +E,7659,12,10000,250,552 +E,7660,12,10000,250,552 +E,7661,12,10000,250,552 +E,7662,12,10000,250,549 +E,7663,12,10000,250,549 +E,7664,12,10000,250,552 +E,7665,12,10000,250,552 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+E,7746,12,10000,250,549 +E,7747,12,10000,250,552 +E,7748,12,10000,250,552 +E,7749,12# step 13/13 rpm=10000 period_us=16 ints=100 count=3356 +D,step_13,1161852462,9,43,206,1,193 +H,step_13,124294,26614,0 +,10000,250,549 +D,end,1163017821,109,215,206,39,126 +H,end,30000,29276,0 +drops,4393 +samples,3357 +=== END === diff --git a/benches/engine_control/silicon/runs/2026-05-09-nucleo_g474re-06515098-gale-systick/events.csv b/benches/engine_control/silicon/runs/2026-05-09-nucleo_g474re-06515098-gale-systick/events.csv new file mode 100644 index 00000000..1d726faa --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-05-09-nucleo_g474re-06515098-gale-systick/events.csv @@ -0,0 +1,3320 @@ +Rsilicon-2026-05-09,gale,E,19,0,500,250,585 +Rsilicon-2026-05-09,gale,E,20,0,500,250,585 +Rsilicon-2026-05-09,gale,E,21,0,500,250,585 +Rsilicon-2026-05-09,gale,E,22,0,500,250,585 +Rsilicon-2026-05-09,gale,E,23,0,500,250,585 +Rsilicon-2026-05-09,gale,E,24,0,500,250,585 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+Rsilicon-2026-05-09,gale,E,7466,10,8000,250,585 +Rsilicon-2026-05-09,gale,E,7467,10,8000,250,588 +Rsilicon-2026-05-09,gale,E,7468,10,8000,250,588 +Rsilicon-2026-05-09,gale,E,7469,10,8000,250,585 +Rsilicon-2026-05-09,gale,E,7470,10,8000,250,585 +Rsilicon-2026-05-09,gale,E,7471,10,8000,250,588 +Rsilicon-2026-05-09,gale,E,7472,10,8000,250,585 +Rsilicon-2026-05-09,gale,E,7473,10,8000,250,585 +Rsilicon-2026-05-09,gale,E,7474,10,8000,250,588 +Rsilicon-2026-05-09,gale,E,7475,10,8000,250,585 +Rsilicon-2026-05-09,gale,E,7476,10,8000,250,588 +Rsilicon-2026-05-09,gale,E,7477,10,8000,250,588 +Rsilicon-2026-05-09,gale,E,7478,10,8000,250,585 +Rsilicon-2026-05-09,gale,E,7479,10,8000,250,588 +Rsilicon-2026-05-09,gale,E,7480,10,8000,250,588 +Rsilicon-2026-05-09,gale,E,7481,10,8000,250,585 +Rsilicon-2026-05-09,gale,E,7482,10,8000,250,585 +Rsilicon-2026-05-09,gale,E,7483,10,8000,250,588 +Rsilicon-2026-05-09,gale,E,7484,10,8000,250,585 +Rsilicon-2026-05-09,gale,E,7485,10,8000,250,585 +Rsilicon-2026-05-09,gale,E,7486,10,8000,250,588 +Rsilicon-2026-05-09,gale,E,7487,10,8000,250,585 +Rsilicon-2026-05-09,gale,E,7488,10,8000,250,588 +Rsilicon-2026-05-09,gale,E,7489,10,8000,250,588 +Rsilicon-2026-05-09,gale,E,7490,10,8000,250,585 +Rsilicon-2026-05-09,gale,E,7491,10,8000,250,585 +Rsilicon-2026-05-09,gale,E,7492,10,8000,250,588 +Rsilicon-2026-05-09,gale,E,7493,10,8000,250,585 +Rsilicon-2026-05-09,gale,E,7494,10,8000,250,585 +Rsilicon-2026-05-09,gale,E,7495,10,8000,250,588 +Rsilicon-2026-05-09,gale,E,7496,10,8000,250,585 +Rsilicon-2026-05-09,gale,E,7497,10,8000,250,588 +Rsilicon-2026-05-09,gale,E,7498,10,8000,250,588 +Rsilicon-2026-05-09,gale,E,7499,10,8000,250,585 +# Rsilicon-2026-05-09 gale: step 11/13 rpm=8000 period_us=20 ints=200 count=3107 +Rsilicon-2026-05-09,gale,D,step_11,1068327588,24,233,68,142,4 +Rsilicon-2026-05-09,gale,H,step_11,173843,27196,0 +Rsilicon-2026-05-09,gale,E,7500,11,9000,250,1350 +Rsilicon-2026-05-09,gale,E,7501,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7502,11,9000,252,582 +Rsilicon-2026-05-09,gale,E,7503,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7504,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7505,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7506,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7507,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7508,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7509,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7510,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7511,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7512,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7513,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7514,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7515,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7516,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7517,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7518,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7519,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7520,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7521,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7522,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7523,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7524,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7525,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7526,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7527,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7528,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7529,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7530,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7531,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7532,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7533,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7534,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7535,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7536,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7537,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7538,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7539,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7540,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7541,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7542,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7543,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7544,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7545,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7546,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7547,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7548,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7549,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7550,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7551,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7552,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7553,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7554,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7555,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7556,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7557,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7558,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7559,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7560,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7561,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7562,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7563,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7564,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7565,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7566,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7567,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7568,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7569,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7570,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7571,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7572,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7573,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7574,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7575,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7576,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7577,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7578,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7579,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7580,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7581,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7582,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7583,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7584,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7585,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7586,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7587,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7588,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7589,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7590,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7591,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7592,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7593,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7594,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7595,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7596,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7597,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7598,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7599,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7600,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7601,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7602,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7603,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7604,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7605,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7606,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7607,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7608,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7609,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7610,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7611,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7612,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7613,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7614,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7615,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7616,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7617,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7618,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7619,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7620,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7621,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7622,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7623,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7624,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7625,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7626,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7627,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7628,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7629,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7630,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7631,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7632,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7633,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7634,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7635,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7636,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7637,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7638,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7639,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7640,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7641,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7642,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7643,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7644,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7645,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7646,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7647,11,9000,250,588 +Rsilicon-2026-05-09,gale,E,7648,11,9000,250,585 +Rsilicon-2026-05-09,gale,E,7649,11,9000,2# step 12/13 rpm=9000 period_us=18 ints=150 count=3256 +Rsilicon-2026-05-09,gale,D,step_12,1123120158,25,183,129,253,113 +Rsilicon-2026-05-09,gale,H,step_12,157927,27048,0 +Rsilicon-2026-05-09,gale,E,7650,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7651,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7652,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7653,12,10000,250,588 +Rsilicon-2026-05-09,gale,E,7654,12,10000,250,588 +Rsilicon-2026-05-09,gale,E,7655,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7656,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7657,12,10000,250,588 +Rsilicon-2026-05-09,gale,E,7658,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7659,12,10000,250,588 +Rsilicon-2026-05-09,gale,E,7660,12,10000,250,588 +Rsilicon-2026-05-09,gale,E,7661,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7662,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7663,12,10000,250,588 +Rsilicon-2026-05-09,gale,E,7664,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7665,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7666,12,10000,250,588 +Rsilicon-2026-05-09,gale,E,7667,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7668,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7669,12,10000,250,588 +Rsilicon-2026-05-09,gale,E,7670,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7671,12,10000,250,588 +Rsilicon-2026-05-09,gale,E,7672,12,10000,250,588 +Rsilicon-2026-05-09,gale,E,7673,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7674,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7675,12,10000,250,588 +Rsilicon-2026-05-09,gale,E,7676,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7677,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7678,12,10000,250,588 +Rsilicon-2026-05-09,gale,E,7679,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7680,12,10000,250,588 +Rsilicon-2026-05-09,gale,E,7681,12,10000,250,588 +Rsilicon-2026-05-09,gale,E,7682,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7683,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7684,12,10000,250,588 +Rsilicon-2026-05-09,gale,E,7685,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7686,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7687,12,10000,250,588 +Rsilicon-2026-05-09,gale,E,7688,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7689,12,10000,250,588 +Rsilicon-2026-05-09,gale,E,7690,12,10000,250,588 +Rsilicon-2026-05-09,gale,E,7691,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7692,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7693,12,10000,250,588 +Rsilicon-2026-05-09,gale,E,7694,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7695,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7696,12,10000,250,588 +Rsilicon-2026-05-09,gale,E,7697,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7698,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7699,12,10000,250,588 +Rsilicon-2026-05-09,gale,E,7700,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7701,12,10000,250,588 +Rsilicon-2026-05-09,gale,E,7702,12,10000,250,588 +Rsilicon-2026-05-09,gale,E,7703,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7704,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7705,12,10000,250,588 +Rsilicon-2026-05-09,gale,E,7706,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7707,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7708,12,10000,250,588 +Rsilicon-2026-05-09,gale,E,7709,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7710,12,10000,250,588 +Rsilicon-2026-05-09,gale,E,7711,12,10000,250,588 +Rsilicon-2026-05-09,gale,E,7712,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7713,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7714,12,10000,250,588 +Rsilicon-2026-05-09,gale,E,7715,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7716,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7717,12,10000,250,588 +Rsilicon-2026-05-09,gale,E,7718,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7719,12,10000,250,588 +Rsilicon-2026-05-09,gale,E,7720,12,10000,250,594 +Rsilicon-2026-05-09,gale,E,7721,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7722,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7723,12,10000,250,588 +Rsilicon-2026-05-09,gale,E,7724,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7725,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7726,12,10000,250,588 +Rsilicon-2026-05-09,gale,E,7727,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7728,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7729,12,10000,250,588 +Rsilicon-2026-05-09,gale,E,7730,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7731,12,10000,250,588 +Rsilicon-2026-05-09,gale,E,7732,12,10000,250,588 +Rsilicon-2026-05-09,gale,E,7733,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7734,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7735,12,10000,250,588 +Rsilicon-2026-05-09,gale,E,7736,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7737,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7738,12,10000,250,588 +Rsilicon-2026-05-09,gale,E,7739,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7740,12,10000,250,588 +Rsilicon-2026-05-09,gale,E,7741,12,10000,250,588 +Rsilicon-2026-05-09,gale,E,7742,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7743,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7744,12,10000,250,588 +Rsilicon-2026-05-09,gale,E,7745,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7746,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7747,12,10000,250,588 +Rsilicon-2026-05-09,gale,E,7748,12,10000,250,585 +Rsilicon-2026-05-09,gale,E,7749,12# step 13/13 rpm=10000 period_us=16 ints=100 count=3356 +Rsilicon-2026-05-09,gale,D,step_13,1161724344,86,32,129,146,119 +Rsilicon-2026-05-09,gale,H,step_13,141111,26333,0 +Rsilicon-2026-05-09,gale,D,end,1162934134,46,200,129,60,65 +Rsilicon-2026-05-09,gale,H,end,27898,30533,0 +M,Rsilicon-2026-05-09,gale,drops,4393 +M,Rsilicon-2026-05-09,gale,samples,3357 +M,Rsilicon-2026-05-09,gale,END diff --git a/benches/engine_control/silicon/runs/2026-05-09-nucleo_g474re-06515098-gale-systick/firmware.elf b/benches/engine_control/silicon/runs/2026-05-09-nucleo_g474re-06515098-gale-systick/firmware.elf new file mode 100755 index 00000000..417bcbb7 Binary files /dev/null and b/benches/engine_control/silicon/runs/2026-05-09-nucleo_g474re-06515098-gale-systick/firmware.elf differ diff --git a/benches/engine_control/silicon/runs/2026-05-09-nucleo_g474re-06515098-gale-systick/firmware.elf.sha256 b/benches/engine_control/silicon/runs/2026-05-09-nucleo_g474re-06515098-gale-systick/firmware.elf.sha256 new file mode 100644 index 00000000..0bbda65b --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-05-09-nucleo_g474re-06515098-gale-systick/firmware.elf.sha256 @@ -0,0 +1 @@ +ae621742dc6c951dbf5754b20e62c4e92ae46069bf29c9895ce5d10878ca311c firmware.elf diff --git a/benches/engine_control/silicon/runs/2026-05-09-nucleo_g474re-06515098-gale-systick/manifest.txt b/benches/engine_control/silicon/runs/2026-05-09-nucleo_g474re-06515098-gale-systick/manifest.txt new file mode 100644 index 00000000..54f17ee7 --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-05-09-nucleo_g474re-06515098-gale-systick/manifest.txt @@ -0,0 +1,23 @@ +# Silicon-anchor manifest +# Produced by benches/engine_control/silicon/capture.sh +captured_at: 2026-05-09T19:56:53Z +board: nucleo_g474re +variant: gale +tick_source: systick +sweep: long +flash_runner: openocd +gale_sha: 06515098b9813fde77dd250e30f9dd998ccf5be9 +gale_status: 4 uncommitted file(s) +host: Darwin 25.3.0 arm64 +rustc: rustc 1.94.1 (e408947bf 2026-03-25) +cargo: cargo 1.94.1 (29ea6fb6a 2026-03-24) +west: West version: v1.5.0 +zephyr_base: /Volumes/Home/git/pulseengine/zephyr +zephyr_sha: fc4d89c118fc1d0ff0ad31906a4fa4bd252c9ced +sdk_dir: /Volumes/Home/zephyr-sdk/zephyr-sdk-1.0.1 +elf_sha256: ae621742dc6c951dbf5754b20e62c4e92ae46069bf29c9895ce5d10878ca311c +csv_sha256: bdaaf70e55465c4121582e1a92317af1a3b949bcd53cc285b5aa85c78c5f183a +csv_bytes: 76782 +csv_event_lines: 3279 +serial_port: /dev/cu.usbmodem132203 +capture_timeout_s: 1800 diff --git a/benches/engine_control/silicon/runs/2026-05-09-nucleo_g474re-06515098-gale-systick/output.csv b/benches/engine_control/silicon/runs/2026-05-09-nucleo_g474re-06515098-gale-systick/output.csv new file mode 100644 index 00000000..933bf4fe --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-05-09-nucleo_g474re-06515098-gale-systick/output.csv @@ -0,0 +1,3324 @@ +50,585 +E,19,0,500,250,585 +E,20,0,500,250,585 +E,21,0,500,250,585 +E,22,0,500,250,585 +E,23,0,500,250,585 +E,24,0,500,250,585 +E,25,0,500,250,58 �b�b���b���b�ª +E,85,0,500,250,293 +E,86,0,500,250,293 +E,87,0,500,250,293 +E,88,0,500,250,293 +E,89,0,500,250,585 +E,90,0,500,250,293 +E,91,0,500,250,293 +E,92,0,500,250,293 +E,93,0,500,250,293 +E,94,0,500,250,585 +E,95,0,500,250,293 +E,96,0,500,250,293 +E,97,0,500,250,293 +E,98,0,500,250,293 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+E,396,0,500,250,585 +E,401,0,500,250,585 +E,406,0,500,250,585 +E,411,0,500,250,585 +E,416,0,500,250,585 +E,421,0,500,250,585 +E,426,0,500,250,585 +E,431,0,500,250,585 +E,437,0,500,250,585 +E,442,0,500,250,585 +E,447,0,500,250,585 +E,452,0,500,250,585 +E,457,0,500,250,585 +E,462,0,500,250,585 +E,467,0,500,250,585 +E,472,0,500,250,585 +E,477,0,500,250,585 +E,482,0,500,250,585 +E,488,0,500,250,585 +E,493,0,500,250,585 +E,498,0,500,250,585 +# step 1/13 rpm=500 period_us=333 ints=500 count=355 +D,step_1,116747128,164,139,163,43,94 +H,step_1,179549,25263,0 +E,500,1,1000,250,1350 +E,501,1,1000,250,585 +E,502,1,1000,250,585 +E,503,1,1000,250,585 +E,504,1,1000,250,585 +E,505,1,1000,250,585 +E,506,1,1000,250,585 +E,507,1,1000,250,585 +E,508,1,1000,250,585 +E,509,1,1000,250,585 +E,510,1,1000,250,585 +E,511,1,1000,250,585 +E,512,1,1000,250,585 +E,513,1,1000,250,585 +E,514,1,1000,250,585 +E,515,1,1000,250,585 +E,516,1,1000,250,585 +E,517,1,1000,250,585 +E,518,1,1000,250,585 +E,519,1,1000,250,585 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+E,1492,2,1500,250,585 +# step 3/13 rpm=1500 period_us=111 ints=500 count=942 +D,step_3,315262053,63,140,80,194,203 +H,step_3,178348,24517,0 +E,1500,3,2000,250,1350 +E,1501,3,2000,250,585 +E,1502,3,2000,250,585 +E,1503,3,2000,250,585 +E,1504,3,2000,250,585 +E,1505,3,2000,250,585 +E,1506,3,2000,250,585 +E,1507,3,2000,250,585 +E,1508,3,2000,250,585 +E,1509,3,2000,250,585 +E,1510,3,2000,250,585 +E,1511,3,2000,250,585 +E,1512,3,2000,250,585 +E,1513,3,2000,250,293 +E,1514,3,2000,250,293 +E,1515,3,2000,250,293 +E,1516,3,2000,250,293 +E,1517,3,2000,250,293 +E,1518,3,2000,250,293 +E,1519,3,2000,250,293 +E,1520,3,2000,250,293 +E,1521,3,2000,250,293 +E,1522,3,2000,250,293 +E,1523,3,2000,250,293 +E,1524,3,2000,250,293 +E,1525,3,2000,250,293 +E,1526,3,2000,250,293 +E,1527,3,2000,250,293 +E,1528,3,2000,250,293 +E,1529,3,2000,250,293 +E,1530,3,2000,250,293 +E,1531,3,2000,250,293 +E,1532,3,2000,250,293 +E,1533,3,2000,250,293 +E,1534,3,2000,250,293 +E,1535,3,2000,250,293 +E,1536,3,2000,250,293 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+E,2363,3,2000,250,585 +E,2386,3,2000,250,585 +E,2408,3,2000,250,585 +E,2430,3,2000,250,585 +E,2452,3,2000,250,585 +E,2474,3,2000,250,585 +E,2496,3,2000,250,585 +# step 4/13 rpm=2000 period_us=83 ints=1000 count=1244 +D,step_4,419691384,86,111,154,107,72 +H,step_4,188858,26057,0 +E,2500,4,2500,250,1350 +E,2501,4,2500,250,585 +E,2502,4,2500,250,585 +E,2503,4,2500,250,585 +E,2504,4,2500,250,585 +E,2505,4,2500,250,585 +E,2506,4,2500,250,585 +E,2507,4,2500,250,585 +E,2508,4,2500,250,585 +E,2509,4,2500,250,585 +E,2510,4,2500,250,293 +E,2511,4,2500,250,293 +E,2512,4,2500,250,293 +E,2513,4,2500,250,293 +E,2514,4,2500,250,293 +E,2515,4,2500,250,293 +E,2516,4,2500,250,293 +E,2517,4,2500,250,293 +E,2518,4,2500,250,293 +E,2519,4,2500,250,293 +E,2520,4,2500,250,293 +E,2521,4,2500,250,293 +E,2522,4,2500,250,293 +E,2523,4,2500,250,293 +E,2524,4,2500,250,293 +E,2525,4,2500,250,293 +E,2526,4,2500,250,293 +E,2527,4,2500,250,293 +E,2528,4,2500,250,293 +E,2529,4,2500,250,585 +E,2530,4,2500,250,293 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+E,3439,4,2500,250,585 +E,3467,4,2500,250,585 +E,3496,4,2500,250,591 +# step 5/13 rpm=2500 period_us=66 ints=1000 count=1536 +D,step_5,520694025,2,4,58,41,232 +H,step_5,183753,25921,0 +E,3500,5,3000,250,1350 +E,3501,5,3000,250,585 +E,3502,5,3000,250,585 +E,3503,5,3000,250,585 +E,3504,5,3000,250,585 +E,3505,5,3000,250,585 +E,3506,5,3000,250,585 +E,3507,5,3000,250,585 +E,3508,5,3000,250,293 +E,3509,5,3000,250,293 +E,3510,5,3000,250,585 +E,3511,5,3000,250,293 +E,3512,5,3000,250,293 +E,3513,5,3000,250,293 +E,3514,5,3000,250,293 +E,3515,5,3000,250,293 +E,3516,5,3000,250,293 +E,3517,5,3000,250,293 +E,3518,5,3000,250,293 +E,3519,5,3000,250,585 +E,3520,5,3000,250,293 +E,3521,5,3000,250,293 +E,3522,5,3000,250,293 +E,3523,5,3000,250,293 +E,3524,5,3000,250,293 +E,3525,5,3000,250,293 +E,3526,5,3000,250,293 +E,3527,5,3000,250,293 +E,3528,5,3000,250,585 +E,3529,5,3000,250,293 +E,3530,5,3000,250,293 +E,3531,5,3000,250,293 +E,3532,5,3000,250,293 +E,3533,5,3000,250,293 +E,3534,5,3000,250,293 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+E,3707,5,3000,250,293 +E,3708,5,3000,250,293 +E,3709,5,3000,250,293 +E,3710,5,3000,250,293 +E,3711,5,3000,250,293 +E,3712,5,3000,250,293 +E,3713,5,3000,250,293 +E,3714,5,3000,250,293 +E,3715,5,3000,250,293 +E,3716,5,3000,250,293 +E,3717,5,3000,250,293 +E,3718,5,3000,250,293 +E,3719,5,3000,250,293 +E,3720,5,3000,250,293 +E,3721,5,3000,250,293 +E,3722,5,3000,250,293 +E,3723,5,3000,250,293 +E,3724,5,3000,250,293 +E,3725,5,3000,250,293 +E,3726,5,3000,250,293 +E,3727,5,3000,250,585 +E,3728,5,3000,250,293 +E,3729,5,3000,250,293 +E,3730,5,3000,250,293 +E,3731,5,3000,250,293 +E,3732,5,3000,250,293 +E,3733,5,3000,250,293 +E,3734,5,3000,250,293 +E,3735,5,3000,250,293 +E,3736,5,3000,250,293 +E,3737,5,3000,250,293 +E,3738,5,3000,250,293 +E,3739,5,3000,250,293 +E,3740,5,3000,250,293 +E,3741,5,3000,250,293 +E,3742,5,3000,250,293 +E,3743,5,3000,250,293 +E,3744,5,3000,250,293 +E,3745,5,3000,250,293 +E,3746,5,3000,250,293 +E,3747,5,3000,250,293 +E,3748,5,3000,250,293 +E,3749,5,3000,250,293 +E,3750,5,3000,250,293 +E,3751,5,3000,250,585 +E,3752,5,3000,250,293 +E,3753,5,3000,250,293 +E,3754,5,3000,250,293 +E,3755,5,3000,250,293 +E,3756,5,3000,250,293 +E,3757,5,3000,250,293 +E,3758,5,3000,250,293 +E,3759,5,3000,250,293 +E,3760,5,3000,250,293 +E,3761,5,3000,250,293 +E,3762,5,3000,250,293 +E,3763,5,3000,250,293 +E,3766,5,3000,250,293 +E,3799,5,3000,250,293 +E,3832,5,3000,250,293 +E,3865,5,3000,250,293 +E,3899,5,3000,250,293 +E,3932,5,3000,250,293 +E,3965,5,3000,250,293 +E,3998,5,3000,250,293 +E,4031,5,3000,250,293 +E,4064,5,3000,250,293 +E,4098,5,3000,250,293 +E,4131,5,3000,250,293 +E,4164,5,3000,250,293 +E,4197,5,3000,250,293 +E,4230,5,3000,250,293 +E,4263,5,3000,250,585 +E,4296,5,3000,250,585 +E,4330,5,3000,250,585 +E,4363,5,3000,250,585 +E,4396,5,3000,250,585 +E,4429,5,3000,250,585 +E,4462,5,3000,250,585 +E,4495,5,3000,250,585 +# step 6/13 rpm=3000 period_us=55 ints=1000 count=1823 +D,step_6,619923551,210,67,44,170,147 +H,step_6,190960,26473,0 +E,4500,6,4000,250,1350 +E,4501,6,4000,250,585 +E,4502,6,4000,250,585 +E,4503,6,4000,250,585 +E,4504,6,4000,250,585 +E,4505,6,4000,250,585 +E,4506,6,4000,250,585 +E,4507,6,4000,250,293 +E,4508,6,4000,250,293 +E,4509,6,4000,250,293 +E,4510,6,4000,250,293 +E,4511,6,4000,250,293 +E,4512,6,4000,250,293 +E,4513,6,4000,250,293 +E,4514,6,4000,250,293 +E,4515,6,4000,250,293 +E,4516,6,4000,250,293 +E,4517,6,4000,250,293 +E,4518,6,4000,250,293 +E,4519,6,4000,250,293 +E,4520,6,4000,250,293 +E,4521,6,4000,250,293 +E,4522,6,4000,250,293 +E,4523,6,4000,250,293 +E,4524,6,4000,250,293 +E,4525,6,4000,250,293 +E,4526,6,4000,250,293 +E,4527,6,4000,250,293 +E,4528,6,4000,250,585 +E,4529,6,4000,250,293 +E,4530,6,4000,250,293 +E,4531,6,4000,250,293 +E,4532,6,4000,250,293 +E,4533,6,4000,250,293 +E,4534,6,4000,250,293 +E,4535,6,4000,250,293 +E,4536,6,4000,250,293 +E,4537,6,4000,250,293 +E,4538,6,4000,250,296 +E,4539,6,4000,250,293 +E,4540,6,4000,250,293 +E,4541,6,4000,250,293 +E,4542,6,4000,250,293 +E,4543,6,4000,250,293 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+E,4716,6,4000,250,293 +E,4717,6,4000,250,293 +E,4718,6,4000,250,293 +E,4719,6,4000,250,293 +E,4720,6,4000,250,293 +E,4721,6,4000,250,293 +E,4722,6,4000,250,293 +E,4723,6,4000,250,293 +E,4724,6,4000,250,293 +E,4725,6,4000,250,293 +E,4726,6,4000,250,293 +E,4727,6,4000,250,585 +E,4728,6,4000,250,293 +E,4729,6,4000,250,293 +E,4730,6,4000,250,293 +E,4731,6,4000,250,293 +E,4732,6,4000,250,293 +E,4733,6,4000,250,293 +E,4734,6,4000,250,293 +E,4735,6,4000,250,293 +E,4736,6,4000,250,293 +E,4737,6,4000,250,293 +E,4738,6,4000,250,293 +E,4739,6,4000,250,293 +E,4740,6,4000,250,293 +E,4741,6,4000,250,293 +E,4742,6,4000,250,293 +E,4743,6,4000,250,293 +E,4744,6,4000,250,585 +E,4745,6,4000,250,293 +E,4746,6,4000,250,293 +E,4747,6,4000,250,293 +E,4748,6,4000,250,293 +E,4749,6,4000,250,293 +E,4750,6,4000,250,293 +E,4751,6,4000,250,293 +E,4752,6,4000,250,293 +E,4753,6,4000,250,293 +E,4754,6,4000,250,293 +E,4755,6,4000,250,293 +E,4756,6,4000,250,293 +E,4757,6,4000,250,293 +E,4758,6,4000,250,293 +E,4759,6,4000,250,293 +E,4760,6,4000,250,293 +E,4761,6,4000,250,293 +E,4762,6,4000,250,293 +E,4779,6,4000,250,293 +E,4819,6,4000,250,293 +E,4859,6,4000,250,293 +E,4899,6,4000,250,293 +E,4938,6,4000,250,293 +E,4978,6,4000,250,293 +E,5018,6,4000,250,293 +E,5058,6,4000,250,293 +E,5097,6,4000,250,293 +E,5137,6,4000,250,293 +E,5177,6,4000,250,293 +E,5217,6,4000,250,293 +E,5256,6,4000,250,585 +E,5296,6,4000,250,585 +E,5336,6,4000,250,585 +E,5376,6,4000,250,585 +E,5415,6,4000,250,585 +E,5455,6,4000,250,585 +E,5495,6,4000,250,585 +# step 7/13 rpm=4000 period_us=41 ints=1000 count=2105 +D,step_7,717506226,48,237,62,65,187 +H,step_7,184054,25787,0 +E,5500,7,5000,250,1350 +E,5501,7,5000,250,585 +E,5502,7,5000,250,585 +E,5503,7,5000,250,585 +E,5504,7,5000,250,585 +E,5505,7,5000,250,585 +E,5506,7,5000,250,293 +E,5507,7,5000,250,293 +E,5508,7,5000,250,293 +E,5509,7,5000,250,293 +E,5510,7,5000,250,293 +E,5511,7,5000,250,293 +E,5512,7,5000,250,293 +E,5513,7,5000,250,293 +E,5514,7,5000,250,293 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+E,5730,7,5000,250,293 +E,5731,7,5000,250,293 +E,5732,7,5000,250,293 +E,5733,7,5000,250,293 +E,5734,7,5000,250,585 +E,5735,7,5000,250,293 +E,5736,7,5000,250,293 +E,5737,7,5000,250,293 +E,5738,7,5000,250,293 +E,5739,7,5000,250,293 +E,5740,7,5000,250,293 +E,5741,7,5000,250,293 +E,5742,7,5000,250,293 +E,5743,7,5000,250,293 +E,5744,7,5000,250,293 +E,5745,7,5000,250,293 +E,5746,7,5000,250,293 +E,5747,7,5000,250,293 +E,5748,7,5000,250,293 +E,5749,7,5000,250,293 +E,5750,7,5000,250,293 +E,5751,7,5000,250,293 +E,5752,7,5000,250,293 +E,5753,7,5000,250,293 +E,5754,7,5000,250,293 +E,5755,7,5000,250,293 +E,5756,7,5000,250,293 +E,5757,7,5000,250,293 +E,5758,7,5000,250,293 +E,5759,7,5000,250,293 +E,5760,7,5000,250,293 +E,5761,7,5000,250,293 +E,5799,7,5000,250,293 +E,5849,7,5000,250,293 +E,5899,7,5000,250,293 +E,5948,7,5000,250,293 +E,5998,7,5000,250,293 +E,6047,7,5000,250,293 +E,6097,7,5000,250,293 +E,6147,7,5000,250,293 +E,6196,7,5000,250,293 +E,6246,7,5000,250,585 +E,6296,7,5000,250,585 +E,6345,7,5000,250,585 +E,6395,7,5000,250,585 +E,6445,7,5000,250,585 +E,6494,7,5000,250,585 +# step 8/13 rpm=5000 period_us=33 ints=1000 count=2382 +D,step_8,813352722,60,149,190,243,138 +H,step_8,187957,26902,0 +E,6500,8,6000,250,1350 +E,6501,8,6000,250,585 +E,6502,8,6000,250,588 +E,6503,8,6000,250,585 +E,6504,8,6000,250,293 +E,6505,8,6000,250,293 +E,6506,8,6000,250,293 +E,6507,8,6000,250,293 +E,6508,8,6000,250,293 +E,6509,8,6000,250,293 +E,6510,8,6000,250,585 +E,6511,8,6000,250,293 +E,6512,8,6000,250,293 +E,6513,8,6000,250,293 +E,6514,8,6000,250,293 +E,6515,8,6000,250,293 +E,6516,8,6000,250,293 +E,6517,8,6000,250,293 +E,6518,8,6000,250,293 +E,6519,8,6000,250,293 +E,6520,8,6000,250,293 +E,6521,8,6000,250,293 +E,6522,8,6000,250,293 +E,6523,8,6000,250,293 +E,6524,8,6000,250,293 +E,6525,8,6000,250,293 +E,6526,8,6000,250,293 +E,6527,8,6000,250,293 +E,6528,8,6000,250,293 +E,6529,8,6000,250,293 +E,6530,8,6000,250,293 +E,6531,8,6000,250,293 +E,6532,8,6000,250,293 +E,6533,8,6000,250,293 +E,6534,8,6000,250,293 +E,6535,8,6000,250,293 +E,6536,8,6000,250,293 +E,6537,8,6000,250,293 +E,6538,8,6000,250,293 +E,6539,8,6000,250,293 +E,6540,8,6000,250,293 +E,6541,8,6000,250,293 +E,6542,8,6000,250,293 +E,6543,8,6000,250,293 +E,6544,8,6000,250,293 +E,6545,8,6000,250,293 +E,6546,8,6000,250,293 +E,6547,8,6000,250,293 +E,6548,8,6000,250,293 +E,6549,8,6000,250,293 +E,6550,8,6000,250,293 +E,6551,8,6000,250,293 +E,6552,8,6000,250,293 +E,6553,8,6000,250,293 +E,6554,8,6000,250,293 +E,6555,8,6000,250,293 +E,6556,8,6000,250,293 +E,6557,8,6000,250,293 +E,6558,8,6000,250,293 +E,6559,8,6000,250,293 +E,6560,8,6000,250,293 +E,6561,8,6000,250,293 +E,6562,8,6000,250,293 +E,6563,8,6000,250,293 +E,6564,8,6000,250,293 +E,6565,8,6000,250,293 +E,6566,8,6000,250,293 +E,6567,8,6000,250,293 +E,6568,8,6000,250,293 +E,6569,8,6000,250,293 +E,6570,8,6000,250,293 +E,6571,8,6000,250,293 +E,6572,8,6000,250,293 +E,6573,8,6000,250,293 +E,6574,8,6000,250,293 +E,6575,8,6000,250,293 +E,6576,8,6000,250,585 +E,6577,8,6000,250,293 +E,6578,8,6000,250,293 +E,6579,8,6000,250,293 +E,6580,8,6000,250,293 +E,6581,8,6000,250,293 +E,6582,8,6000,250,293 +E,6583,8,6000,250,293 +E,6584,8,6000,250,293 +E,6585,8,6000,250,293 +E,6586,8,6000,250,293 +E,6587,8,6000,250,293 +E,6588,8,6000,250,293 +E,6589,8,6000,250,293 +E,6590,8,6000,250,293 +E,6591,8,6000,250,293 +E,6592,8,6000,250,293 +E,6593,8,6000,250,293 +E,6594,8,6000,250,293 +E,6595,8,6000,250,293 +E,6596,8,6000,250,293 +E,6597,8,6000,250,293 +E,6598,8,6000,250,293 +E,6599,8,6000,250,293 +E,6600,8,6000,250,293 +E,6601,8,6000,250,293 +E,6602,8,6000,250,293 +E,6603,8,6000,250,293 +E,6604,8,6000,250,293 +E,6605,8,6000,250,293 +E,6606,8,6000,250,293 +E,6607,8,6000,250,293 +E,6608,8,6000,250,293 +E,6609,8,6000,250,293 +E,6610,8,6000,250,293 +E,6611,8,6000,250,293 +E,6612,8,6000,250,293 +E,6613,8,6000,250,293 +E,6614,8,6000,250,293 +E,6615,8,6000,250,293 +E,6616,8,6000,250,293 +E,6617,8,6000,250,293 +E,6618,8,6000,250,293 +E,6619,8,6000,250,293 +E,6620,8,6000,250,293 +E,6621,8,6000,250,293 +E,6622,8,6000,250,293 +E,6623,8,6000,250,293 +E,6624,8,6000,250,293 +E,6625,8,6000,250,293 +E,6626,8,6000,250,293 +E,6627,8,6000,250,293 +E,6628,8,6000,250,293 +E,6629,8,6000,250,293 +E,6630,8,6000,250,293 +E,6631,8,6000,250,293 +E,6632,8,6000,250,293 +E,6633,8,6000,250,293 +E,6634,8,6000,250,293 +E,6635,8,6000,250,293 +E,6636,8,6000,250,293 +E,6637,8,6000,250,293 +E,6638,8,6000,250,293 +E,6639,8,6000,250,293 +E,6640,8,6000,250,293 +E,6641,8,6000,250,293 +E,6642,8,6000,250,293 +E,6643,8,6000,250,585 +E,6644,8,6000,250,293 +E,6645,8,6000,250,293 +E,6646,8,6000,250,293 +E,6647,8,6000,250,293 +E,6648,8,6000,250,293 +E,6649,8,6000,250,293 +E,6650,8,6000,250,293 +E,6651,8,6000,250,293 +E,6652,8,6000,250,293 +E,6653,8,6000,250,293 +E,6654,8,6000,250,293 +E,6655,8,6000,250,293 +E,6656,8,6000,250,293 +E,6657,8,6000,250,293 +E,6658,8,6000,250,293 +E,6659,8,6000,250,293 +E,6660,8,6000,250,293 +E,6661,8,6000,250,293 +E,6662,8,6000,250,293 +E,6663,8,6000,250,293 +E,6664,8,6000,250,293 +E,6665,8,6000,250,293 +E,6666,8,6000,250,293 +E,6667,8,6000,250,293 +E,6668,8,6000,250,293 +E,6669,8,6000,250,293 +E,6670,8,6000,250,293 +E,6671,8,6000,250,293 +E,6672,8,6000,250,293 +E,6673,8,6000,250,293 +E,6674,8,6000,250,293 +E,6675,8,6000,250,293 +E,6676,8,6000,250,293 +E,6677,8,6000,250,293 +E,6678,8,6000,250,293 +E,6679,8,6000,250,293 +E,6680,8,6000,250,293 +E,6681,8,6000,250,293 +E,6682,8,6000,250,293 +E,6683,8,6000,250,293 +E,6684,8,6000,250,293 +E,6685,8,6000,250,293 +E,6686,8,6000,250,293 +E,6687,8,6000,250,293 +E,6688,8,6000,250,293 +E,6689,8,6000,250,293 +E,6690,8,6000,250,293 +E,6691,8,6000,250,293 +E,6692,8,6000,250,293 +E,6693,8,6000,250,293 +E,6694,8,6000,250,293 +E,6695,8,6000,250,293 +E,6696,8,6000,250,293 +E,6697,8,6000,250,293 +E,6698,8,6000,250,293 +E,6699,8,6000,250,293 +E,6700,8,6000,250,293 +E,6701,8,6000,250,293 +E,6702,8,6000,250,293 +E,6703,8,6000,250,293 +E,6704,8,6000,250,293 +E,6705,8,6000,250,293 +E,6706,8,6000,250,293 +E,6707,8,6000,250,293 +E,6708,8,6000,250,293 +E,6709,8,6000,250,585 +E,6710,8,6000,250,293 +E,6711,8,6000,250,293 +E,6712,8,6000,250,293 +E,6713,8,6000,250,293 +E,6714,8,6000,250,293 +E,6715,8,6000,250,293 +E,6716,8,6000,250,293 +E,6717,8,6000,250,293 +E,6718,8,6000,250,293 +E,6719,8,6000,250,293 +E,6720,8,6000,250,293 +E,6721,8,6000,250,293 +E,6722,8,6000,250,293 +E,6723,8,6000,250,293 +E,6724,8,6000,250,293 +E,6725,8,6000,250,293 +E,6726,8,6000,250,293 +E,6727,8,6000,250,293 +E,6728,8,6000,250,293 +E,6729,8,6000,250,293 +E,6730,8,6000,250,293 +E,6731,8,6000,250,293 +E,6732,8,6000,250,293 +E,6733,8,6000,250,293 +E,6734,8,6000,250,293 +E,6735,8,6000,250,293 +E,6736,8,6000,250,293 +E,6737,8,6000,250,293 +E,6738,8,6000,250,293 +E,6739,8,6000,250,293 +E,6740,8,6000,250,293 +E,6741,8,6000,250,293 +E,6742,8,6000,250,293 +E,6743,8,6000,250,293 +E,6744,8,6000,250,585 +E,6745,8,6000,250,585 +E,6746,8,6000,250,585 +E,6747,8,6000,250,585 +E,6748,8,6000,250,585 +E,6749,8,6000,250,585 +E,6750,8,6000,250,585 +E,6751,8,6000,250,585 +E,6752,8,6000,250,585 +E,6753,8,6000,250,585 +E,6754,8,6000,250,585 +E,6755,8,6000,250,585 +E,6756,8,6000,250,585 +E,6757,8,6000,250,585 +E,6758,8,6000,250,585 +E,6759,8,6000,250,585 +E,6766,8,6000,250,585 +E,6832,8,6000,250,585 +E,6899,8,6000,250,585 +E,6965,8,6000,250,585 +# step 9/13 rpm=6000 period_us=27 ints=500 count=2646 +D,step_9,904907554,22,174,251,50,66 +H,step_9,187957,26902,0 +E,7000,9,7000,250,1350 +E,7001,9,7000,250,585 +E,7002,9,7000,250,588 +E,7003,9,7000,250,585 +E,7004,9,7000,250,293 +E,7005,9,7000,250,293 +E,7006,9,7000,250,293 +E,7007,9,7000,250,293 +E,7008,9,7000,250,293 +E,7009,9,7000,250,293 +E,7010,9,7000,250,585 +E,7011,9,7000,250,293 +E,7012,9,7000,250,293 +E,7013,9,7000,250,293 +E,7014,9,7000,250,293 +E,7015,9,7000,250,293 +E,7016,9,7000,250,293 +E,7017,9,7000,250,293 +E,7018,9,7000,250,293 +E,7019,9,7000,250,293 +E,7020,9,7000,250,293 +E,7021,9,7000,250,293 +E,7022,9,7000,250,293 +E,7023,9,7000,250,293 +E,7024,9,7000,250,293 +E,7025,9,7000,250,293 +E,7026,9,7000,250,293 +E,7027,9,7000,250,293 +E,7028,9,7000,250,293 +E,7029,9,7000,250,293 +E,7030,9,7000,250,293 +E,7031,9,7000,250,293 +E,7032,9,7000,250,293 +E,7033,9,7000,250,293 +E,7034,9,7000,250,293 +E,7035,9,7000,250,293 +E,7036,9,7000,250,293 +E,7037,9,7000,250,293 +E,7038,9,7000,250,293 +E,7039,9,7000,250,293 +E,7040,9,7000,250,293 +E,7041,9,7000,250,293 +E,7042,9,7000,250,293 +E,7043,9,7000,250,293 +E,7044,9,7000,250,585 +E,7045,9,7000,250,585 +E,7046,9,7000,250,585 +E,7047,9,7000,250,585 +E,7048,9,7000,250,585 +E,7049,9,7000,250,585 +E,7050,9,7000,250,585 +E,7051,9,7000,250,585 +E,7052,9,7000,250,585 +E,7053,9,7000,250,585 +E,7054,9,7000,250,585 +E,7055,9,7000,250,585 +E,7056,9,7000,250,585 +E,7057,9,7000,250,585 +E,7058,9,7000,250,585 +E,7059,9,7000,250,585 +E,7060,9,7000,250,585 +E,7061,9,7000,250,585 +E,7062,9,7000,250,585 +E,7063,9,7000,250,585 +E,7064,9,7000,250,585 +E,7065,9,7000,250,585 +E,7066,9,7000,250,585 +E,7067,9,7000,250,585 +E,7068,9,7000,250,585 +E,7069,9,7000,250,585 +E,7070,9,7000,250,585 +E,7071,9,7000,250,585 +E,7072,9,7000,250,585 +E,7073,9,7000,250,585 +E,7074,9,7000,250,585 +E,7075,9,7000,250,585 +E,7076,9,7000,250,585 +E,7077,9,7000,250,585 +E,7078,9,7000,250,585 +E,7079,9,7000,250,585 +E,7080,9,7000,250,585 +E,7081,9,7000,250,585 +E,7082,9,7000,250,585 +E,7083,9,7000,250,585 +E,7084,9,7000,250,585 +E,7085,9,7000,250,585 +E,7086,9,7000,250,585 +E,7087,9,7000,250,585 +E,7088,9,7000,250,585 +E,7089,9,7000,250,585 +E,7090,9,7000,250,585 +E,7091,9,7000,250,585 +E,7092,9,7000,250,585 +E,7093,9,7000,250,585 +E,7094,9,7000,250,585 +E,7095,9,7000,250,585 +E,7096,9,7000,250,585 +E,7097,9,7000,250,585 +E,7098,9,7000,250,585 +E,7099,9,7000,250,585 +E,7100,9,7000,250,585 +E,7101,9,7000,250,585 +E,7102,9,7000,250,585 +E,7103,9,7000,250,585 +E,7104,9,7000,250,585 +E,7105,9,7000,250,585 +E,7106,9,7000,250,585 +E,7107,9,7000,250,585 +E,7108,9,7000,250,585 +E,7109,9,7000,250,585 +E,7110,9,7000,250,585 +E,7111,9,7000,250,585 +E,7112,9,7000,250,585 +E,7113,9,7000,250,585 +E,7114,9,7000,250,585 +E,7115,9,7000,250,585 +E,7116,9,7000,250,585 +E,7117,9,7000,250,585 +E,7118,9,7000,250,585 +E,7119,9,7000,250,585 +E,7120,9,7000,250,585 +E,7121,9,7000,250,585 +E,7122,9,7000,250,585 +E,7123,9,7000,250,585 +E,7124,9,7000,250,585 +E,7125,9,7000,250,585 +E,7126,9,7000,250,585 +E,7127,9,7000,250,585 +E,7128,9,7000,250,585 +E,7129,9,7000,250,585 +E,7130,9,7000,250,585 +E,7131,9,7000,250,585 +E,7132,9,7000,250,585 +E,7133,9,7000,250,585 +E,7134,9,7000,250,585 +E,7135,9,7000,250,585 +E,7136,9,7000,250,585 +E,7137,9,7000,250,585 +E,7138,9,7000,250,585 +E,7139,9,7000,250,585 +E,7140,9,7000,250,585 +E,7141,9,7000,250,585 +E,7142,9,7000,250,585 +E,7143,9,7000,250,585 +E,7144,9,7000,250,585 +E,7145,9,7000,250,585 +E,7146,9,7000,250,585 +E,7147,9,7000,250,585 +E,7148,9,7000,250,585 +E,7149,9,7000,250,585 +E,7150,9,7000,250,585 +E,7151,9,7000,250,585 +E,7152,9,7000,250,585 +E,7153,9,7000,250,585 +E,7154,9,7000,250,585 +E,7155,9,7000,250,585 +E,7156,9,7000,250,585 +E,7157,9,7000,250,585 +E,7158,9,7000,250,585 +E,7159,9,7000,250,585 +E,7160,9,7000,250,585 +E,7161,9,7000,250,585 +E,7162,9,7000,250,585 +E,7163,9,7000,250,585 +E,7164,9,7000,250,585 +E,7165,9,7000,250,585 +E,7166,9,7000,250,585 +E,7167,9,7000,250,585 +E,7168,9,7000,250,585 +E,7169,9,7000,250,594 +E,7170,9,7000,250,585 +E,7171,9,7000,250,585 +E,7172,9,7000,250,585 +E,7173,9,7000,250,585 +E,7174,9,7000,250,585 +E,7175,9,7000,250,585 +E,7176,9,7000,250,585 +E,7177,9,7000,250,585 +E,7178,9,7000,250,585 +E,7179,9,7000,250,585 +E,7180,9,7000,250,585 +E,7181,9,7000,250,585 +E,7182,9,7000,250,585 +E,7183,9,7000,250,585 +E,7184,9,7000,250,585 +E,7185,9,7000,250,585 +E,7186,9,7000,250,585 +E,7187,9,7000,250,585 +E,7188,9,7000,250,585 +E,7189,9,7000,250,585 +E,7190,9,7000,250,585 +E,7191,9,7000,250,585 +E,7192,9,7000,250,585 +E,7193,9,7000,250,585 +E,7194,9,7000,250,585 +E,7195,9,7000,250,585 +E,7196,9,7000,250,585 +E,7197,9,7000,250,585 +E,7198,9,7000,250,585 +E,7199,9,7000,250,585 +E,7200,9,7000,250,585 +E,7201,9,7000,250,585 +E,7202,9,7000,250,585 +E,7203,9,7000,250,585 +E,7204,9,7000,250,585 +E,7205,9,7000,250,585 +E,7206,9,7000,250,585 +E,7207,9,7000,250,585 +E,7208,9,7000,250,585 +E,7209,9,7000,250,585 +E,7210,9,7000,250,585 +E,7211,9,7000,250,585 +E,7212,9,7000,250,585 +E,7213,9,7000,250,585 +E,7214,9,7000,250,585 +E,7215,9,7000,250,585 +E,7216,9,7000,250,585 +E,7217,9,7000,250,585 +E,7218,9,7000,250,585 +E,7219,9,7000,250,585 +E,7220,9,7000,250,585 +E,7221,9,7000,250,585 +E,7222,9,7000,250,585 +E,7223,9,7000,250,585 +E,7224,9,7000,250,585 +E,7225,9,7000,250,585 +E,7226,9,7000,250,585 +E,7227,9,7000,250,585 +E,7228,9,7000,250,585 +E,7229,9,7000,250,585 +E,7230,9,7000,250,585 +E,7231,9,7000,250,585 +E,7232,9,7000,250,585 +E,7233,9,7000,250,585 +E,7234,9,7000,250,585 +E,7235,9,7000,250,585 +E,7236,9,7000,250,585 +E,7237,9,7000,250,585 +E,7238,9,7000,250,585 +E,7239,9,7000,250,585 +E,7240,9,7000,250,585 +E,7241,9,7000,250,585 +E,7242,9,7000,250,585 +E,7243,9,7000,250,585 +E,7244,9,7000,250,585 +E,7245,9,7000,250,585 +E,7246,9,7000,250,585 +E,7247,9,7000,250,585 +E,7248,9,7000,250,585 +E,7249,9,7000,250,585 +E,7250,9,7000,250,585 +E,7251,9,7000,250,585 +E,7252,9,7000,250,585 +E,7253,9,7000,250,585 +E,7254,9,7000,250,585 +E,7255,9,7000,250,585 +E,7256,9,7000,250,585 +E,7257,9,7000,250,585 +E,7258,9,7000,250,585 +E,7259,9,7000,250,585 +E,7266,9,7000,250,585 +# step 10/13 rpm=7000 period_us=23 ints=300 count=2907 +D,step_10,995585239,2,10,190,247,250 +H,step_10,184354,25392,0 +E,7300,10,8000,250,1350 +E,7301,10,8000,250,588 +E,7302,10,8000,252,582 +E,7303,10,8000,250,585 +E,7304,10,8000,250,588 +E,7305,10,8000,250,588 +E,7306,10,8000,250,588 +E,7307,10,8000,250,585 +E,7308,10,8000,250,585 +E,7309,10,8000,250,588 +E,7310,10,8000,250,585 +E,7311,10,8000,250,585 +E,7312,10,8000,250,588 +E,7313,10,8000,250,585 +E,7314,10,8000,250,585 +E,7315,10,8000,250,588 +E,7316,10,8000,250,585 +E,7317,10,8000,250,588 +E,7318,10,8000,250,588 +E,7319,10,8000,250,585 +E,7320,10,8000,250,585 +E,7321,10,8000,250,588 +E,7322,10,8000,250,585 +E,7323,10,8000,250,585 +E,7324,10,8000,250,588 +E,7325,10,8000,250,585 +E,7326,10,8000,250,588 +E,7327,10,8000,250,588 +E,7328,10,8000,250,585 +E,7329,10,8000,250,585 +E,7330,10,8000,250,588 +E,7331,10,8000,250,585 +E,7332,10,8000,250,585 +E,7333,10,8000,250,588 +E,7334,10,8000,250,585 +E,7335,10,8000,250,588 +E,7336,10,8000,250,588 +E,7337,10,8000,250,585 +E,7338,10,8000,250,585 +E,7339,10,8000,250,588 +E,7340,10,8000,250,585 +E,7341,10,8000,250,585 +E,7342,10,8000,250,588 +E,7343,10,8000,250,585 +E,7344,10,8000,250,585 +E,7345,10,8000,250,588 +E,7346,10,8000,250,585 +E,7347,10,8000,250,588 +E,7348,10,8000,250,588 +E,7349,10,8000,250,585 +E,7350,10,8000,250,585 +E,7351,10,8000,250,588 +E,7352,10,8000,250,585 +E,7353,10,8000,250,585 +E,7354,10,8000,250,588 +E,7355,10,8000,250,585 +E,7356,10,8000,250,588 +E,7357,10,8000,250,588 +E,7358,10,8000,250,585 +E,7359,10,8000,250,585 +E,7360,10,8000,250,588 +E,7361,10,8000,250,585 +E,7362,10,8000,250,585 +E,7363,10,8000,250,588 +E,7364,10,8000,250,585 +E,7365,10,8000,250,588 +E,7366,10,8000,250,588 +E,7367,10,8000,250,585 +E,7368,10,8000,250,585 +E,7369,10,8000,250,588 +E,7370,10,8000,250,585 +E,7371,10,8000,250,585 +E,7372,10,8000,250,588 +E,7373,10,8000,250,585 +E,7374,10,8000,250,585 +E,7375,10,8000,250,588 +E,7376,10,8000,250,585 +E,7377,10,8000,250,588 +E,7378,10,8000,250,588 +E,7379,10,8000,250,585 +E,7380,10,8000,250,585 +E,7381,10,8000,250,588 +E,7382,10,8000,250,585 +E,7383,10,8000,250,585 +E,7384,10,8000,250,588 +E,7385,10,8000,250,585 +E,7386,10,8000,250,588 +E,7387,10,8000,250,588 +E,7388,10,8000,250,585 +E,7389,10,8000,250,585 +E,7390,10,8000,250,588 +E,7391,10,8000,250,585 +E,7392,10,8000,250,585 +E,7393,10,8000,250,588 +E,7394,10,8000,250,585 +E,7395,10,8000,250,585 +E,7396,10,8000,250,588 +E,7397,10,8000,250,585 +E,7398,10,8000,250,588 +E,7399,10,8000,250,588 +E,7400,10,8000,250,585 +E,7401,10,8000,250,585 +E,7402,10,8000,250,588 +E,7403,10,8000,250,585 +E,7404,10,8000,250,585 +E,7405,10,8000,250,588 +E,7406,10,8000,250,585 +E,7407,10,8000,250,588 +E,7408,10,8000,250,588 +E,7409,10,8000,250,585 +E,7410,10,8000,250,585 +E,7411,10,8000,250,588 +E,7412,10,8000,250,585 +E,7413,10,8000,250,585 +E,7414,10,8000,250,588 +E,7415,10,8000,250,585 +E,7416,10,8000,250,588 +E,7417,10,8000,250,588 +E,7418,10,8000,250,585 +E,7419,10,8000,250,585 +E,7420,10,8000,250,588 +E,7421,10,8000,250,585 +E,7422,10,8000,250,585 +E,7423,10,8000,250,588 +E,7424,10,8000,250,585 +E,7425,10,8000,250,585 +E,7426,10,8000,250,588 +E,7427,10,8000,250,585 +E,7428,10,8000,250,588 +E,7429,10,8000,250,588 +E,7430,10,8000,250,585 +E,7431,10,8000,250,585 +E,7432,10,8000,250,588 +E,7433,10,8000,250,585 +E,7434,10,8000,250,585 +E,7435,10,8000,250,588 +E,7436,10,8000,250,585 +E,7437,10,8000,250,588 +E,7438,10,8000,250,588 +E,7439,10,8000,250,585 +E,7440,10,8000,250,585 +E,7441,10,8000,250,588 +E,7442,10,8000,250,585 +E,7443,10,8000,250,585 +E,7444,10,8000,250,588 +E,7445,10,8000,250,585 +E,7446,10,8000,250,588 +E,7447,10,8000,250,588 +E,7448,10,8000,250,585 +E,7449,10,8000,250,585 +E,7450,10,8000,250,588 +E,7451,10,8000,250,585 +E,7452,10,8000,250,585 +E,7453,10,8000,250,588 +E,7454,10,8000,250,585 +E,7455,10,8000,250,585 +E,7456,10,8000,250,588 +E,7457,10,8000,250,585 +E,7458,10,8000,250,588 +E,7459,10,8000,250,588 +E,7460,10,8000,250,585 +E,7461,10,8000,250,585 +E,7462,10,8000,250,588 +E,7463,10,8000,250,585 +E,7464,10,8000,250,591 +E,7465,10,8000,250,588 +E,7466,10,8000,250,585 +E,7467,10,8000,250,588 +E,7468,10,8000,250,588 +E,7469,10,8000,250,585 +E,7470,10,8000,250,585 +E,7471,10,8000,250,588 +E,7472,10,8000,250,585 +E,7473,10,8000,250,585 +E,7474,10,8000,250,588 +E,7475,10,8000,250,585 +E,7476,10,8000,250,588 +E,7477,10,8000,250,588 +E,7478,10,8000,250,585 +E,7479,10,8000,250,588 +E,7480,10,8000,250,588 +E,7481,10,8000,250,585 +E,7482,10,8000,250,585 +E,7483,10,8000,250,588 +E,7484,10,8000,250,585 +E,7485,10,8000,250,585 +E,7486,10,8000,250,588 +E,7487,10,8000,250,585 +E,7488,10,8000,250,588 +E,7489,10,8000,250,588 +E,7490,10,8000,250,585 +E,7491,10,8000,250,585 +E,7492,10,8000,250,588 +E,7493,10,8000,250,585 +E,7494,10,8000,250,585 +E,7495,10,8000,250,588 +E,7496,10,8000,250,585 +E,7497,10,8000,250,588 +E,7498,10,8000,250,588 +E,7499,10,8000,250,585 +# step 11/13 rpm=8000 period_us=20 ints=200 count=3107 +D,step_11,1068327588,24,233,68,142,4 +H,step_11,173843,27196,0 +E,7500,11,9000,250,1350 +E,7501,11,9000,250,588 +E,7502,11,9000,252,582 +E,7503,11,9000,250,585 +E,7504,11,9000,250,588 +E,7505,11,9000,250,588 +E,7506,11,9000,250,588 +E,7507,11,9000,250,585 +E,7508,11,9000,250,585 +E,7509,11,9000,250,588 +E,7510,11,9000,250,585 +E,7511,11,9000,250,585 +E,7512,11,9000,250,588 +E,7513,11,9000,250,585 +E,7514,11,9000,250,585 +E,7515,11,9000,250,588 +E,7516,11,9000,250,585 +E,7517,11,9000,250,588 +E,7518,11,9000,250,588 +E,7519,11,9000,250,585 +E,7520,11,9000,250,585 +E,7521,11,9000,250,588 +E,7522,11,9000,250,585 +E,7523,11,9000,250,585 +E,7524,11,9000,250,588 +E,7525,11,9000,250,585 +E,7526,11,9000,250,588 +E,7527,11,9000,250,588 +E,7528,11,9000,250,585 +E,7529,11,9000,250,585 +E,7530,11,9000,250,588 +E,7531,11,9000,250,585 +E,7532,11,9000,250,585 +E,7533,11,9000,250,588 +E,7534,11,9000,250,585 +E,7535,11,9000,250,588 +E,7536,11,9000,250,588 +E,7537,11,9000,250,585 +E,7538,11,9000,250,585 +E,7539,11,9000,250,588 +E,7540,11,9000,250,585 +E,7541,11,9000,250,585 +E,7542,11,9000,250,588 +E,7543,11,9000,250,585 +E,7544,11,9000,250,585 +E,7545,11,9000,250,588 +E,7546,11,9000,250,585 +E,7547,11,9000,250,588 +E,7548,11,9000,250,588 +E,7549,11,9000,250,585 +E,7550,11,9000,250,585 +E,7551,11,9000,250,588 +E,7552,11,9000,250,585 +E,7553,11,9000,250,585 +E,7554,11,9000,250,588 +E,7555,11,9000,250,585 +E,7556,11,9000,250,588 +E,7557,11,9000,250,588 +E,7558,11,9000,250,585 +E,7559,11,9000,250,585 +E,7560,11,9000,250,588 +E,7561,11,9000,250,585 +E,7562,11,9000,250,585 +E,7563,11,9000,250,588 +E,7564,11,9000,250,585 +E,7565,11,9000,250,588 +E,7566,11,9000,250,588 +E,7567,11,9000,250,585 +E,7568,11,9000,250,585 +E,7569,11,9000,250,588 +E,7570,11,9000,250,585 +E,7571,11,9000,250,585 +E,7572,11,9000,250,588 +E,7573,11,9000,250,585 +E,7574,11,9000,250,585 +E,7575,11,9000,250,588 +E,7576,11,9000,250,585 +E,7577,11,9000,250,588 +E,7578,11,9000,250,588 +E,7579,11,9000,250,585 +E,7580,11,9000,250,585 +E,7581,11,9000,250,588 +E,7582,11,9000,250,585 +E,7583,11,9000,250,585 +E,7584,11,9000,250,588 +E,7585,11,9000,250,585 +E,7586,11,9000,250,588 +E,7587,11,9000,250,588 +E,7588,11,9000,250,585 +E,7589,11,9000,250,585 +E,7590,11,9000,250,588 +E,7591,11,9000,250,585 +E,7592,11,9000,250,585 +E,7593,11,9000,250,588 +E,7594,11,9000,250,585 +E,7595,11,9000,250,585 +E,7596,11,9000,250,588 +E,7597,11,9000,250,585 +E,7598,11,9000,250,588 +E,7599,11,9000,250,588 +E,7600,11,9000,250,585 +E,7601,11,9000,250,585 +E,7602,11,9000,250,588 +E,7603,11,9000,250,585 +E,7604,11,9000,250,585 +E,7605,11,9000,250,588 +E,7606,11,9000,250,585 +E,7607,11,9000,250,588 +E,7608,11,9000,250,588 +E,7609,11,9000,250,585 +E,7610,11,9000,250,585 +E,7611,11,9000,250,588 +E,7612,11,9000,250,585 +E,7613,11,9000,250,585 +E,7614,11,9000,250,588 +E,7615,11,9000,250,585 +E,7616,11,9000,250,588 +E,7617,11,9000,250,588 +E,7618,11,9000,250,585 +E,7619,11,9000,250,585 +E,7620,11,9000,250,588 +E,7621,11,9000,250,585 +E,7622,11,9000,250,585 +E,7623,11,9000,250,588 +E,7624,11,9000,250,585 +E,7625,11,9000,250,585 +E,7626,11,9000,250,588 +E,7627,11,9000,250,585 +E,7628,11,9000,250,588 +E,7629,11,9000,250,588 +E,7630,11,9000,250,585 +E,7631,11,9000,250,585 +E,7632,11,9000,250,588 +E,7633,11,9000,250,585 +E,7634,11,9000,250,585 +E,7635,11,9000,250,588 +E,7636,11,9000,250,585 +E,7637,11,9000,250,588 +E,7638,11,9000,250,588 +E,7639,11,9000,250,585 +E,7640,11,9000,250,585 +E,7641,11,9000,250,588 +E,7642,11,9000,250,585 +E,7643,11,9000,250,585 +E,7644,11,9000,250,588 +E,7645,11,9000,250,585 +E,7646,11,9000,250,588 +E,7647,11,9000,250,588 +E,7648,11,9000,250,585 +E,7649,11,9000,2# step 12/13 rpm=9000 period_us=18 ints=150 count=3256 +D,step_12,1123120158,25,183,129,253,113 +H,step_12,157927,27048,0 +50,585 +E,7650,12,10000,250,585 +E,7651,12,10000,250,585 +E,7652,12,10000,250,585 +E,7653,12,10000,250,588 +E,7654,12,10000,250,588 +E,7655,12,10000,250,585 +E,7656,12,10000,250,585 +E,7657,12,10000,250,588 +E,7658,12,10000,250,585 +E,7659,12,10000,250,588 +E,7660,12,10000,250,588 +E,7661,12,10000,250,585 +E,7662,12,10000,250,585 +E,7663,12,10000,250,588 +E,7664,12,10000,250,585 +E,7665,12,10000,250,585 +E,7666,12,10000,250,588 +E,7667,12,10000,250,585 +E,7668,12,10000,250,585 +E,7669,12,10000,250,588 +E,7670,12,10000,250,585 +E,7671,12,10000,250,588 +E,7672,12,10000,250,588 +E,7673,12,10000,250,585 +E,7674,12,10000,250,585 +E,7675,12,10000,250,588 +E,7676,12,10000,250,585 +E,7677,12,10000,250,585 +E,7678,12,10000,250,588 +E,7679,12,10000,250,585 +E,7680,12,10000,250,588 +E,7681,12,10000,250,588 +E,7682,12,10000,250,585 +E,7683,12,10000,250,585 +E,7684,12,10000,250,588 +E,7685,12,10000,250,585 +E,7686,12,10000,250,585 +E,7687,12,10000,250,588 +E,7688,12,10000,250,585 +E,7689,12,10000,250,588 +E,7690,12,10000,250,588 +E,7691,12,10000,250,585 +E,7692,12,10000,250,585 +E,7693,12,10000,250,588 +E,7694,12,10000,250,585 +E,7695,12,10000,250,585 +E,7696,12,10000,250,588 +E,7697,12,10000,250,585 +E,7698,12,10000,250,585 +E,7699,12,10000,250,588 +E,7700,12,10000,250,585 +E,7701,12,10000,250,588 +E,7702,12,10000,250,588 +E,7703,12,10000,250,585 +E,7704,12,10000,250,585 +E,7705,12,10000,250,588 +E,7706,12,10000,250,585 +E,7707,12,10000,250,585 +E,7708,12,10000,250,588 +E,7709,12,10000,250,585 +E,7710,12,10000,250,588 +E,7711,12,10000,250,588 +E,7712,12,10000,250,585 +E,7713,12,10000,250,585 +E,7714,12,10000,250,588 +E,7715,12,10000,250,585 +E,7716,12,10000,250,585 +E,7717,12,10000,250,588 +E,7718,12,10000,250,585 +E,7719,12,10000,250,588 +E,7720,12,10000,250,594 +E,7721,12,10000,250,585 +E,7722,12,10000,250,585 +E,7723,12,10000,250,588 +E,7724,12,10000,250,585 +E,7725,12,10000,250,585 +E,7726,12,10000,250,588 +E,7727,12,10000,250,585 +E,7728,12,10000,250,585 +E,7729,12,10000,250,588 +E,7730,12,10000,250,585 +E,7731,12,10000,250,588 +E,7732,12,10000,250,588 +E,7733,12,10000,250,585 +E,7734,12,10000,250,585 +E,7735,12,10000,250,588 +E,7736,12,10000,250,585 +E,7737,12,10000,250,585 +E,7738,12,10000,250,588 +E,7739,12,10000,250,585 +E,7740,12,10000,250,588 +E,7741,12,10000,250,588 +E,7742,12,10000,250,585 +E,7743,12,10000,250,585 +E,7744,12,10000,250,588 +E,7745,12,10000,250,585 +E,7746,12,10000,250,585 +E,7747,12,10000,250,588 +E,7748,12,10000,250,585 +E,7749,12# step 13/13 rpm=10000 period_us=16 ints=100 count=3356 +D,step_13,1161724344,86,32,129,146,119 +H,step_13,141111,26333,0 +,10000,250,585 +D,end,1162934134,46,200,129,60,65 +H,end,27898,30533,0 +drops,4393 +samples,3357 +=== END === diff --git a/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-418c6b8c-gale-synth-systick/events.csv b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-418c6b8c-gale-synth-systick/events.csv new file mode 100644 index 00000000..99251a44 --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-418c6b8c-gale-synth-systick/events.csv @@ -0,0 +1,7354 @@ +Rsilicon-2026-05-10,gale-synth,E,435,0,500,253,582 +Rsilicon-2026-05-10,gale-synth,E,436,0,500,253,582 +Rsilicon-2026-05-10,gale-synth,E,437,0,500,253,582 +Rsilicon-2026-05-10,gale-synth,E,438,0,500,253,582 +Rsilicon-2026-05-10,gale-synth,E,439,0,500,253,582 +Rsilicon-2026-05-10,gale-synth,E,440,0,500,253,582 +Rsilicon-2026-05-10,gale-synth,E,441,0,500,253,582 +Rsilicon-2026-05-10,gale-synth,E,442,0,500,253,582 +Rsilicon-2026-05-10,gale-synth,E,443,0,500,253,582 +Rsilicon-2026-05-10,gale-synth,E,444,0,500,253,582 +Rsilicon-2026-05-10,gale-synth,E,445,0,500,253,582 +Rsilicon-2026-05-10,gale-synth,E,446,0,500,253,582 +Rsilicon-2026-05-10,gale-synth,E,447,0,500,253,582 +Rsilicon-2026-05-10,gale-synth,E,448,0,500,253,582 +Rsilicon-2026-05-10,gale-synth,E,449,0,500,253,582 +Rsilicon-2026-05-10,gale-synth,E,450,0,500,253,582 +Rsilicon-2026-05-10,gale-synth,E,451,0,500,253,582 +Rsilicon-2026-05-10,gale-synth,E,452,0,500,253,582 +Rsilicon-2026-05-10,gale-synth,E,453,0,500,253,582 +Rsilicon-2026-05-10,gale-synth,E,454,0,500,253,582 +Rsilicon-2026-05-10,gale-synth,E,455,0,500,253,582 +Rsilicon-2026-05-10,gale-synth,E,456,0,500,253,582 +Rsilicon-2026-05-10,gale-synth,E,457,0,500,253,582 +Rsilicon-2026-05-10,gale-synth,E,458,0,500,253,582 +Rsilicon-2026-05-10,gale-synth,E,459,0,500,253,582 +Rsilicon-2026-05-10,gale-synth,E,460,0,500,253,582 +Rsilicon-2026-05-10,gale-synth,E,461,0,500,253,582 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+Rsilicon-2026-05-10,gale-synth,E,7569,11,9000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7570,11,9000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7571,11,9000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7572,11,9000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7573,11,9000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7574,11,9000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7575,11,9000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7576,11,9000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7577,11,9000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7578,11,9000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7579,11,9000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7580,11,9000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7581,11,9000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7582,11,9000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7583,11,9000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7584,11,9000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7585,11,9000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7586,11,9000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7587,11,9000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7588,11,9000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7589,11,9000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7590,11,9000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7591,11,9000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7592,11,9000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7593,11,9000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7594,11,9000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7595,11,9000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7596,11,9000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7597,11,9000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7598,11,9000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7599,11,9000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7600,11,9000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7601,11,9000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7602,11,9000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7603,11,9000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7604,11,9000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7605,11,9000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7606,11,9000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7607,11,9000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7608,11,9000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7609,11,9000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7610,11,9000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7611,11,9000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7612,11,9000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7613,11,9000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7614,11,9000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7615,11,9000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7616,11,9000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7617,11,9000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7618,11,9000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7619,11,9000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7620,11,9000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7621,11,9000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7622,11,9000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7623,11,9000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7624,11,9000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7625,11,9000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7626,11,9000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7627,11,9000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7628,11,9000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7629,11,9000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7630,11,9000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7631,11,9000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7632,11,9000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7633,11,9000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7634,11,9000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7635,11,9000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7636,11,9000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7637,11,9000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7638,11,9000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7639,11,9000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7640,11,9000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7641,11,9000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7642,11,9000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7643,11,9000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7644,11,9000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7645,11,9000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7646,11,9000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7647,11,9000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7648,11,9000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7649,11,9000,25# step 12/13 rpm=9000 period_us=18 ints=150 count=7649 +Rsilicon-2026-05-10,gale-synth,D,step_12,2607184839,113,194,90,107,243 +Rsilicon-2026-05-10,gale-synth,H,step_12,163033,27196,0 +Rsilicon-2026-05-10,gale-synth,E,7650,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7651,12,10000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7652,12,10000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7653,12,10000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7654,12,10000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7655,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7656,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7657,12,10000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7658,12,10000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7659,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7660,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7661,12,10000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7662,12,10000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7663,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7664,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7665,12,10000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7666,12,10000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7667,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7668,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7669,12,10000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7670,12,10000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7671,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7672,12,10000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7673,12,10000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7674,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7675,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7676,12,10000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7677,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7678,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7679,12,10000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7680,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7681,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7682,12,10000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7683,12,10000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7684,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7685,12,10000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7686,12,10000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7687,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7688,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7689,12,10000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7690,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7691,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7692,12,10000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7693,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7694,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7695,12,10000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7696,12,10000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7697,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7698,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7699,12,10000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7700,12,10000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7701,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7702,12,10000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7703,12,10000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7704,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7705,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7706,12,10000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7707,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7708,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7709,12,10000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7710,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7711,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7712,12,10000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7713,12,10000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7714,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7715,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7716,12,10000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7717,12,10000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7718,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7719,12,10000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7720,12,10000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7721,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7722,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7723,12,10000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7724,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7725,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7726,12,10000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7727,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7728,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7729,12,10000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7730,12,10000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7731,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7732,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7733,12,10000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7734,12,10000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7735,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7736,12,10000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7737,12,10000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7738,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7739,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7740,12,10000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7741,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7742,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7743,12,10000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7744,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7745,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7746,12,10000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7747,12,10000,253,588 +Rsilicon-2026-05-10,gale-synth,E,7748,12,10000,253,582 +Rsilicon-2026-05-10,gale-synth,E,7749,12,# step 13/13 rpm=10000 period_us=16 ints=100 count=7749 +Rsilicon-2026-05-10,gale-synth,D,step_13,2645789022,203,40,90,182,96 +Rsilicon-2026-05-10,gale-synth,H,step_13,134504,27650,0 +Rsilicon-2026-05-10,gale-synth,D,end,2646969212,101,212,90,103,44 +Rsilicon-2026-05-10,gale-synth,H,end,26697,27650,0 +M,Rsilicon-2026-05-10,gale-synth,drops,0 +M,Rsilicon-2026-05-10,gale-synth,samples,7750 +M,Rsilicon-2026-05-10,gale-synth,END diff --git a/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-418c6b8c-gale-synth-systick/firmware.elf b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-418c6b8c-gale-synth-systick/firmware.elf new file mode 100755 index 00000000..9cb613ac Binary files /dev/null and b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-418c6b8c-gale-synth-systick/firmware.elf differ diff --git a/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-418c6b8c-gale-synth-systick/firmware.elf.sha256 b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-418c6b8c-gale-synth-systick/firmware.elf.sha256 new file mode 100644 index 00000000..b57eecf1 --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-418c6b8c-gale-synth-systick/firmware.elf.sha256 @@ -0,0 +1 @@ +ab14f955ebb02e029b1f10d9cd105c7fe78d7e5b1e5a3863ca6e4042461b9306 firmware.elf diff --git a/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-418c6b8c-gale-synth-systick/manifest.txt b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-418c6b8c-gale-synth-systick/manifest.txt new file mode 100644 index 00000000..7ffaa340 --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-418c6b8c-gale-synth-systick/manifest.txt @@ -0,0 +1,27 @@ +# Silicon-anchor manifest +# Produced by benches/engine_control/silicon/capture.sh + manual flash for GALE_USE_SYNTH variant +captured_at: 2026-05-10T08:35:00Z +board: nucleo_g474re +variant: gale-synth +tick_source: systick +sweep: long +flash_runner: openocd +build_pipeline: wasm32-unknown-unknown -> synth -> ar -> libgale_ffi.a +synth_version: synth 0.1.0 +loom_version: loom 0.5.0 +wasm_opt_version: wasm-opt version 129 +gale_sha: 418c6b8ca9c250239d186df3a00dd5b8e8b6feac +gale_status: clean +host: Darwin 25.3.0 arm64 +rustc: rustc 1.94.1 (e408947bf 2026-03-25) +cargo: cargo 1.94.1 (29ea6fb6a 2026-03-24) +west: West version: v1.5.0 +zephyr_base: /Volumes/Home/git/pulseengine/zephyr +zephyr_sha: fc4d89c118fc1d0ff0ad31906a4fa4bd252c9ced +sdk_dir: /Volumes/Home/zephyr-sdk/zephyr-sdk-1.0.1 +elf_sha256: ab14f955ebb02e029b1f10d9cd105c7fe78d7e5b1e5a3863ca6e4042461b9306 +csv_sha256: 179cd4b243b21e9a2b7ab5d2f8749faaca2a3afd3e9955e95cb2175608855dfb +csv_bytes: 169848 +csv_event_lines: 7315 +serial_port: /dev/cu.usbmodem132203 +capture_timeout_s: 1800 diff --git a/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-418c6b8c-gale-synth-systick/output.csv b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-418c6b8c-gale-synth-systick/output.csv new file mode 100644 index 00000000..b5aa72ce --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-418c6b8c-gale-synth-systick/output.csv @@ -0,0 +1,7360 @@ +b�b���b���b�’ +E,435,0,500,253,582 +E,436,0,500,253,582 +E,437,0,500,253,582 +E,438,0,500,253,582 +E,439,0,500,253,582 +E,440,0,500,253,582 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+E,6496,7,5000,253,582 +E,6497,7,5000,253,582 +E,6498,7,5000,253,582 +E,6499,7,5000,253,582 +# step 8/13 rpm=5000 period_us=33 ints=1000 count=6500 +D,step_8,2204137403,250,68,243,177,95 +H,step_8,242012,27048,0 +E,6500,8,6000,253,582 +E,6501,8,6000,253,582 +E,6502,8,6000,253,582 +E,6503,8,6000,253,582 +E,6504,8,6000,253,582 +E,6505,8,6000,253,582 +E,6506,8,6000,253,582 +E,6507,8,6000,253,582 +E,6508,8,6000,253,582 +E,6509,8,6000,253,582 +E,6510,8,6000,253,582 +E,6511,8,6000,253,582 +E,6512,8,6000,253,582 +E,6513,8,6000,253,582 +E,6514,8,6000,253,582 +E,6515,8,6000,253,582 +E,6516,8,6000,253,582 +E,6517,8,6000,253,582 +E,6518,8,6000,253,582 +E,6519,8,6000,253,582 +E,6520,8,6000,253,582 +E,6521,8,6000,253,582 +E,6522,8,6000,253,582 +E,6523,8,6000,253,582 +E,6524,8,6000,253,582 +E,6525,8,6000,253,582 +E,6526,8,6000,253,582 +E,6527,8,6000,253,582 +E,6528,8,6000,253,582 +E,6529,8,6000,253,582 +E,6530,8,6000,253,582 +E,6531,8,6000,253,582 +E,6532,8,6000,253,582 +E,6533,8,6000,253,582 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+D,step_10,2479606112,86,150,90,38,164 +H,step_10,209279,27048,0 +82 +E,7300,10,8000,253,582 +E,7301,10,8000,253,582 +E,7302,10,8000,253,582 +E,7303,10,8000,253,582 +E,7304,10,8000,253,588 +E,7305,10,8000,253,582 +E,7306,10,8000,253,582 +E,7307,10,8000,253,588 +E,7308,10,8000,253,588 +E,7309,10,8000,253,582 +E,7310,10,8000,253,582 +E,7311,10,8000,253,588 +E,7312,10,8000,253,588 +E,7313,10,8000,253,582 +E,7314,10,8000,253,582 +E,7315,10,8000,253,588 +E,7316,10,8000,253,588 +E,7317,10,8000,253,582 +E,7318,10,8000,253,582 +E,7319,10,8000,253,588 +E,7320,10,8000,253,588 +E,7321,10,8000,253,582 +E,7322,10,8000,253,588 +E,7323,10,8000,253,588 +E,7324,10,8000,253,582 +E,7325,10,8000,253,582 +E,7326,10,8000,253,588 +E,7327,10,8000,253,582 +E,7328,10,8000,253,582 +E,7329,10,8000,253,588 +E,7330,10,8000,253,582 +E,7331,10,8000,253,582 +E,7332,10,8000,253,588 +E,7333,10,8000,253,588 +E,7334,10,8000,253,582 +E,7335,10,8000,253,582 +E,7336,10,8000,253,588 +E,7337,10,8000,253,588 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+E,7420,10,8000,253,588 +E,7421,10,8000,253,588 +E,7422,10,8000,253,582 +E,7423,10,8000,253,582 +E,7424,10,8000,253,588 +E,7425,10,8000,253,582 +E,7426,10,8000,253,582 +E,7427,10,8000,253,588 +E,7428,10,8000,253,582 +E,7429,10,8000,253,582 +E,7430,10,8000,253,588 +E,7431,10,8000,253,588 +E,7432,10,8000,253,582 +E,7433,10,8000,253,588 +E,7434,10,8000,253,588 +E,7435,10,8000,253,582 +E,7436,10,8000,253,582 +E,7437,10,8000,253,588 +E,7438,10,8000,253,582 +E,7439,10,8000,253,582 +E,7440,10,8000,253,588 +E,7441,10,8000,253,582 +E,7442,10,8000,253,582 +E,7443,10,8000,253,588 +E,7444,10,8000,253,588 +E,7445,10,8000,253,582 +E,7446,10,8000,253,582 +E,7447,10,8000,253,588 +E,7448,10,8000,253,588 +E,7449,10,8000,253,582 +E,7450,10,8000,253,588 +E,7451,10,8000,253,588 +E,7452,10,8000,253,582 +E,7453,10,8000,253,582 +E,7454,10,8000,253,588 +E,7455,10,8000,253,582 +E,7456,10,8000,253,582 +E,7457,10,8000,253,588 +E,7458,10,8000,253,582 +E,7459,10,8000,253,582 +E,7460,10,8000,253,588 +E,7461,10,8000,253,588 +E,7462,10,8000,253,582 +E,7463,10,8000,253,588 +E,7464,10,8000,253,588 +E,7465,10,8000,253,582 +E,7466,10,8000,253,588 +E,7467,10,8000,253,588 +E,7468,10,8000,253,582 +E,7469,10,8000,253,582 +E,7470,10,8000,253,588 +E,7471,10,8000,253,582 +E,7472,10,8000,253,582 +E,7473,10,8000,253,588 +E,7474,10,8000,253,588 +E,7475,10,8000,253,582 +E,7476,10,8000,253,582 +E,7477,10,8000,253,588 +E,7478,10,8000,253,588 +E,7479,10,8000,253,582 +E,7480,10,8000,253,582 +E,7481,10,8000,253,588 +E,7482,10,8000,253,582 +E,7483,10,8000,253,582 +E,7484,10,8000,253,588 +E,7485,10,8000,253,582 +E,7486,10,8000,253,582 +E,7487,10,8000,253,588 +E,7488,10,8000,253,582 +E,7489,10,8000,253,582 +E,7490,10,8000,253,588 +E,7491,10,8000,253,588 +E,7492,10,8000,253,582 +E,7493,10,8000,253,582 +E,7494,10,8000,253,588 +E,7495,10,8000,253,588 +E,7496,10,8000,253,582 +E,7497,10,8000,253,588 +E,7498,10,8000,253,588 +E,7499,10,8000,253,582 +# step 11/13 rpm=8000 period_us=20 ints=200 count=7500 +D,step_11,2552362752,153,197,90,74,229 +H,step_11,185855,26473,0 +E,7500,11,9000,253,582 +E,7501,11,9000,253,582 +E,7502,11,9000,253,582 +E,7503,11,9000,253,582 +E,7504,11,9000,253,588 +E,7505,11,9000,253,582 +E,7506,11,9000,253,582 +E,7507,11,9000,253,588 +E,7508,11,9000,253,588 +E,7509,11,9000,253,582 +E,7510,11,9000,253,582 +E,7511,11,9000,253,588 +E,7512,11,9000,253,588 +E,7513,11,9000,253,582 +E,7514,11,9000,253,582 +E,7515,11,9000,253,588 +E,7516,11,9000,253,588 +E,7517,11,9000,253,582 +E,7518,11,9000,253,582 +E,7519,11,9000,253,588 +E,7520,11,9000,253,588 +E,7521,11,9000,253,582 +E,7522,11,9000,253,588 +E,7523,11,9000,253,588 +E,7524,11,9000,253,582 +E,7525,11,9000,253,582 +E,7526,11,9000,253,588 +E,7527,11,9000,253,582 +E,7528,11,9000,253,582 +E,7529,11,9000,253,588 +E,7530,11,9000,253,582 +E,7531,11,9000,253,582 +E,7532,11,9000,253,588 +E,7533,11,9000,253,588 +E,7534,11,9000,253,582 +E,7535,11,9000,253,582 +E,7536,11,9000,253,588 +E,7537,11,9000,253,588 +E,7538,11,9000,253,582 +E,7539,11,9000,253,588 +E,7540,11,9000,253,588 +E,7541,11,9000,253,582 +E,7542,11,9000,253,582 +E,7543,11,9000,253,588 +E,7544,11,9000,253,582 +E,7545,11,9000,253,582 +E,7546,11,9000,253,588 +E,7547,11,9000,253,582 +E,7548,11,9000,253,582 +E,7549,11,9000,253,588 +E,7550,11,9000,253,588 +E,7551,11,9000,253,582 +E,7552,11,9000,253,588 +E,7553,11,9000,253,588 +E,7554,11,9000,253,582 +E,7555,11,9000,253,582 +E,7556,11,9000,253,588 +E,7557,11,9000,253,582 +E,7558,11,9000,253,582 +E,7559,11,9000,253,588 +E,7560,11,9000,253,582 +E,7561,11,9000,253,582 +E,7562,11,9000,253,588 +E,7563,11,9000,253,588 +E,7564,11,9000,253,582 +E,7565,11,9000,253,582 +E,7566,11,9000,253,588 +E,7567,11,9000,253,588 +E,7568,11,9000,253,582 +E,7569,11,9000,253,588 +E,7570,11,9000,253,588 +E,7571,11,9000,253,582 +E,7572,11,9000,253,582 +E,7573,11,9000,253,588 +E,7574,11,9000,253,582 +E,7575,11,9000,253,582 +E,7576,11,9000,253,588 +E,7577,11,9000,253,582 +E,7578,11,9000,253,582 +E,7579,11,9000,253,588 +E,7580,11,9000,253,588 +E,7581,11,9000,253,582 +E,7582,11,9000,253,582 +E,7583,11,9000,253,588 +E,7584,11,9000,253,588 +E,7585,11,9000,253,582 +E,7586,11,9000,253,588 +E,7587,11,9000,253,588 +E,7588,11,9000,253,582 +E,7589,11,9000,253,582 +E,7590,11,9000,253,588 +E,7591,11,9000,253,582 +E,7592,11,9000,253,582 +E,7593,11,9000,253,588 +E,7594,11,9000,253,582 +E,7595,11,9000,253,582 +E,7596,11,9000,253,588 +E,7597,11,9000,253,588 +E,7598,11,9000,253,582 +E,7599,11,9000,253,582 +E,7600,11,9000,253,588 +E,7601,11,9000,253,588 +E,7602,11,9000,253,582 +E,7603,11,9000,253,588 +E,7604,11,9000,253,588 +E,7605,11,9000,253,582 +E,7606,11,9000,253,582 +E,7607,11,9000,253,588 +E,7608,11,9000,253,582 +E,7609,11,9000,253,582 +E,7610,11,9000,253,588 +E,7611,11,9000,253,582 +E,7612,11,9000,253,582 +E,7613,11,9000,253,588 +E,7614,11,9000,253,588 +E,7615,11,9000,253,582 +E,7616,11,9000,253,588 +E,7617,11,9000,253,588 +E,7618,11,9000,253,582 +E,7619,11,9000,253,582 +E,7620,11,9000,253,588 +E,7621,11,9000,253,582 +E,7622,11,9000,253,582 +E,7623,11,9000,253,588 +E,7624,11,9000,253,582 +E,7625,11,9000,253,582 +E,7626,11,9000,253,588 +E,7627,11,9000,253,588 +E,7628,11,9000,253,582 +E,7629,11,9000,253,582 +E,7630,11,9000,253,588 +E,7631,11,9000,253,588 +E,7632,11,9000,253,582 +E,7633,11,9000,253,588 +E,7634,11,9000,253,588 +E,7635,11,9000,253,582 +E,7636,11,9000,253,582 +E,7637,11,9000,253,588 +E,7638,11,9000,253,582 +E,7639,11,9000,253,582 +E,7640,11,9000,253,588 +E,7641,11,9000,253,582 +E,7642,11,9000,253,582 +E,7643,11,9000,253,588 +E,7644,11,9000,253,588 +E,7645,11,9000,253,582 +E,7646,11,9000,253,582 +E,7647,11,9000,253,588 +E,7648,11,9000,253,588 +E,7649,11,9000,25# step 12/13 rpm=9000 period_us=18 ints=150 count=7649 +D,step_12,2607184839,113,194,90,107,243 +H,step_12,163033,27196,0 +3,582 +E,7650,12,10000,253,582 +E,7651,12,10000,253,588 +E,7652,12,10000,253,588 +E,7653,12,10000,253,588 +E,7654,12,10000,253,588 +E,7655,12,10000,253,582 +E,7656,12,10000,253,582 +E,7657,12,10000,253,588 +E,7658,12,10000,253,588 +E,7659,12,10000,253,582 +E,7660,12,10000,253,582 +E,7661,12,10000,253,588 +E,7662,12,10000,253,588 +E,7663,12,10000,253,582 +E,7664,12,10000,253,582 +E,7665,12,10000,253,588 +E,7666,12,10000,253,588 +E,7667,12,10000,253,582 +E,7668,12,10000,253,582 +E,7669,12,10000,253,588 +E,7670,12,10000,253,588 +E,7671,12,10000,253,582 +E,7672,12,10000,253,588 +E,7673,12,10000,253,588 +E,7674,12,10000,253,582 +E,7675,12,10000,253,582 +E,7676,12,10000,253,588 +E,7677,12,10000,253,582 +E,7678,12,10000,253,582 +E,7679,12,10000,253,588 +E,7680,12,10000,253,582 +E,7681,12,10000,253,582 +E,7682,12,10000,253,588 +E,7683,12,10000,253,588 +E,7684,12,10000,253,582 +E,7685,12,10000,253,588 +E,7686,12,10000,253,588 +E,7687,12,10000,253,582 +E,7688,12,10000,253,582 +E,7689,12,10000,253,588 +E,7690,12,10000,253,582 +E,7691,12,10000,253,582 +E,7692,12,10000,253,588 +E,7693,12,10000,253,582 +E,7694,12,10000,253,582 +E,7695,12,10000,253,588 +E,7696,12,10000,253,588 +E,7697,12,10000,253,582 +E,7698,12,10000,253,582 +E,7699,12,10000,253,588 +E,7700,12,10000,253,588 +E,7701,12,10000,253,582 +E,7702,12,10000,253,588 +E,7703,12,10000,253,588 +E,7704,12,10000,253,582 +E,7705,12,10000,253,582 +E,7706,12,10000,253,588 +E,7707,12,10000,253,582 +E,7708,12,10000,253,582 +E,7709,12,10000,253,588 +E,7710,12,10000,253,582 +E,7711,12,10000,253,582 +E,7712,12,10000,253,588 +E,7713,12,10000,253,588 +E,7714,12,10000,253,582 +E,7715,12,10000,253,582 +E,7716,12,10000,253,588 +E,7717,12,10000,253,588 +E,7718,12,10000,253,582 +E,7719,12,10000,253,588 +E,7720,12,10000,253,588 +E,7721,12,10000,253,582 +E,7722,12,10000,253,582 +E,7723,12,10000,253,588 +E,7724,12,10000,253,582 +E,7725,12,10000,253,582 +E,7726,12,10000,253,588 +E,7727,12,10000,253,582 +E,7728,12,10000,253,582 +E,7729,12,10000,253,588 +E,7730,12,10000,253,588 +E,7731,12,10000,253,582 +E,7732,12,10000,253,582 +E,7733,12,10000,253,588 +E,7734,12,10000,253,588 +E,7735,12,10000,253,582 +E,7736,12,10000,253,588 +E,7737,12,10000,253,588 +E,7738,12,10000,253,582 +E,7739,12,10000,253,582 +E,7740,12,10000,253,588 +E,7741,12,10000,253,582 +E,7742,12,10000,253,582 +E,7743,12,10000,253,588 +E,7744,12,10000,253,582 +E,7745,12,10000,253,582 +E,7746,12,10000,253,588 +E,7747,12,10000,253,588 +E,7748,12,10000,253,582 +E,7749,12,# step 13/13 rpm=10000 period_us=16 ints=100 count=7749 +D,step_13,2645789022,203,40,90,182,96 +H,step_13,134504,27650,0 +10000,253,588 +D,end,2646969212,101,212,90,103,44 +H,end,26697,27650,0 +drops,0 +samples,7750 +=== END === diff --git a/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-8a4d817d-baseline-systick/events.csv b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-8a4d817d-baseline-systick/events.csv new file mode 100644 index 00000000..6187a14a --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-8a4d817d-baseline-systick/events.csv @@ -0,0 +1,7392 @@ +Rsilicon-2026-05-10,baseline,E,397,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,398,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,399,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,400,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,401,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,402,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,403,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,404,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,405,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,406,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,407,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,408,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,409,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,410,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,411,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,412,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,413,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,414,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,415,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,416,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,417,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,418,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,419,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,420,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,421,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,422,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,423,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,424,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,425,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,426,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,427,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,428,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,429,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,430,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,431,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,432,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,433,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,434,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,435,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,436,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,437,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,438,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,439,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,440,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,441,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,442,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,443,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,444,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,445,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,446,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,447,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,448,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,449,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,450,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,451,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,452,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,453,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,454,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,455,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,456,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,457,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,458,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,459,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,460,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,461,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,462,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,463,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,464,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,465,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,466,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,467,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,468,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,469,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,470,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,471,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,472,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,473,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,474,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,475,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,476,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,477,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,478,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,479,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,480,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,481,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,482,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,483,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,484,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,485,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,486,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,487,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,488,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,489,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,490,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,491,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,492,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,493,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,494,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,495,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,496,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,497,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,498,0,500,253,506 +Rsilicon-2026-05-10,baseline,E,4# step 1/13 rpm=500 period_us=333 ints=500 count=499 +Rsilicon-2026-05-10,baseline,D,step_1,161291164,252,48,223,111,196 +Rsilicon-2026-05-10,baseline,H,step_1,159729,22218,0 +Rsilicon-2026-05-10,baseline,E,500,1,1000,253,506 +Rsilicon-2026-05-10,baseline,E,501,1,1000,253,506 +Rsilicon-2026-05-10,baseline,E,502,1,1000,253,506 +Rsilicon-2026-05-10,baseline,E,503,1,1000,253,506 +Rsilicon-2026-05-10,baseline,E,504,1,1000,253,506 +Rsilicon-2026-05-10,baseline,E,505,1,1000,253,506 +Rsilicon-2026-05-10,baseline,E,506,1,1000,253,506 +Rsilicon-2026-05-10,baseline,E,507,1,1000,253,506 +Rsilicon-2026-05-10,baseline,E,508,1,1000,253,506 +Rsilicon-2026-05-10,baseline,E,509,1,1000,253,506 +Rsilicon-2026-05-10,baseline,E,510,1,1000,253,506 +Rsilicon-2026-05-10,baseline,E,511,1,1000,253,506 +Rsilicon-2026-05-10,baseline,E,512,1,1000,253,506 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+Rsilicon-2026-05-10,baseline,E,1498,2,1500,253,506 +Rsilicon-2026-05-10,baseline,E,1499,2,1500,253,506 +# Rsilicon-2026-05-10 baseline: step 3/13 rpm=1500 period_us=111 ints=500 count=1500 +Rsilicon-2026-05-10,baseline,D,step_3,497515784,71,217,28,5,16 +Rsilicon-2026-05-10,baseline,H,step_3,172342,22520,0 +Rsilicon-2026-05-10,baseline,E,1500,3,2000,253,1283 +Rsilicon-2026-05-10,baseline,E,1501,3,2000,253,506 +Rsilicon-2026-05-10,baseline,E,1502,3,2000,253,506 +Rsilicon-2026-05-10,baseline,E,1503,3,2000,253,506 +Rsilicon-2026-05-10,baseline,E,1504,3,2000,253,506 +Rsilicon-2026-05-10,baseline,E,1505,3,2000,253,506 +Rsilicon-2026-05-10,baseline,E,1506,3,2000,253,506 +Rsilicon-2026-05-10,baseline,E,1507,3,2000,253,506 +Rsilicon-2026-05-10,baseline,E,1508,3,2000,253,506 +Rsilicon-2026-05-10,baseline,E,1509,3,2000,253,506 +Rsilicon-2026-05-10,baseline,E,1510,3,2000,253,506 +Rsilicon-2026-05-10,baseline,E,1511,3,2000,253,506 +Rsilicon-2026-05-10,baseline,E,1512,3,2000,253,506 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ints=1000 count=2500 +Rsilicon-2026-05-10,baseline,D,step_4,838808573,239,251,174,239,11 +Rsilicon-2026-05-10,baseline,H,step_4,186756,22022,0 +Rsilicon-2026-05-10,baseline,E,2500,4,2500,253,1283 +Rsilicon-2026-05-10,baseline,E,2501,4,2500,253,506 +Rsilicon-2026-05-10,baseline,E,2502,4,2500,253,506 +Rsilicon-2026-05-10,baseline,E,2503,4,2500,253,506 +Rsilicon-2026-05-10,baseline,E,2504,4,2500,253,506 +Rsilicon-2026-05-10,baseline,E,2505,4,2500,253,506 +Rsilicon-2026-05-10,baseline,E,2506,4,2500,253,506 +Rsilicon-2026-05-10,baseline,E,2507,4,2500,253,506 +Rsilicon-2026-05-10,baseline,E,2508,4,2500,253,506 +Rsilicon-2026-05-10,baseline,E,2509,4,2500,253,506 +Rsilicon-2026-05-10,baseline,E,2510,4,2500,253,506 +Rsilicon-2026-05-10,baseline,E,2511,4,2500,253,506 +Rsilicon-2026-05-10,baseline,E,2512,4,2500,253,506 +Rsilicon-2026-05-10,baseline,E,2513,4,2500,253,506 +Rsilicon-2026-05-10,baseline,E,2514,4,2500,253,506 +Rsilicon-2026-05-10,baseline,E,2515,4,2500,253,506 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+Rsilicon-2026-05-10,baseline,E,3485,4,2500,253,506 +Rsilicon-2026-05-10,baseline,E,3486,4,2500,253,506 +Rsilicon-2026-05-10,baseline,E,3487,4,2500,253,506 +Rsilicon-2026-05-10,baseline,E,3488,4,2500,253,506 +Rsilicon-2026-05-10,baseline,E,3489,4,2500,253,506 +Rsilicon-2026-05-10,baseline,E,3490,4,2500,253,506 +Rsilicon-2026-05-10,baseline,E,3491,4,2500,253,506 +Rsilicon-2026-05-10,baseline,E,3492,4,2500,253,506 +Rsilicon-2026-05-10,baseline,E,3493,4,2500,253,506 +Rsilicon-2026-05-10,baseline,E,3494,4,2500,253,506 +Rsilicon-2026-05-10,baseline,E,3495,4,2500,253,506 +Rsilicon-2026-05-10,baseline,E,3496,4,2500,253,506 +Rsilicon-2026-05-10,baseline,E,3497,4,2500,253,506 +Rsilicon-2026-05-10,baseline,E,3498,4,2500,253,506 +Rsilicon-2026-05-10,baseline,E,3499,4,2500,253,506 +# Rsilicon-2026-05-10 baseline: step 5/13 rpm=2500 period_us=66 ints=1000 count=3500 +Rsilicon-2026-05-10,baseline,D,step_5,1180144934,199,120,50,71,118 +Rsilicon-2026-05-10,baseline,H,step_5,203573,23366,0 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+Rsilicon-2026-05-10,baseline,E,4488,5,3000,253,506 +Rsilicon-2026-05-10,baseline,E,4489,5,3000,253,506 +Rsilicon-2026-05-10,baseline,E,4490,5,3000,253,506 +Rsilicon-2026-05-10,baseline,E,4491,5,3000,253,506 +Rsilicon-2026-05-10,baseline,E,4492,5,3000,253,506 +Rsilicon-2026-05-10,baseline,E,4493,5,3000,253,506 +Rsilicon-2026-05-10,baseline,E,4494,5,3000,253,506 +Rsilicon-2026-05-10,baseline,E,4495,5,3000,253,506 +Rsilicon-2026-05-10,baseline,E,4496,5,3000,253,506 +Rsilicon-2026-05-10,baseline,E,4497,5,3000,253,506 +Rsilicon-2026-05-10,baseline,E,4498,5,3000,253,506 +Rsilicon-2026-05-10,baseline,E,4499,5,3000,253,506 +# Rsilicon-2026-05-10 baseline: step 6/13 rpm=3000 period_us=55 ints=1000 count=4500 +Rsilicon-2026-05-10,baseline,D,step_6,1521487943,223,175,212,192,131 +Rsilicon-2026-05-10,baseline,H,step_6,184054,22218,0 +Rsilicon-2026-05-10,baseline,E,4500,6,4000,253,1283 +Rsilicon-2026-05-10,baseline,E,4501,6,4000,253,506 +Rsilicon-2026-05-10,baseline,E,4502,6,4000,253,506 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+Rsilicon-2026-05-10,baseline,E,7407,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7408,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7409,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7410,10,8000,253,506 +Rsilicon-2026-05-10,baseline,E,7411,10,8000,253,506 +Rsilicon-2026-05-10,baseline,E,7412,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7413,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7414,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7415,10,8000,253,506 +Rsilicon-2026-05-10,baseline,E,7416,10,8000,253,506 +Rsilicon-2026-05-10,baseline,E,7417,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7418,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7419,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7420,10,8000,253,506 +Rsilicon-2026-05-10,baseline,E,7421,10,8000,253,506 +Rsilicon-2026-05-10,baseline,E,7422,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7423,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7424,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7425,10,8000,253,506 +Rsilicon-2026-05-10,baseline,E,7426,10,8000,253,506 +Rsilicon-2026-05-10,baseline,E,7427,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7428,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7429,10,8000,253,506 +Rsilicon-2026-05-10,baseline,E,7430,10,8000,253,506 +Rsilicon-2026-05-10,baseline,E,7431,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7432,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7433,10,8000,253,506 +Rsilicon-2026-05-10,baseline,E,7434,10,8000,253,506 +Rsilicon-2026-05-10,baseline,E,7435,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7436,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7437,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7438,10,8000,253,506 +Rsilicon-2026-05-10,baseline,E,7439,10,8000,253,506 +Rsilicon-2026-05-10,baseline,E,7440,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7441,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7442,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7443,10,8000,253,506 +Rsilicon-2026-05-10,baseline,E,7444,10,8000,253,506 +Rsilicon-2026-05-10,baseline,E,7445,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7446,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7447,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7448,10,8000,253,506 +Rsilicon-2026-05-10,baseline,E,7449,10,8000,253,506 +Rsilicon-2026-05-10,baseline,E,7450,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7451,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7452,10,8000,253,506 +Rsilicon-2026-05-10,baseline,E,7453,10,8000,253,506 +Rsilicon-2026-05-10,baseline,E,7454,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7455,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7456,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7457,10,8000,253,506 +Rsilicon-2026-05-10,baseline,E,7458,10,8000,253,506 +Rsilicon-2026-05-10,baseline,E,7459,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7460,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7461,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7462,10,8000,253,506 +Rsilicon-2026-05-10,baseline,E,7463,10,8000,253,506 +Rsilicon-2026-05-10,baseline,E,7464,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7465,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7466,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7467,10,8000,253,506 +Rsilicon-2026-05-10,baseline,E,7468,10,8000,253,506 +Rsilicon-2026-05-10,baseline,E,7469,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7470,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7471,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7472,10,8000,253,506 +Rsilicon-2026-05-10,baseline,E,7473,10,8000,253,506 +Rsilicon-2026-05-10,baseline,E,7474,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7475,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7476,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7477,10,8000,253,506 +Rsilicon-2026-05-10,baseline,E,7478,10,8000,253,506 +Rsilicon-2026-05-10,baseline,E,7479,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7480,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7481,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7482,10,8000,253,506 +Rsilicon-2026-05-10,baseline,E,7483,10,8000,253,506 +Rsilicon-2026-05-10,baseline,E,7484,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7485,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7486,10,8000,253,506 +Rsilicon-2026-05-10,baseline,E,7487,10,8000,253,506 +Rsilicon-2026-05-10,baseline,E,7488,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7489,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7490,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7491,10,8000,253,506 +Rsilicon-2026-05-10,baseline,E,7492,10,8000,253,506 +Rsilicon-2026-05-10,baseline,E,7493,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7494,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7495,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7496,10,8000,253,506 +Rsilicon-2026-05-10,baseline,E,7497,10,8000,253,506 +Rsilicon-2026-05-10,baseline,E,7498,10,8000,253,512 +Rsilicon-2026-05-10,baseline,E,7499,10,8000,253,512 +# Rsilicon-2026-05-10 baseline: step 11/13 rpm=8000 period_us=20 ints=200 count=7500 +Rsilicon-2026-05-10,baseline,D,step_11,2552486078,254,234,215,45,85 +Rsilicon-2026-05-10,baseline,H,step_11,128198,22318,0 +Rsilicon-2026-05-10,baseline,E,7500,11,9000,253,1283 +Rsilicon-2026-05-10,baseline,E,7501,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7502,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7503,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7504,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7505,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7506,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7507,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7508,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7509,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7510,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7511,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7512,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7513,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7514,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7515,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7516,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7517,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7518,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7519,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7520,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7521,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7522,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7523,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7524,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7525,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7526,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7527,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7528,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7529,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7530,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7531,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7532,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7533,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7534,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7535,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7536,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7537,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7538,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7539,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7540,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7541,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7542,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7543,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7544,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7545,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7546,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7547,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7548,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7549,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7550,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7551,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7552,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7553,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7554,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7555,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7556,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7557,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7558,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7559,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7560,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7561,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7562,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7563,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7564,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7565,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7566,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7567,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7568,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7569,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7570,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7571,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7572,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7573,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7574,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7575,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7576,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7577,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7578,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7579,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7580,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7581,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7582,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7583,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7584,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7585,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7586,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7587,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7588,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7589,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7590,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7591,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7592,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7593,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7594,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7595,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7596,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7597,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7598,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7599,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7600,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7601,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7602,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7603,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7604,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7605,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7606,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7607,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7608,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7609,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7610,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7611,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7612,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7613,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7614,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7615,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7616,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7617,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7618,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7619,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7620,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7621,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7622,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7623,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7624,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7625,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7626,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7627,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7628,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7629,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7630,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7631,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7632,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7633,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7634,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7635,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7636,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7637,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7638,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7639,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7640,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7641,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7642,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7643,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7644,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7645,11,9000,253,506 +Rsilicon-2026-05-10,baseline,E,7646,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7647,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7648,11,9000,253,512 +Rsilicon-2026-05-10,baseline,E,7649,11,9000,2# step 12/13 rpm=9000 period_us=18 ints=150 count=7649 +Rsilicon-2026-05-10,baseline,D,step_12,2607308156,178,232,192,178,167 +Rsilicon-2026-05-10,baseline,H,step_12,117087,23366,0 +Rsilicon-2026-05-10,baseline,E,7650,12,10000,253,506 +Rsilicon-2026-05-10,baseline,E,7651,12,10000,253,506 +Rsilicon-2026-05-10,baseline,E,7652,12,10000,253,506 +Rsilicon-2026-05-10,baseline,E,7653,12,10000,253,506 +Rsilicon-2026-05-10,baseline,E,7654,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7655,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7656,12,10000,253,506 +Rsilicon-2026-05-10,baseline,E,7657,12,10000,253,506 +Rsilicon-2026-05-10,baseline,E,7658,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7659,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7660,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7661,12,10000,253,506 +Rsilicon-2026-05-10,baseline,E,7662,12,10000,253,506 +Rsilicon-2026-05-10,baseline,E,7663,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7664,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7665,12,10000,253,506 +Rsilicon-2026-05-10,baseline,E,7666,12,10000,253,506 +Rsilicon-2026-05-10,baseline,E,7667,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7668,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7669,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7670,12,10000,253,506 +Rsilicon-2026-05-10,baseline,E,7671,12,10000,253,506 +Rsilicon-2026-05-10,baseline,E,7672,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7673,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7674,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7675,12,10000,253,506 +Rsilicon-2026-05-10,baseline,E,7676,12,10000,253,506 +Rsilicon-2026-05-10,baseline,E,7677,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7678,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7679,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7680,12,10000,253,506 +Rsilicon-2026-05-10,baseline,E,7681,12,10000,253,506 +Rsilicon-2026-05-10,baseline,E,7682,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7683,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7684,12,10000,253,506 +Rsilicon-2026-05-10,baseline,E,7685,12,10000,253,506 +Rsilicon-2026-05-10,baseline,E,7686,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7687,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7688,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7689,12,10000,253,506 +Rsilicon-2026-05-10,baseline,E,7690,12,10000,253,506 +Rsilicon-2026-05-10,baseline,E,7691,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7692,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7693,12,10000,253,506 +Rsilicon-2026-05-10,baseline,E,7694,12,10000,253,506 +Rsilicon-2026-05-10,baseline,E,7695,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7696,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7697,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7698,12,10000,253,506 +Rsilicon-2026-05-10,baseline,E,7699,12,10000,253,506 +Rsilicon-2026-05-10,baseline,E,7700,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7701,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7702,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7703,12,10000,253,506 +Rsilicon-2026-05-10,baseline,E,7704,12,10000,253,506 +Rsilicon-2026-05-10,baseline,E,7705,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7706,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7707,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7708,12,10000,253,506 +Rsilicon-2026-05-10,baseline,E,7709,12,10000,253,506 +Rsilicon-2026-05-10,baseline,E,7710,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7711,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7712,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7713,12,10000,253,506 +Rsilicon-2026-05-10,baseline,E,7714,12,10000,253,506 +Rsilicon-2026-05-10,baseline,E,7715,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7716,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7717,12,10000,253,506 +Rsilicon-2026-05-10,baseline,E,7718,12,10000,253,506 +Rsilicon-2026-05-10,baseline,E,7719,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7720,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7721,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7722,12,10000,253,506 +Rsilicon-2026-05-10,baseline,E,7723,12,10000,253,506 +Rsilicon-2026-05-10,baseline,E,7724,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7725,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7726,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7727,12,10000,253,506 +Rsilicon-2026-05-10,baseline,E,7728,12,10000,253,506 +Rsilicon-2026-05-10,baseline,E,7729,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7730,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7731,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7732,12,10000,253,506 +Rsilicon-2026-05-10,baseline,E,7733,12,10000,253,506 +Rsilicon-2026-05-10,baseline,E,7734,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7735,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7736,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7737,12,10000,253,506 +Rsilicon-2026-05-10,baseline,E,7738,12,10000,253,506 +Rsilicon-2026-05-10,baseline,E,7739,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7740,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7741,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7742,12,10000,253,506 +Rsilicon-2026-05-10,baseline,E,7743,12,10000,253,506 +Rsilicon-2026-05-10,baseline,E,7744,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7745,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7746,12,10000,253,512 +Rsilicon-2026-05-10,baseline,E,7747,12,10000,253,506 +Rsilicon-2026-05-10,baseline,E,7748,12,10000,253,506 +Rsilicon-2026-05-10,baseline,E,7749,12# step 13/13 rpm=10000 period_us=16 ints=100 count=7749 +Rsilicon-2026-05-10,baseline,D,step_13,2645927100,236,170,192,139,57 +Rsilicon-2026-05-10,baseline,H,step_13,88858,23366,0 +Rsilicon-2026-05-10,baseline,D,end,2647136780,35,82,192,79,255 +Rsilicon-2026-05-10,baseline,H,end,9880,25921,0 +M,Rsilicon-2026-05-10,baseline,drops,0 +M,Rsilicon-2026-05-10,baseline,samples,7750 +M,Rsilicon-2026-05-10,baseline,END diff --git a/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-8a4d817d-baseline-systick/firmware.elf b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-8a4d817d-baseline-systick/firmware.elf new file mode 100755 index 00000000..90958438 Binary files /dev/null and b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-8a4d817d-baseline-systick/firmware.elf differ diff --git a/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-8a4d817d-baseline-systick/firmware.elf.sha256 b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-8a4d817d-baseline-systick/firmware.elf.sha256 new file mode 100644 index 00000000..a948436a --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-8a4d817d-baseline-systick/firmware.elf.sha256 @@ -0,0 +1 @@ +5b73e47f7277da0644086844826a8985b143741c259b3a285dcdbdec0f3ee6b4 firmware.elf diff --git a/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-8a4d817d-baseline-systick/manifest.txt b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-8a4d817d-baseline-systick/manifest.txt new file mode 100644 index 00000000..fba01b47 --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-8a4d817d-baseline-systick/manifest.txt @@ -0,0 +1,23 @@ +# Silicon-anchor manifest +# Produced by benches/engine_control/silicon/capture.sh +captured_at: 2026-05-10T07:33:52Z +board: nucleo_g474re +variant: baseline +tick_source: systick +sweep: long +flash_runner: openocd +gale_sha: 8a4d817d1c414797f234cb1f7c0b8f3ddbbbaf41 +gale_status: 1 uncommitted file(s) +host: Darwin 25.3.0 arm64 +rustc: rustc 1.94.1 (e408947bf 2026-03-25) +cargo: cargo 1.94.1 (29ea6fb6a 2026-03-24) +west: West version: v1.5.0 +zephyr_base: /Volumes/Home/git/pulseengine/zephyr +zephyr_sha: fc4d89c118fc1d0ff0ad31906a4fa4bd252c9ced +sdk_dir: /Volumes/Home/zephyr-sdk/zephyr-sdk-1.0.1 +elf_sha256: 5b73e47f7277da0644086844826a8985b143741c259b3a285dcdbdec0f3ee6b4 +csv_sha256: 8e6ee18697503e42eac221ed127ae4e466eb3721b657ab46eb7395ed8d807163 +csv_bytes: 170637 +csv_event_lines: 7353 +serial_port: /dev/cu.usbmodem132203 +capture_timeout_s: 1800 diff --git a/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-8a4d817d-baseline-systick/output.csv b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-8a4d817d-baseline-systick/output.csv new file mode 100644 index 00000000..f136fbf2 --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-8a4d817d-baseline-systick/output.csv @@ -0,0 +1,7398 @@ +b��� +E,397,0,500,253,506 +E,398,0,500,253,506 +E,399,0,500,253,506 +E,400,0,500,253,506 +E,401,0,500,253,506 +E,402,0,500,253,506 +E,403,0,500,253,506 +E,404,0,500,253,506 +E,405,0,500,253,506 +E,406,0,500,253,506 +E,407,0,500,253,506 +E,408,0,500,253,506 +E,409,0,500,253,506 +E,410,0,500,253,506 +E,411,0,500,253,506 +E,412,0,500,253,506 +E,413,0,500,253,506 +E,414,0,500,253,506 +E,415,0,500,253,506 +E,416,0,500,253,506 +E,417,0,500,253,506 +E,418,0,500,253,506 +E,419,0,500,253,506 +E,420,0,500,253,506 +E,421,0,500,253,506 +E,422,0,500,253,506 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+E,470,0,500,253,506 +E,471,0,500,253,506 +E,472,0,500,253,506 +E,473,0,500,253,506 +E,474,0,500,253,506 +E,475,0,500,253,506 +E,476,0,500,253,506 +E,477,0,500,253,506 +E,478,0,500,253,506 +E,479,0,500,253,506 +E,480,0,500,253,506 +E,481,0,500,253,506 +E,482,0,500,253,506 +E,483,0,500,253,506 +E,484,0,500,253,506 +E,485,0,500,253,506 +E,486,0,500,253,506 +E,487,0,500,253,506 +E,488,0,500,253,506 +E,489,0,500,253,506 +E,490,0,500,253,506 +E,491,0,500,253,506 +E,492,0,500,253,506 +E,493,0,500,253,506 +E,494,0,500,253,506 +E,495,0,500,253,506 +E,496,0,500,253,506 +E,497,0,500,253,506 +E,498,0,500,253,506 +E,4# step 1/13 rpm=500 period_us=333 ints=500 count=499 +D,step_1,161291164,252,48,223,111,196 +H,step_1,159729,22218,0 +99,0,500,253,506 +E,500,1,1000,253,506 +E,501,1,1000,253,506 +E,502,1,1000,253,506 +E,503,1,1000,253,506 +E,504,1,1000,253,506 +E,505,1,1000,253,506 +E,506,1,1000,253,506 +E,507,1,1000,253,506 +E,508,1,1000,253,506 +E,509,1,1000,253,506 +E,510,1,1000,253,506 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+E,7287,9,7000,253,506 +E,7288,9,7000,253,506 +E,7289,9,7000,253,506 +E,7290,9,7000,253,506 +E,7291,9,7000,253,506 +E,7292,9,7000,253,506 +E,7293,9,7000,253,506 +E,7294,9,7000,253,506 +E,7295,9,7000,253,506 +E,7296,9,7000,253,506 +E,7297,9,7000,253,506 +E,7298,9,7000,253,506 +E,7299,9,7000,253,5# step 10/13 rpm=7000 period_us=23 ints=300 count=7299 +D,step_10,2479712726,37,149,221,138,33 +H,step_10,160630,22726,0 +06 +E,7300,10,8000,253,506 +E,7301,10,8000,253,506 +E,7302,10,8000,253,506 +E,7303,10,8000,253,506 +E,7304,10,8000,253,512 +E,7305,10,8000,253,512 +E,7306,10,8000,253,506 +E,7307,10,8000,253,506 +E,7308,10,8000,253,512 +E,7309,10,8000,253,512 +E,7310,10,8000,253,512 +E,7311,10,8000,253,506 +E,7312,10,8000,253,506 +E,7313,10,8000,253,512 +E,7314,10,8000,253,512 +E,7315,10,8000,253,512 +E,7316,10,8000,253,506 +E,7317,10,8000,253,506 +E,7318,10,8000,253,512 +E,7319,10,8000,253,512 +E,7320,10,8000,253,506 +E,7321,10,8000,253,506 +E,7322,10,8000,253,512 +E,7323,10,8000,253,512 +E,7324,10,8000,253,512 +E,7325,10,8000,253,506 +E,7326,10,8000,253,506 +E,7327,10,8000,253,512 +E,7328,10,8000,253,512 +E,7329,10,8000,253,506 +E,7330,10,8000,253,506 +E,7331,10,8000,253,512 +E,7332,10,8000,253,512 +E,7333,10,8000,253,512 +E,7334,10,8000,253,506 +E,7335,10,8000,253,506 +E,7336,10,8000,253,512 +E,7337,10,8000,253,512 +E,7338,10,8000,253,512 +E,7339,10,8000,253,506 +E,7340,10,8000,253,506 +E,7341,10,8000,253,512 +E,7342,10,8000,253,512 +E,7343,10,8000,253,512 +E,7344,10,8000,253,506 +E,7345,10,8000,253,506 +E,7346,10,8000,253,512 +E,7347,10,8000,253,512 +E,7348,10,8000,253,506 +E,7349,10,8000,253,506 +E,7350,10,8000,253,512 +E,7351,10,8000,253,512 +E,7352,10,8000,253,512 +E,7353,10,8000,253,506 +E,7354,10,8000,253,506 +E,7355,10,8000,253,512 +E,7356,10,8000,253,512 +E,7357,10,8000,253,512 +E,7358,10,8000,253,506 +E,7359,10,8000,253,506 +E,7360,10,8000,253,512 +E,7361,10,8000,253,512 +E,7362,10,8000,253,506 +E,7363,10,8000,253,506 +E,7364,10,8000,253,512 +E,7365,10,8000,253,512 +E,7366,10,8000,253,512 +E,7367,10,8000,253,506 +E,7368,10,8000,253,506 +E,7369,10,8000,253,512 +E,7370,10,8000,253,512 +E,7371,10,8000,253,512 +E,7372,10,8000,253,506 +E,7373,10,8000,253,506 +E,7374,10,8000,253,512 +E,7375,10,8000,253,512 +E,7376,10,8000,253,512 +E,7377,10,8000,253,506 +E,7378,10,8000,253,506 +E,7379,10,8000,253,512 +E,7380,10,8000,253,512 +E,7381,10,8000,253,506 +E,7382,10,8000,253,506 +E,7383,10,8000,253,512 +E,7384,10,8000,253,512 +E,7385,10,8000,253,512 +E,7386,10,8000,253,506 +E,7387,10,8000,253,506 +E,7388,10,8000,253,512 +E,7389,10,8000,253,512 +E,7390,10,8000,253,512 +E,7391,10,8000,253,506 +E,7392,10,8000,253,506 +E,7393,10,8000,253,512 +E,7394,10,8000,253,512 +E,7395,10,8000,253,512 +E,7396,10,8000,253,506 +E,7397,10,8000,253,506 +E,7398,10,8000,253,512 +E,7399,10,8000,253,512 +E,7400,10,8000,253,506 +E,7401,10,8000,253,506 +E,7402,10,8000,253,512 +E,7403,10,8000,253,512 +E,7404,10,8000,253,512 +E,7405,10,8000,253,506 +E,7406,10,8000,253,506 +E,7407,10,8000,253,512 +E,7408,10,8000,253,512 +E,7409,10,8000,253,512 +E,7410,10,8000,253,506 +E,7411,10,8000,253,506 +E,7412,10,8000,253,512 +E,7413,10,8000,253,512 +E,7414,10,8000,253,512 +E,7415,10,8000,253,506 +E,7416,10,8000,253,506 +E,7417,10,8000,253,512 +E,7418,10,8000,253,512 +E,7419,10,8000,253,512 +E,7420,10,8000,253,506 +E,7421,10,8000,253,506 +E,7422,10,8000,253,512 +E,7423,10,8000,253,512 +E,7424,10,8000,253,512 +E,7425,10,8000,253,506 +E,7426,10,8000,253,506 +E,7427,10,8000,253,512 +E,7428,10,8000,253,512 +E,7429,10,8000,253,506 +E,7430,10,8000,253,506 +E,7431,10,8000,253,512 +E,7432,10,8000,253,512 +E,7433,10,8000,253,506 +E,7434,10,8000,253,506 +E,7435,10,8000,253,512 +E,7436,10,8000,253,512 +E,7437,10,8000,253,512 +E,7438,10,8000,253,506 +E,7439,10,8000,253,506 +E,7440,10,8000,253,512 +E,7441,10,8000,253,512 +E,7442,10,8000,253,512 +E,7443,10,8000,253,506 +E,7444,10,8000,253,506 +E,7445,10,8000,253,512 +E,7446,10,8000,253,512 +E,7447,10,8000,253,512 +E,7448,10,8000,253,506 +E,7449,10,8000,253,506 +E,7450,10,8000,253,512 +E,7451,10,8000,253,512 +E,7452,10,8000,253,506 +E,7453,10,8000,253,506 +E,7454,10,8000,253,512 +E,7455,10,8000,253,512 +E,7456,10,8000,253,512 +E,7457,10,8000,253,506 +E,7458,10,8000,253,506 +E,7459,10,8000,253,512 +E,7460,10,8000,253,512 +E,7461,10,8000,253,512 +E,7462,10,8000,253,506 +E,7463,10,8000,253,506 +E,7464,10,8000,253,512 +E,7465,10,8000,253,512 +E,7466,10,8000,253,512 +E,7467,10,8000,253,506 +E,7468,10,8000,253,506 +E,7469,10,8000,253,512 +E,7470,10,8000,253,512 +E,7471,10,8000,253,512 +E,7472,10,8000,253,506 +E,7473,10,8000,253,506 +E,7474,10,8000,253,512 +E,7475,10,8000,253,512 +E,7476,10,8000,253,512 +E,7477,10,8000,253,506 +E,7478,10,8000,253,506 +E,7479,10,8000,253,512 +E,7480,10,8000,253,512 +E,7481,10,8000,253,512 +E,7482,10,8000,253,506 +E,7483,10,8000,253,506 +E,7484,10,8000,253,512 +E,7485,10,8000,253,512 +E,7486,10,8000,253,506 +E,7487,10,8000,253,506 +E,7488,10,8000,253,512 +E,7489,10,8000,253,512 +E,7490,10,8000,253,512 +E,7491,10,8000,253,506 +E,7492,10,8000,253,506 +E,7493,10,8000,253,512 +E,7494,10,8000,253,512 +E,7495,10,8000,253,512 +E,7496,10,8000,253,506 +E,7497,10,8000,253,506 +E,7498,10,8000,253,512 +E,7499,10,8000,253,512 +# step 11/13 rpm=8000 period_us=20 ints=200 count=7500 +D,step_11,2552486078,254,234,215,45,85 +H,step_11,128198,22318,0 +E,7500,11,9000,253,1283 +E,7501,11,9000,253,506 +E,7502,11,9000,253,506 +E,7503,11,9000,253,512 +E,7504,11,9000,253,512 +E,7505,11,9000,253,506 +E,7506,11,9000,253,506 +E,7507,11,9000,253,512 +E,7508,11,9000,253,512 +E,7509,11,9000,253,506 +E,7510,11,9000,253,506 +E,7511,11,9000,253,512 +E,7512,11,9000,253,512 +E,7513,11,9000,253,512 +E,7514,11,9000,253,506 +E,7515,11,9000,253,506 +E,7516,11,9000,253,512 +E,7517,11,9000,253,512 +E,7518,11,9000,253,512 +E,7519,11,9000,253,506 +E,7520,11,9000,253,506 +E,7521,11,9000,253,512 +E,7522,11,9000,253,512 +E,7523,11,9000,253,512 +E,7524,11,9000,253,506 +E,7525,11,9000,253,506 +E,7526,11,9000,253,512 +E,7527,11,9000,253,512 +E,7528,11,9000,253,512 +E,7529,11,9000,253,506 +E,7530,11,9000,253,506 +E,7531,11,9000,253,512 +E,7532,11,9000,253,512 +E,7533,11,9000,253,506 +E,7534,11,9000,253,506 +E,7535,11,9000,253,512 +E,7536,11,9000,253,512 +E,7537,11,9000,253,512 +E,7538,11,9000,253,506 +E,7539,11,9000,253,506 +E,7540,11,9000,253,512 +E,7541,11,9000,253,512 +E,7542,11,9000,253,512 +E,7543,11,9000,253,506 +E,7544,11,9000,253,506 +E,7545,11,9000,253,512 +E,7546,11,9000,253,512 +E,7547,11,9000,253,512 +E,7548,11,9000,253,506 +E,7549,11,9000,253,506 +E,7550,11,9000,253,512 +E,7551,11,9000,253,512 +E,7552,11,9000,253,506 +E,7553,11,9000,253,506 +E,7554,11,9000,253,512 +E,7555,11,9000,253,512 +E,7556,11,9000,253,512 +E,7557,11,9000,253,506 +E,7558,11,9000,253,506 +E,7559,11,9000,253,512 +E,7560,11,9000,253,512 +E,7561,11,9000,253,512 +E,7562,11,9000,253,506 +E,7563,11,9000,253,506 +E,7564,11,9000,253,512 +E,7565,11,9000,253,512 +E,7566,11,9000,253,506 +E,7567,11,9000,253,506 +E,7568,11,9000,253,512 +E,7569,11,9000,253,512 +E,7570,11,9000,253,512 +E,7571,11,9000,253,506 +E,7572,11,9000,253,506 +E,7573,11,9000,253,512 +E,7574,11,9000,253,512 +E,7575,11,9000,253,512 +E,7576,11,9000,253,506 +E,7577,11,9000,253,506 +E,7578,11,9000,253,512 +E,7579,11,9000,253,512 +E,7580,11,9000,253,512 +E,7581,11,9000,253,506 +E,7582,11,9000,253,506 +E,7583,11,9000,253,512 +E,7584,11,9000,253,512 +E,7585,11,9000,253,512 +E,7586,11,9000,253,506 +E,7587,11,9000,253,506 +E,7588,11,9000,253,512 +E,7589,11,9000,253,512 +E,7590,11,9000,253,512 +E,7591,11,9000,253,506 +E,7592,11,9000,253,506 +E,7593,11,9000,253,512 +E,7594,11,9000,253,512 +E,7595,11,9000,253,512 +E,7596,11,9000,253,506 +E,7597,11,9000,253,506 +E,7598,11,9000,253,512 +E,7599,11,9000,253,512 +E,7600,11,9000,253,512 +E,7601,11,9000,253,506 +E,7602,11,9000,253,506 +E,7603,11,9000,253,512 +E,7604,11,9000,253,512 +E,7605,11,9000,253,512 +E,7606,11,9000,253,506 +E,7607,11,9000,253,506 +E,7608,11,9000,253,512 +E,7609,11,9000,253,512 +E,7610,11,9000,253,506 +E,7611,11,9000,253,506 +E,7612,11,9000,253,512 +E,7613,11,9000,253,512 +E,7614,11,9000,253,512 +E,7615,11,9000,253,506 +E,7616,11,9000,253,506 +E,7617,11,9000,253,512 +E,7618,11,9000,253,512 +E,7619,11,9000,253,512 +E,7620,11,9000,253,506 +E,7621,11,9000,253,506 +E,7622,11,9000,253,512 +E,7623,11,9000,253,512 +E,7624,11,9000,253,512 +E,7625,11,9000,253,506 +E,7626,11,9000,253,506 +E,7627,11,9000,253,512 +E,7628,11,9000,253,512 +E,7629,11,9000,253,512 +E,7630,11,9000,253,506 +E,7631,11,9000,253,506 +E,7632,11,9000,253,512 +E,7633,11,9000,253,512 +E,7634,11,9000,253,512 +E,7635,11,9000,253,506 +E,7636,11,9000,253,506 +E,7637,11,9000,253,512 +E,7638,11,9000,253,512 +E,7639,11,9000,253,506 +E,7640,11,9000,253,506 +E,7641,11,9000,253,512 +E,7642,11,9000,253,512 +E,7643,11,9000,253,512 +E,7644,11,9000,253,506 +E,7645,11,9000,253,506 +E,7646,11,9000,253,512 +E,7647,11,9000,253,512 +E,7648,11,9000,253,512 +E,7649,11,9000,2# step 12/13 rpm=9000 period_us=18 ints=150 count=7649 +D,step_12,2607308156,178,232,192,178,167 +H,step_12,117087,23366,0 +53,506 +E,7650,12,10000,253,506 +E,7651,12,10000,253,506 +E,7652,12,10000,253,506 +E,7653,12,10000,253,506 +E,7654,12,10000,253,512 +E,7655,12,10000,253,512 +E,7656,12,10000,253,506 +E,7657,12,10000,253,506 +E,7658,12,10000,253,512 +E,7659,12,10000,253,512 +E,7660,12,10000,253,512 +E,7661,12,10000,253,506 +E,7662,12,10000,253,506 +E,7663,12,10000,253,512 +E,7664,12,10000,253,512 +E,7665,12,10000,253,506 +E,7666,12,10000,253,506 +E,7667,12,10000,253,512 +E,7668,12,10000,253,512 +E,7669,12,10000,253,512 +E,7670,12,10000,253,506 +E,7671,12,10000,253,506 +E,7672,12,10000,253,512 +E,7673,12,10000,253,512 +E,7674,12,10000,253,512 +E,7675,12,10000,253,506 +E,7676,12,10000,253,506 +E,7677,12,10000,253,512 +E,7678,12,10000,253,512 +E,7679,12,10000,253,512 +E,7680,12,10000,253,506 +E,7681,12,10000,253,506 +E,7682,12,10000,253,512 +E,7683,12,10000,253,512 +E,7684,12,10000,253,506 +E,7685,12,10000,253,506 +E,7686,12,10000,253,512 +E,7687,12,10000,253,512 +E,7688,12,10000,253,512 +E,7689,12,10000,253,506 +E,7690,12,10000,253,506 +E,7691,12,10000,253,512 +E,7692,12,10000,253,512 +E,7693,12,10000,253,506 +E,7694,12,10000,253,506 +E,7695,12,10000,253,512 +E,7696,12,10000,253,512 +E,7697,12,10000,253,512 +E,7698,12,10000,253,506 +E,7699,12,10000,253,506 +E,7700,12,10000,253,512 +E,7701,12,10000,253,512 +E,7702,12,10000,253,512 +E,7703,12,10000,253,506 +E,7704,12,10000,253,506 +E,7705,12,10000,253,512 +E,7706,12,10000,253,512 +E,7707,12,10000,253,512 +E,7708,12,10000,253,506 +E,7709,12,10000,253,506 +E,7710,12,10000,253,512 +E,7711,12,10000,253,512 +E,7712,12,10000,253,512 +E,7713,12,10000,253,506 +E,7714,12,10000,253,506 +E,7715,12,10000,253,512 +E,7716,12,10000,253,512 +E,7717,12,10000,253,506 +E,7718,12,10000,253,506 +E,7719,12,10000,253,512 +E,7720,12,10000,253,512 +E,7721,12,10000,253,512 +E,7722,12,10000,253,506 +E,7723,12,10000,253,506 +E,7724,12,10000,253,512 +E,7725,12,10000,253,512 +E,7726,12,10000,253,512 +E,7727,12,10000,253,506 +E,7728,12,10000,253,506 +E,7729,12,10000,253,512 +E,7730,12,10000,253,512 +E,7731,12,10000,253,512 +E,7732,12,10000,253,506 +E,7733,12,10000,253,506 +E,7734,12,10000,253,512 +E,7735,12,10000,253,512 +E,7736,12,10000,253,512 +E,7737,12,10000,253,506 +E,7738,12,10000,253,506 +E,7739,12,10000,253,512 +E,7740,12,10000,253,512 +E,7741,12,10000,253,512 +E,7742,12,10000,253,506 +E,7743,12,10000,253,506 +E,7744,12,10000,253,512 +E,7745,12,10000,253,512 +E,7746,12,10000,253,512 +E,7747,12,10000,253,506 +E,7748,12,10000,253,506 +E,7749,12# step 13/13 rpm=10000 period_us=16 ints=100 count=7749 +D,step_13,2645927100,236,170,192,139,57 +H,step_13,88858,23366,0 +,10000,253,512 +D,end,2647136780,35,82,192,79,255 +H,end,9880,25921,0 +drops,0 +samples,7750 +=== END === diff --git a/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-8a4d817d-gale-systick/events.csv b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-8a4d817d-gale-systick/events.csv new file mode 100644 index 00000000..83a2a818 --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-8a4d817d-gale-systick/events.csv @@ -0,0 +1,7406 @@ +# Rsilicon-2026-05-10 gale: DWT rows: D,,,,,,, +# Rsilicon-2026-05-10 gale: health rows:H,,,, +Rsilicon-2026-05-10,gale,D,boot,6498924,193,52,0,210,151 +Rsilicon-2026-05-10,gale,H,boot,211981,27650,0 +Rsilicon-2026-05-10,gale,E,0,0,500,253,1345 +Rsilicon-2026-05-10,gale,E,1,0,500,253,582 +Rsilicon-2026-05-10,gale,E,2,0,500,253,582 +Rsilicon-2026-05-10,gale,E,3,0,500,253,582 +Rsilicon-2026-05-10,gale,E,4,0,500,253,582 +Rsilicon-2026-05-10,gale,E,5,0,500,253,582 +Rsilicon-2026-05-10,gale,E,6,0,500,253,582 +Rsilicon-2026-05-10,gale,E,7,0,500,253,582 +Rsilicon-2026-05-10,gale,E,8,0,500,253,582 +Rsilicon-2026-05-10,gale,E,9,0,500,253,582 +Rsilicon-2026-05-10,gale,E,10,0,500,253,582 +Rsilicon-2026-05-10,gale,E,11,0,500,253,582 +Rsilicon-2026-05-10,gale,E,12,0,500,253,582 +Rsilicon-2026-05-10,gale,E,13,0,500,253,582 +Rsilicon-2026-05-10,gale,E,14,0,500,253,582 +Rsilicon-2026-05-10,gale,E,15,0,500,253,582 +Rsilicon-2026-05-10,gale,E,16,0,500,253,582 +Rsilicon-2026-05-10,gale,E,17,0,500,253,582 +Rsilicon-2026-05-10,gale,E,18,0,500,253,582 +Rsilicon-2026-05-10,gale,E,19,0,500,253,582 +Rsilicon-2026-05-10,gale,E,20,0,500,253,582 +Rsilicon-2026-05-10,gale,E,21���b���b�’ +Rsilicon-2026-05-10,gale,E,409,0,500,253,582 +Rsilicon-2026-05-10,gale,E,410,0,500,253,582 +Rsilicon-2026-05-10,gale,E,411,0,500,253,582 +Rsilicon-2026-05-10,gale,E,412,0,500,253,582 +Rsilicon-2026-05-10,gale,E,413,0,500,253,582 +Rsilicon-2026-05-10,gale,E,414,0,500,253,582 +Rsilicon-2026-05-10,gale,E,415,0,500,253,582 +Rsilicon-2026-05-10,gale,E,416,0,500,253,582 +Rsilicon-2026-05-10,gale,E,417,0,500,253,582 +Rsilicon-2026-05-10,gale,E,418,0,500,253,582 +Rsilicon-2026-05-10,gale,E,419,0,500,253,582 +Rsilicon-2026-05-10,gale,E,420,0,500,253,582 +Rsilicon-2026-05-10,gale,E,421,0,500,253,582 +Rsilicon-2026-05-10,gale,E,422,0,500,253,582 +Rsilicon-2026-05-10,gale,E,423,0,500,253,582 +Rsilicon-2026-05-10,gale,E,424,0,500,253,582 +Rsilicon-2026-05-10,gale,E,425,0,500,253,582 +Rsilicon-2026-05-10,gale,E,426,0,500,253,582 +Rsilicon-2026-05-10,gale,E,427,0,500,253,582 +Rsilicon-2026-05-10,gale,E,428,0,500,253,582 +Rsilicon-2026-05-10,gale,E,429,0,500,253,582 +Rsilicon-2026-05-10,gale,E,430,0,500,253,582 +Rsilicon-2026-05-10,gale,E,431,0,500,253,582 +Rsilicon-2026-05-10,gale,E,432,0,500,253,582 +Rsilicon-2026-05-10,gale,E,433,0,500,253,582 +Rsilicon-2026-05-10,gale,E,434,0,500,253,582 +Rsilicon-2026-05-10,gale,E,435,0,500,253,582 +Rsilicon-2026-05-10,gale,E,436,0,500,253,582 +Rsilicon-2026-05-10,gale,E,437,0,500,253,582 +Rsilicon-2026-05-10,gale,E,438,0,500,253,582 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+Rsilicon-2026-05-10,gale,E,7584,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7585,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7586,11,9000,253,588 +Rsilicon-2026-05-10,gale,E,7587,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7588,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7589,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7590,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7591,11,9000,253,588 +Rsilicon-2026-05-10,gale,E,7592,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7593,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7594,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7595,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7596,11,9000,253,588 +Rsilicon-2026-05-10,gale,E,7597,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7598,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7599,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7600,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7601,11,9000,253,588 +Rsilicon-2026-05-10,gale,E,7602,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7603,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7604,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7605,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7606,11,9000,253,588 +Rsilicon-2026-05-10,gale,E,7607,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7608,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7609,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7610,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7611,11,9000,253,588 +Rsilicon-2026-05-10,gale,E,7612,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7613,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7614,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7615,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7616,11,9000,253,588 +Rsilicon-2026-05-10,gale,E,7617,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7618,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7619,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7620,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7621,11,9000,253,588 +Rsilicon-2026-05-10,gale,E,7622,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7623,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7624,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7625,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7626,11,9000,253,588 +Rsilicon-2026-05-10,gale,E,7627,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7628,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7629,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7630,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7631,11,9000,253,588 +Rsilicon-2026-05-10,gale,E,7632,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7633,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7634,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7635,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7636,11,9000,253,588 +Rsilicon-2026-05-10,gale,E,7637,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7638,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7639,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7640,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7641,11,9000,253,588 +Rsilicon-2026-05-10,gale,E,7642,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7643,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7644,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7645,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7646,11,9000,253,588 +Rsilicon-2026-05-10,gale,E,7647,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7648,11,9000,253,582 +Rsilicon-2026-05-10,gale,E,7649,11,9000,25# step 12/13 rpm=9000 period_us=18 ints=150 count=7649 +Rsilicon-2026-05-10,gale,D,step_12,2607228370,190,44,161,27,121 +Rsilicon-2026-05-10,gale,H,step_12,116486,22418,0 +Rsilicon-2026-05-10,gale,E,7650,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7651,12,10000,253,588 +Rsilicon-2026-05-10,gale,E,7652,12,10000,253,588 +Rsilicon-2026-05-10,gale,E,7653,12,10000,253,588 +Rsilicon-2026-05-10,gale,E,7654,12,10000,253,588 +Rsilicon-2026-05-10,gale,E,7655,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7656,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7657,12,10000,253,588 +Rsilicon-2026-05-10,gale,E,7658,12,10000,253,588 +Rsilicon-2026-05-10,gale,E,7659,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7660,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7661,12,10000,253,588 +Rsilicon-2026-05-10,gale,E,7662,12,10000,253,588 +Rsilicon-2026-05-10,gale,E,7663,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7664,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7665,12,10000,253,588 +Rsilicon-2026-05-10,gale,E,7666,12,10000,253,588 +Rsilicon-2026-05-10,gale,E,7667,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7668,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7669,12,10000,253,588 +Rsilicon-2026-05-10,gale,E,7670,12,10000,253,588 +Rsilicon-2026-05-10,gale,E,7671,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7672,12,10000,253,588 +Rsilicon-2026-05-10,gale,E,7673,12,10000,253,588 +Rsilicon-2026-05-10,gale,E,7674,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7675,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7676,12,10000,253,588 +Rsilicon-2026-05-10,gale,E,7677,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7678,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7679,12,10000,253,588 +Rsilicon-2026-05-10,gale,E,7680,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7681,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7682,12,10000,253,588 +Rsilicon-2026-05-10,gale,E,7683,12,10000,253,588 +Rsilicon-2026-05-10,gale,E,7684,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7685,12,10000,253,588 +Rsilicon-2026-05-10,gale,E,7686,12,10000,253,588 +Rsilicon-2026-05-10,gale,E,7687,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7688,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7689,12,10000,253,588 +Rsilicon-2026-05-10,gale,E,7690,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7691,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7692,12,10000,253,588 +Rsilicon-2026-05-10,gale,E,7693,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7694,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7695,12,10000,253,588 +Rsilicon-2026-05-10,gale,E,7696,12,10000,253,588 +Rsilicon-2026-05-10,gale,E,7697,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7698,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7699,12,10000,253,588 +Rsilicon-2026-05-10,gale,E,7700,12,10000,253,588 +Rsilicon-2026-05-10,gale,E,7701,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7702,12,10000,253,588 +Rsilicon-2026-05-10,gale,E,7703,12,10000,253,588 +Rsilicon-2026-05-10,gale,E,7704,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7705,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7706,12,10000,253,588 +Rsilicon-2026-05-10,gale,E,7707,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7708,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7709,12,10000,253,588 +Rsilicon-2026-05-10,gale,E,7710,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7711,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7712,12,10000,253,588 +Rsilicon-2026-05-10,gale,E,7713,12,10000,253,588 +Rsilicon-2026-05-10,gale,E,7714,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7715,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7716,12,10000,253,588 +Rsilicon-2026-05-10,gale,E,7717,12,10000,253,588 +Rsilicon-2026-05-10,gale,E,7718,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7719,12,10000,253,588 +Rsilicon-2026-05-10,gale,E,7720,12,10000,253,588 +Rsilicon-2026-05-10,gale,E,7721,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7722,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7723,12,10000,253,588 +Rsilicon-2026-05-10,gale,E,7724,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7725,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7726,12,10000,253,588 +Rsilicon-2026-05-10,gale,E,7727,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7728,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7729,12,10000,253,588 +Rsilicon-2026-05-10,gale,E,7730,12,10000,253,588 +Rsilicon-2026-05-10,gale,E,7731,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7732,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7733,12,10000,253,588 +Rsilicon-2026-05-10,gale,E,7734,12,10000,253,588 +Rsilicon-2026-05-10,gale,E,7735,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7736,12,10000,253,588 +Rsilicon-2026-05-10,gale,E,7737,12,10000,253,588 +Rsilicon-2026-05-10,gale,E,7738,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7739,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7740,12,10000,253,588 +Rsilicon-2026-05-10,gale,E,7741,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7742,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7743,12,10000,253,588 +Rsilicon-2026-05-10,gale,E,7744,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7745,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7746,12,10000,253,588 +Rsilicon-2026-05-10,gale,E,7747,12,10000,253,588 +Rsilicon-2026-05-10,gale,E,7748,12,10000,253,582 +Rsilicon-2026-05-10,gale,E,7749,12,# step 13/13 rpm=10000 period_us=16 ints=100 count=7749 +Rsilicon-2026-05-10,gale,D,step_13,2645817802,240,143,161,156,228 +Rsilicon-2026-05-10,gale,H,step_13,91861,23257,0 +Rsilicon-2026-05-10,gale,D,end,2647027500,4,55,161,205,180 +Rsilicon-2026-05-10,gale,H,end,9280,28118,0 +M,Rsilicon-2026-05-10,gale,drops,0 +M,Rsilicon-2026-05-10,gale,samples,7750 +M,Rsilicon-2026-05-10,gale,END diff --git a/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-8a4d817d-gale-systick/firmware.elf b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-8a4d817d-gale-systick/firmware.elf new file mode 100755 index 00000000..c36860b1 Binary files /dev/null and b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-8a4d817d-gale-systick/firmware.elf differ diff --git a/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-8a4d817d-gale-systick/firmware.elf.sha256 b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-8a4d817d-gale-systick/firmware.elf.sha256 new file mode 100644 index 00000000..041e99bf --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-8a4d817d-gale-systick/firmware.elf.sha256 @@ -0,0 +1 @@ +4798174d3a55abd8ecc0c8eb7cfd2c4b945370bf20639934ec9708c5a6a7c440 firmware.elf diff --git a/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-8a4d817d-gale-systick/manifest.txt b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-8a4d817d-gale-systick/manifest.txt new file mode 100644 index 00000000..4d94c655 --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-8a4d817d-gale-systick/manifest.txt @@ -0,0 +1,23 @@ +# Silicon-anchor manifest +# Produced by benches/engine_control/silicon/capture.sh +captured_at: 2026-05-10T07:34:18Z +board: nucleo_g474re +variant: gale +tick_source: systick +sweep: long +flash_runner: openocd +gale_sha: 8a4d817d1c414797f234cb1f7c0b8f3ddbbbaf41 +gale_status: 2 uncommitted file(s) +host: Darwin 25.3.0 arm64 +rustc: rustc 1.94.1 (e408947bf 2026-03-25) +cargo: cargo 1.94.1 (29ea6fb6a 2026-03-24) +west: West version: v1.5.0 +zephyr_base: /Volumes/Home/git/pulseengine/zephyr +zephyr_sha: fc4d89c118fc1d0ff0ad31906a4fa4bd252c9ced +sdk_dir: /Volumes/Home/zephyr-sdk/zephyr-sdk-1.0.1 +elf_sha256: 4798174d3a55abd8ecc0c8eb7cfd2c4b945370bf20639934ec9708c5a6a7c440 +csv_sha256: b62b00668974f431b2699b6407681054bd35b7533e891c934daa267d252c9fbc +csv_bytes: 171032 +csv_event_lines: 7363 +serial_port: /dev/cu.usbmodem132203 +capture_timeout_s: 1800 diff --git a/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-8a4d817d-gale-systick/output.csv b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-8a4d817d-gale-systick/output.csv new file mode 100644 index 00000000..3e82e154 --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-8a4d817d-gale-systick/output.csv @@ -0,0 +1,7412 @@ +,,, +# DWT rows: D,,,,,,, +# health rows:H,,,, +D,boot,6498924,193,52,0,210,151 +H,boot,211981,27650,0 +E,0,0,500,253,1345 +E,1,0,500,253,582 +E,2,0,500,253,582 +E,3,0,500,253,582 +E,4,0,500,253,582 +E,5,0,500,253,582 +E,6,0,500,253,582 +E,7,0,500,253,582 +E,8,0,500,253,582 +E,9,0,500,253,582 +E,10,0,500,253,582 +E,11,0,500,253,582 +E,12,0,500,253,582 +E,13,0,500,253,582 +E,14,0,500,253,582 +E,15,0,500,253,582 +E,16,0,500,253,582 +E,17,0,500,253,582 +E,18,0,500,253,582 +E,19,0,500,253,582 +E,20,0,500,253,582 +E,21���b���b�’ +E,409,0,500,253,582 +E,410,0,500,253,582 +E,411,0,500,253,582 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+E,459,0,500,253,582 +E,460,0,500,253,582 +E,461,0,500,253,582 +E,462,0,500,253,582 +E,463,0,500,253,582 +E,464,0,500,253,582 +E,465,0,500,253,582 +E,466,0,500,253,582 +E,467,0,500,253,582 +E,468,0,500,253,582 +E,469,0,500,253,582 +E,470,0,500,253,582 +E,471,0,500,253,582 +E,472,0,500,253,582 +E,473,0,500,253,582 +E,474,0,500,253,582 +E,475,0,500,253,582 +E,476,0,500,253,582 +E,477,0,500,253,582 +E,478,0,500,253,582 +E,479,0,500,253,582 +E,480,0,500,253,582 +E,481,0,500,253,582 +E,482,0,500,253,582 +E,483,0,500,253,582 +E,484,0,500,253,582 +E,485,0,500,253,582 +E,486,0,500,253,582 +E,487,0,500,253,582 +E,488,0,500,253,582 +E,489,0,500,253,582 +E,490,0,500,253,582 +E,491,0,500,253,582 +E,492,0,500,253,582 +E,493,0,500,253,582 +E,494,0,500,253,582 +E,495,0,500,253,582 +E,496,0,500,253,582 +E,497,0,500,253,582 +E,498,0,500,253,582 +E,4# step 1/13 rpm=500 period_us=333 ints=500 count=499 +D,step_1,161231651,178,89,46,71,141 +H,step_1,168438,22318,0 +99,0,500,253,582 +E,500,1,1000,253,582 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+E,7478,10,8000,253,588 +E,7479,10,8000,253,582 +E,7480,10,8000,253,582 +E,7481,10,8000,253,588 +E,7482,10,8000,253,588 +E,7483,10,8000,253,582 +E,7484,10,8000,253,588 +E,7485,10,8000,253,588 +E,7486,10,8000,253,582 +E,7487,10,8000,253,582 +E,7488,10,8000,253,588 +E,7489,10,8000,253,582 +E,7490,10,8000,253,582 +E,7491,10,8000,253,588 +E,7492,10,8000,253,582 +E,7493,10,8000,253,582 +E,7494,10,8000,253,588 +E,7495,10,8000,253,588 +E,7496,10,8000,253,582 +E,7497,10,8000,253,582 +E,7498,10,8000,253,588 +E,7499,10,8000,253,588 +# step 11/13 rpm=8000 period_us=20 ints=200 count=7500 +D,step_11,2552391530,144,226,161,95,213 +H,step_11,137807,22726,0 +E,7500,11,9000,253,902 +E,7501,11,9000,253,588 +E,7502,11,9000,253,582 +E,7503,11,9000,253,582 +E,7504,11,9000,253,582 +E,7505,11,9000,253,582 +E,7506,11,9000,253,588 +E,7507,11,9000,253,582 +E,7508,11,9000,253,582 +E,7509,11,9000,253,582 +E,7510,11,9000,253,582 +E,7511,11,9000,253,588 +E,7512,11,9000,253,582 +E,7513,11,9000,253,582 +E,7514,11,9000,253,582 +E,7515,11,9000,253,582 +E,7516,11,9000,253,588 +E,7517,11,9000,253,582 +E,7518,11,9000,253,582 +E,7519,11,9000,253,582 +E,7520,11,9000,253,582 +E,7521,11,9000,253,588 +E,7522,11,9000,253,582 +E,7523,11,9000,253,582 +E,7524,11,9000,253,582 +E,7525,11,9000,253,582 +E,7526,11,9000,253,588 +E,7527,11,9000,253,582 +E,7528,11,9000,253,582 +E,7529,11,9000,253,582 +E,7530,11,9000,253,582 +E,7531,11,9000,253,588 +E,7532,11,9000,253,582 +E,7533,11,9000,253,582 +E,7534,11,9000,253,582 +E,7535,11,9000,253,582 +E,7536,11,9000,253,588 +E,7537,11,9000,253,582 +E,7538,11,9000,253,582 +E,7539,11,9000,253,582 +E,7540,11,9000,253,582 +E,7541,11,9000,253,588 +E,7542,11,9000,253,582 +E,7543,11,9000,253,582 +E,7544,11,9000,253,582 +E,7545,11,9000,253,582 +E,7546,11,9000,253,588 +E,7547,11,9000,253,582 +E,7548,11,9000,253,582 +E,7549,11,9000,253,582 +E,7550,11,9000,253,582 +E,7551,11,9000,253,588 +E,7552,11,9000,253,582 +E,7553,11,9000,253,582 +E,7554,11,9000,253,582 +E,7555,11,9000,253,582 +E,7556,11,9000,253,588 +E,7557,11,9000,253,582 +E,7558,11,9000,253,582 +E,7559,11,9000,253,582 +E,7560,11,9000,253,582 +E,7561,11,9000,253,588 +E,7562,11,9000,253,582 +E,7563,11,9000,253,582 +E,7564,11,9000,253,582 +E,7565,11,9000,253,582 +E,7566,11,9000,253,588 +E,7567,11,9000,253,582 +E,7568,11,9000,253,582 +E,7569,11,9000,253,582 +E,7570,11,9000,253,582 +E,7571,11,9000,253,588 +E,7572,11,9000,253,582 +E,7573,11,9000,253,582 +E,7574,11,9000,253,582 +E,7575,11,9000,253,582 +E,7576,11,9000,253,588 +E,7577,11,9000,253,582 +E,7578,11,9000,253,582 +E,7579,11,9000,253,582 +E,7580,11,9000,253,582 +E,7581,11,9000,253,588 +E,7582,11,9000,253,582 +E,7583,11,9000,253,582 +E,7584,11,9000,253,582 +E,7585,11,9000,253,582 +E,7586,11,9000,253,588 +E,7587,11,9000,253,582 +E,7588,11,9000,253,582 +E,7589,11,9000,253,582 +E,7590,11,9000,253,582 +E,7591,11,9000,253,588 +E,7592,11,9000,253,582 +E,7593,11,9000,253,582 +E,7594,11,9000,253,582 +E,7595,11,9000,253,582 +E,7596,11,9000,253,588 +E,7597,11,9000,253,582 +E,7598,11,9000,253,582 +E,7599,11,9000,253,582 +E,7600,11,9000,253,582 +E,7601,11,9000,253,588 +E,7602,11,9000,253,582 +E,7603,11,9000,253,582 +E,7604,11,9000,253,582 +E,7605,11,9000,253,582 +E,7606,11,9000,253,588 +E,7607,11,9000,253,582 +E,7608,11,9000,253,582 +E,7609,11,9000,253,582 +E,7610,11,9000,253,582 +E,7611,11,9000,253,588 +E,7612,11,9000,253,582 +E,7613,11,9000,253,582 +E,7614,11,9000,253,582 +E,7615,11,9000,253,582 +E,7616,11,9000,253,588 +E,7617,11,9000,253,582 +E,7618,11,9000,253,582 +E,7619,11,9000,253,582 +E,7620,11,9000,253,582 +E,7621,11,9000,253,588 +E,7622,11,9000,253,582 +E,7623,11,9000,253,582 +E,7624,11,9000,253,582 +E,7625,11,9000,253,582 +E,7626,11,9000,253,588 +E,7627,11,9000,253,582 +E,7628,11,9000,253,582 +E,7629,11,9000,253,582 +E,7630,11,9000,253,582 +E,7631,11,9000,253,588 +E,7632,11,9000,253,582 +E,7633,11,9000,253,582 +E,7634,11,9000,253,582 +E,7635,11,9000,253,582 +E,7636,11,9000,253,588 +E,7637,11,9000,253,582 +E,7638,11,9000,253,582 +E,7639,11,9000,253,582 +E,7640,11,9000,253,582 +E,7641,11,9000,253,588 +E,7642,11,9000,253,582 +E,7643,11,9000,253,582 +E,7644,11,9000,253,582 +E,7645,11,9000,253,582 +E,7646,11,9000,253,588 +E,7647,11,9000,253,582 +E,7648,11,9000,253,582 +E,7649,11,9000,25# step 12/13 rpm=9000 period_us=18 ints=150 count=7649 +D,step_12,2607228370,190,44,161,27,121 +H,step_12,116486,22418,0 +3,582 +E,7650,12,10000,253,582 +E,7651,12,10000,253,588 +E,7652,12,10000,253,588 +E,7653,12,10000,253,588 +E,7654,12,10000,253,588 +E,7655,12,10000,253,582 +E,7656,12,10000,253,582 +E,7657,12,10000,253,588 +E,7658,12,10000,253,588 +E,7659,12,10000,253,582 +E,7660,12,10000,253,582 +E,7661,12,10000,253,588 +E,7662,12,10000,253,588 +E,7663,12,10000,253,582 +E,7664,12,10000,253,582 +E,7665,12,10000,253,588 +E,7666,12,10000,253,588 +E,7667,12,10000,253,582 +E,7668,12,10000,253,582 +E,7669,12,10000,253,588 +E,7670,12,10000,253,588 +E,7671,12,10000,253,582 +E,7672,12,10000,253,588 +E,7673,12,10000,253,588 +E,7674,12,10000,253,582 +E,7675,12,10000,253,582 +E,7676,12,10000,253,588 +E,7677,12,10000,253,582 +E,7678,12,10000,253,582 +E,7679,12,10000,253,588 +E,7680,12,10000,253,582 +E,7681,12,10000,253,582 +E,7682,12,10000,253,588 +E,7683,12,10000,253,588 +E,7684,12,10000,253,582 +E,7685,12,10000,253,588 +E,7686,12,10000,253,588 +E,7687,12,10000,253,582 +E,7688,12,10000,253,582 +E,7689,12,10000,253,588 +E,7690,12,10000,253,582 +E,7691,12,10000,253,582 +E,7692,12,10000,253,588 +E,7693,12,10000,253,582 +E,7694,12,10000,253,582 +E,7695,12,10000,253,588 +E,7696,12,10000,253,588 +E,7697,12,10000,253,582 +E,7698,12,10000,253,582 +E,7699,12,10000,253,588 +E,7700,12,10000,253,588 +E,7701,12,10000,253,582 +E,7702,12,10000,253,588 +E,7703,12,10000,253,588 +E,7704,12,10000,253,582 +E,7705,12,10000,253,582 +E,7706,12,10000,253,588 +E,7707,12,10000,253,582 +E,7708,12,10000,253,582 +E,7709,12,10000,253,588 +E,7710,12,10000,253,582 +E,7711,12,10000,253,582 +E,7712,12,10000,253,588 +E,7713,12,10000,253,588 +E,7714,12,10000,253,582 +E,7715,12,10000,253,582 +E,7716,12,10000,253,588 +E,7717,12,10000,253,588 +E,7718,12,10000,253,582 +E,7719,12,10000,253,588 +E,7720,12,10000,253,588 +E,7721,12,10000,253,582 +E,7722,12,10000,253,582 +E,7723,12,10000,253,588 +E,7724,12,10000,253,582 +E,7725,12,10000,253,582 +E,7726,12,10000,253,588 +E,7727,12,10000,253,582 +E,7728,12,10000,253,582 +E,7729,12,10000,253,588 +E,7730,12,10000,253,588 +E,7731,12,10000,253,582 +E,7732,12,10000,253,582 +E,7733,12,10000,253,588 +E,7734,12,10000,253,588 +E,7735,12,10000,253,582 +E,7736,12,10000,253,588 +E,7737,12,10000,253,588 +E,7738,12,10000,253,582 +E,7739,12,10000,253,582 +E,7740,12,10000,253,588 +E,7741,12,10000,253,582 +E,7742,12,10000,253,582 +E,7743,12,10000,253,588 +E,7744,12,10000,253,582 +E,7745,12,10000,253,582 +E,7746,12,10000,253,588 +E,7747,12,10000,253,588 +E,7748,12,10000,253,582 +E,7749,12,# step 13/13 rpm=10000 period_us=16 ints=100 count=7749 +D,step_13,2645817802,240,143,161,156,228 +H,step_13,91861,23257,0 +10000,253,588 +D,end,2647027500,4,55,161,205,180 +H,end,9280,28118,0 +drops,0 +samples,7750 +=== END === diff --git a/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-b48a81ac-baseline-noadc-systick/events.csv b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-b48a81ac-baseline-noadc-systick/events.csv new file mode 100644 index 00000000..6413a257 --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-b48a81ac-baseline-noadc-systick/events.csv @@ -0,0 +1,7343 @@ +Rsilicon-2026-05-10,baseline,E,446,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,447,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,448,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,449,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,450,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,451,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,452,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,453,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,454,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,455,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,456,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,457,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,458,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,459,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,460,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,461,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,462,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,463,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,464,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,465,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,466,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,467,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,468,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,469,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,470,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,471,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,472,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,473,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,474,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,475,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,476,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,477,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,478,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,479,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,480,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,481,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,482,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,483,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,484,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,485,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,486,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,487,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,488,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,489,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,490,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,491,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,492,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,493,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,494,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,495,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,496,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,497,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,498,0,500,268,528 +Rsilicon-2026-05-10,baseline,E,49# step 1/13 rpm=500 period_us=333 ints=500 count=499 +Rsilicon-2026-05-10,baseline,D,step_1,160089125,220,248,57,107,238 +Rsilicon-2026-05-10,baseline,H,step_1,0,0,0 +Rsilicon-2026-05-10,baseline,E,500,1,1000,268,528 +Rsilicon-2026-05-10,baseline,E,501,1,1000,268,528 +Rsilicon-2026-05-10,baseline,E,502,1,1000,268,528 +Rsilicon-2026-05-10,baseline,E,503,1,1000,268,528 +Rsilicon-2026-05-10,baseline,E,504,1,1000,268,528 +Rsilicon-2026-05-10,baseline,E,505,1,1000,268,528 +Rsilicon-2026-05-10,baseline,E,506,1,1000,268,528 +Rsilicon-2026-05-10,baseline,E,507,1,1000,268,528 +Rsilicon-2026-05-10,baseline,E,508,1,1000,268,528 +Rsilicon-2026-05-10,baseline,E,509,1,1000,268,528 +Rsilicon-2026-05-10,baseline,E,510,1,1000,268,528 +Rsilicon-2026-05-10,baseline,E,511,1,1000,268,528 +Rsilicon-2026-05-10,baseline,E,512,1,1000,268,528 +Rsilicon-2026-05-10,baseline,E,513,1,1000,268,528 +Rsilicon-2026-05-10,baseline,E,514,1,1000,268,528 +Rsilicon-2026-05-10,baseline,E,515,1,1000,268,528 +Rsilicon-2026-05-10,baseline,E,516,1,1000,268,528 +Rsilicon-2026-05-10,baseline,E,517,1,1000,268,528 +Rsilicon-2026-05-10,baseline,E,518,1,1000,268,528 +Rsilicon-2026-05-10,baseline,E,519,1,1000,268,528 +Rsilicon-2026-05-10,baseline,E,520,1,1000,268,528 +Rsilicon-2026-05-10,baseline,E,521,1,1000,268,528 +Rsilicon-2026-05-10,baseline,E,522,1,1000,268,528 +Rsilicon-2026-05-10,baseline,E,523,1,1000,268,528 +Rsilicon-2026-05-10,baseline,E,524,1,1000,268,528 +Rsilicon-2026-05-10,baseline,E,525,1,1000,268,528 +Rsilicon-2026-05-10,baseline,E,526,1,1000,268,528 +Rsilicon-2026-05-10,baseline,E,527,1,1000,268,528 +Rsilicon-2026-05-10,baseline,E,528,1,1000,268,528 +Rsilicon-2026-05-10,baseline,E,529,1,1000,268,528 +Rsilicon-2026-05-10,baseline,E,530,1,1000,268,528 +Rsilicon-2026-05-10,baseline,E,531,1,1000,268,528 +Rsilicon-2026-05-10,baseline,E,532,1,1000,268,528 +Rsilicon-2026-05-10,baseline,E,533,1,1000,268,528 +Rsilicon-2026-05-10,baseline,E,534,1,1000,268,528 +Rsilicon-2026-05-10,baseline,E,535,1,1000,268,528 +Rsilicon-2026-05-10,baseline,E,536,1,1000,268,528 +Rsilicon-2026-05-10,baseline,E,537,1,1000,268,528 +Rsilicon-2026-05-10,baseline,E,538,1,1000,268,528 +Rsilicon-2026-05-10,baseline,E,539,1,1000,268,528 +Rsilicon-2026-05-10,baseline,E,540,1,1000,268,528 +Rsilicon-2026-05-10,baseline,E,541,1,1000,268,528 +Rsilicon-2026-05-10,baseline,E,542,1,1000,268,528 +Rsilicon-2026-05-10,baseline,E,543,1,1000,268,528 +Rsilicon-2026-05-10,baseline,E,544,1,1000,268,528 +Rsilicon-2026-05-10,baseline,E,545,1,1000,268,528 +Rsilicon-2026-05-10,baseline,E,546,1,1000,268,528 +Rsilicon-2026-05-10,baseline,E,547,1,1000,268,528 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+Rsilicon-2026-05-10,baseline,E,1476,2,1500,268,528 +Rsilicon-2026-05-10,baseline,E,1477,2,1500,268,528 +Rsilicon-2026-05-10,baseline,E,1478,2,1500,268,528 +Rsilicon-2026-05-10,baseline,E,1479,2,1500,268,528 +Rsilicon-2026-05-10,baseline,E,1480,2,1500,268,528 +Rsilicon-2026-05-10,baseline,E,1481,2,1500,268,528 +Rsilicon-2026-05-10,baseline,E,1482,2,1500,268,528 +Rsilicon-2026-05-10,baseline,E,1483,2,1500,268,528 +Rsilicon-2026-05-10,baseline,E,1484,2,1500,268,528 +Rsilicon-2026-05-10,baseline,E,1485,2,1500,268,528 +Rsilicon-2026-05-10,baseline,E,1486,2,1500,268,528 +Rsilicon-2026-05-10,baseline,E,1487,2,1500,268,528 +Rsilicon-2026-05-10,baseline,E,1488,2,1500,268,528 +Rsilicon-2026-05-10,baseline,E,1489,2,1500,268,528 +Rsilicon-2026-05-10,baseline,E,1490,2,1500,268,528 +Rsilicon-2026-05-10,baseline,E,1491,2,1500,268,528 +Rsilicon-2026-05-10,baseline,E,1492,2,1500,268,528 +Rsilicon-2026-05-10,baseline,E,1493,2,1500,268,528 +Rsilicon-2026-05-10,baseline,E,1494,2,1500,268,528 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+Rsilicon-2026-05-10,baseline,E,2460,3,2000,268,528 +Rsilicon-2026-05-10,baseline,E,2461,3,2000,268,528 +Rsilicon-2026-05-10,baseline,E,2462,3,2000,268,528 +Rsilicon-2026-05-10,baseline,E,2463,3,2000,268,528 +Rsilicon-2026-05-10,baseline,E,2464,3,2000,268,528 +Rsilicon-2026-05-10,baseline,E,2465,3,2000,268,528 +Rsilicon-2026-05-10,baseline,E,2466,3,2000,268,528 +Rsilicon-2026-05-10,baseline,E,2467,3,2000,268,528 +Rsilicon-2026-05-10,baseline,E,2468,3,2000,268,528 +Rsilicon-2026-05-10,baseline,E,2469,3,2000,268,528 +Rsilicon-2026-05-10,baseline,E,2470,3,2000,268,528 +Rsilicon-2026-05-10,baseline,E,2471,3,2000,268,528 +Rsilicon-2026-05-10,baseline,E,2472,3,2000,268,528 +Rsilicon-2026-05-10,baseline,E,2473,3,2000,268,528 +Rsilicon-2026-05-10,baseline,E,2474,3,2000,268,528 +Rsilicon-2026-05-10,baseline,E,2475,3,2000,268,528 +Rsilicon-2026-05-10,baseline,E,2476,3,2000,268,528 +Rsilicon-2026-05-10,baseline,E,2477,3,2000,268,528 +Rsilicon-2026-05-10,baseline,E,2478,3,2000,268,528 +Rsilicon-2026-05-10,baseline,E,2479,3,2000,268,528 +Rsilicon-2026-05-10,baseline,E,2480,3,2000,268,528 +Rsilicon-2026-05-10,baseline,E,2481,3,2000,268,528 +Rsilicon-2026-05-10,baseline,E,2482,3,2000,268,528 +Rsilicon-2026-05-10,baseline,E,2483,3,2000,268,528 +Rsilicon-2026-05-10,baseline,E,2484,3,2000,268,528 +Rsilicon-2026-05-10,baseline,E,2485,3,2000,268,528 +Rsilicon-2026-05-10,baseline,E,2486,3,2000,268,528 +Rsilicon-2026-05-10,baseline,E,2487,3,2000,268,528 +Rsilicon-2026-05-10,baseline,E,2488,3,2000,268,528 +Rsilicon-2026-05-10,baseline,E,2489,3,2000,268,528 +Rsilicon-2026-05-10,baseline,E,2490,3,2000,268,528 +Rsilicon-2026-05-10,baseline,E,2491,3,2000,268,528 +Rsilicon-2026-05-10,baseline,E,2492,3,2000,268,528 +Rsilicon-2026-05-10,baseline,E,2493,3,2000,268,528 +Rsilicon-2026-05-10,baseline,E,2494,3,2000,268,528 +Rsilicon-2026-05-10,baseline,E,2495,3,2000,268,528 +Rsilicon-2026-05-10,baseline,E,2496,3,2000,268,528 +Rsilicon-2026-05-10,baseline,E,2497,3,2000,268,528 +Rsilicon-2026-05-10,baseline,E,2498,3,2000,268,528 +Rsilicon-2026-05-10,baseline,E,2499,3,2000,268,528 +# Rsilicon-2026-05-10 baseline: step 4/13 rpm=2000 period_us=83 ints=1000 count=2500 +Rsilicon-2026-05-10,baseline,D,step_4,837264887,127,46,229,5,51 +Rsilicon-2026-05-10,baseline,H,step_4,0,0,0 +Rsilicon-2026-05-10,baseline,E,2500,4,2500,268,1302 +Rsilicon-2026-05-10,baseline,E,2501,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2502,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2503,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2504,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2505,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2506,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2507,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2508,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2509,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2510,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2511,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2512,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2513,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2514,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2515,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2516,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2517,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2518,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2519,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2520,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2521,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2522,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2523,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2524,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2525,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2526,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2527,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2528,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2529,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2530,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2531,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2532,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2533,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2534,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2535,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2536,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2537,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2538,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2539,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2540,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2541,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2542,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2543,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2544,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2545,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2546,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2547,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2548,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2549,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2550,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2551,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2552,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2553,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2554,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2555,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2556,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2557,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2558,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2559,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2560,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2561,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2562,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2563,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2564,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2565,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2566,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2567,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2568,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2569,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2570,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2571,4,2500,268,531 +Rsilicon-2026-05-10,baseline,E,2572,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2573,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2574,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2575,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2576,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2577,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2578,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2579,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2580,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2581,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2582,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2583,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2584,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2585,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2586,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2587,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2588,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2589,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2590,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2591,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2592,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2593,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2594,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2595,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2596,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2597,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2598,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2599,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2600,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2601,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2602,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2603,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2604,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2605,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2606,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2607,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2608,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2609,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2610,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2611,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2612,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2613,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2614,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2615,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2616,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2617,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2618,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2619,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2620,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2621,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2622,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2623,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2624,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2625,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2626,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2627,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2628,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2629,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2630,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2631,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2632,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2633,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2634,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2635,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2636,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2637,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2638,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2639,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2640,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2641,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2642,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2643,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2644,4,2500,268,528 +Rsilicon-2026-05-10,baseline,E,2645,4,2500,268,528 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ints=1000 count=3500 +Rsilicon-2026-05-10,baseline,D,step_5,1178441760,150,209,33,37,89 +Rsilicon-2026-05-10,baseline,H,step_5,0,0,0 +Rsilicon-2026-05-10,baseline,E,3500,5,3000,268,1302 +Rsilicon-2026-05-10,baseline,E,3501,5,3000,268,528 +Rsilicon-2026-05-10,baseline,E,3502,5,3000,268,528 +Rsilicon-2026-05-10,baseline,E,3503,5,3000,268,528 +Rsilicon-2026-05-10,baseline,E,3504,5,3000,268,528 +Rsilicon-2026-05-10,baseline,E,3505,5,3000,268,528 +Rsilicon-2026-05-10,baseline,E,3506,5,3000,268,528 +Rsilicon-2026-05-10,baseline,E,3507,5,3000,268,528 +Rsilicon-2026-05-10,baseline,E,3508,5,3000,268,528 +Rsilicon-2026-05-10,baseline,E,3509,5,3000,268,528 +Rsilicon-2026-05-10,baseline,E,3510,5,3000,268,528 +Rsilicon-2026-05-10,baseline,E,3511,5,3000,268,528 +Rsilicon-2026-05-10,baseline,E,3512,5,3000,268,528 +Rsilicon-2026-05-10,baseline,E,3513,5,3000,268,528 +Rsilicon-2026-05-10,baseline,E,3514,5,3000,268,528 +Rsilicon-2026-05-10,baseline,E,3515,5,3000,268,528 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+Rsilicon-2026-05-10,baseline,E,4485,5,3000,268,528 +Rsilicon-2026-05-10,baseline,E,4486,5,3000,268,528 +Rsilicon-2026-05-10,baseline,E,4487,5,3000,268,528 +Rsilicon-2026-05-10,baseline,E,4488,5,3000,268,528 +Rsilicon-2026-05-10,baseline,E,4489,5,3000,268,528 +Rsilicon-2026-05-10,baseline,E,4490,5,3000,268,528 +Rsilicon-2026-05-10,baseline,E,4491,5,3000,268,528 +Rsilicon-2026-05-10,baseline,E,4492,5,3000,268,528 +Rsilicon-2026-05-10,baseline,E,4493,5,3000,268,528 +Rsilicon-2026-05-10,baseline,E,4494,5,3000,268,528 +Rsilicon-2026-05-10,baseline,E,4495,5,3000,268,528 +Rsilicon-2026-05-10,baseline,E,4496,5,3000,268,528 +Rsilicon-2026-05-10,baseline,E,4497,5,3000,268,528 +Rsilicon-2026-05-10,baseline,E,4498,5,3000,268,528 +Rsilicon-2026-05-10,baseline,E,4499,5,3000,268,528 +# Rsilicon-2026-05-10 baseline: step 6/13 rpm=3000 period_us=55 ints=1000 count=4500 +Rsilicon-2026-05-10,baseline,D,step_6,1519646220,20,168,208,143,195 +Rsilicon-2026-05-10,baseline,H,step_6,0,0,0 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+Rsilicon-2026-05-10,baseline,E,5488,6,4000,268,528 +Rsilicon-2026-05-10,baseline,E,5489,6,4000,268,528 +Rsilicon-2026-05-10,baseline,E,5490,6,4000,268,528 +Rsilicon-2026-05-10,baseline,E,5491,6,4000,268,528 +Rsilicon-2026-05-10,baseline,E,5492,6,4000,268,528 +Rsilicon-2026-05-10,baseline,E,5493,6,4000,268,528 +Rsilicon-2026-05-10,baseline,E,5494,6,4000,268,528 +Rsilicon-2026-05-10,baseline,E,5495,6,4000,268,528 +Rsilicon-2026-05-10,baseline,E,5496,6,4000,268,528 +Rsilicon-2026-05-10,baseline,E,5497,6,4000,268,528 +Rsilicon-2026-05-10,baseline,E,5498,6,4000,268,528 +Rsilicon-2026-05-10,baseline,E,5499,6,4000,268,528 +# Rsilicon-2026-05-10 baseline: step 7/13 rpm=4000 period_us=41 ints=1000 count=5500 +Rsilicon-2026-05-10,baseline,D,step_7,1860883872,202,59,207,41,221 +Rsilicon-2026-05-10,baseline,H,step_7,0,0,0 +Rsilicon-2026-05-10,baseline,E,5500,7,5000,268,1302 +Rsilicon-2026-05-10,baseline,E,5501,7,5000,268,528 +Rsilicon-2026-05-10,baseline,E,5502,7,5000,268,528 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+Rsilicon-2026-05-10,baseline,E,6491,7,5000,268,528 +Rsilicon-2026-05-10,baseline,E,6492,7,5000,268,528 +Rsilicon-2026-05-10,baseline,E,6493,7,5000,268,528 +Rsilicon-2026-05-10,baseline,E,6494,7,5000,268,528 +Rsilicon-2026-05-10,baseline,E,6495,7,5000,268,528 +Rsilicon-2026-05-10,baseline,E,6496,7,5000,268,528 +Rsilicon-2026-05-10,baseline,E,6497,7,5000,268,528 +Rsilicon-2026-05-10,baseline,E,6498,7,5000,268,528 +Rsilicon-2026-05-10,baseline,E,6499,7,5000,268,528 +# Rsilicon-2026-05-10 baseline: step 8/13 rpm=5000 period_us=33 ints=1000 count=6500 +Rsilicon-2026-05-10,baseline,D,step_8,2202095921,89,72,87,31,199 +Rsilicon-2026-05-10,baseline,H,step_8,0,0,0 +Rsilicon-2026-05-10,baseline,E,6500,8,6000,268,1302 +Rsilicon-2026-05-10,baseline,E,6501,8,6000,268,528 +Rsilicon-2026-05-10,baseline,E,6502,8,6000,268,528 +Rsilicon-2026-05-10,baseline,E,6503,8,6000,268,528 +Rsilicon-2026-05-10,baseline,E,6504,8,6000,268,528 +Rsilicon-2026-05-10,baseline,E,6505,8,6000,268,528 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+Rsilicon-2026-05-10,baseline,E,7477,10,8000,268,531 +Rsilicon-2026-05-10,baseline,E,7478,10,8000,268,531 +Rsilicon-2026-05-10,baseline,E,7479,10,8000,268,528 +Rsilicon-2026-05-10,baseline,E,7480,10,8000,268,528 +Rsilicon-2026-05-10,baseline,E,7481,10,8000,268,531 +Rsilicon-2026-05-10,baseline,E,7482,10,8000,268,531 +Rsilicon-2026-05-10,baseline,E,7483,10,8000,268,528 +Rsilicon-2026-05-10,baseline,E,7484,10,8000,268,528 +Rsilicon-2026-05-10,baseline,E,7485,10,8000,268,531 +Rsilicon-2026-05-10,baseline,E,7486,10,8000,268,531 +Rsilicon-2026-05-10,baseline,E,7487,10,8000,268,528 +Rsilicon-2026-05-10,baseline,E,7488,10,8000,268,528 +Rsilicon-2026-05-10,baseline,E,7489,10,8000,268,531 +Rsilicon-2026-05-10,baseline,E,7490,10,8000,268,531 +Rsilicon-2026-05-10,baseline,E,7491,10,8000,268,528 +Rsilicon-2026-05-10,baseline,E,7492,10,8000,268,528 +Rsilicon-2026-05-10,baseline,E,7493,10,8000,268,531 +Rsilicon-2026-05-10,baseline,E,7494,10,8000,268,531 +Rsilicon-2026-05-10,baseline,E,7495,10,8000,268,528 +Rsilicon-2026-05-10,baseline,E,7496,10,8000,268,528 +Rsilicon-2026-05-10,baseline,E,7497,10,8000,268,531 +Rsilicon-2026-05-10,baseline,E,7498,10,8000,268,531 +Rsilicon-2026-05-10,baseline,E,7499,10,8000,268,528 +# Rsilicon-2026-05-10 baseline: step 11/13 rpm=8000 period_us=20 ints=200 count=7500 +Rsilicon-2026-05-10,baseline,D,step_11,2549929071,26,31,140,205,123 +Rsilicon-2026-05-10,baseline,H,step_11,0,0,0 +Rsilicon-2026-05-10,baseline,E,7500,11,9000,268,1302 +Rsilicon-2026-05-10,baseline,E,7501,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7502,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7503,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7504,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7505,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7506,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7507,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7508,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7509,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7510,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7511,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7512,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7513,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7514,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7515,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7516,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7517,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7518,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7519,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7520,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7521,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7522,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7523,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7524,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7525,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7526,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7527,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7528,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7529,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7530,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7531,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7532,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7533,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7534,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7535,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7536,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7537,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7538,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7539,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7540,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7541,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7542,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7543,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7544,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7545,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7546,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7547,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7548,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7549,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7550,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7551,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7552,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7553,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7554,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7555,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7556,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7557,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7558,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7559,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7560,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7561,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7562,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7563,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7564,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7565,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7566,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7567,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7568,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7569,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7570,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7571,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7572,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7573,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7574,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7575,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7576,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7577,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7578,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7579,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7580,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7581,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7582,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7583,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7584,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7585,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7586,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7587,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7588,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7589,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7590,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7591,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7592,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7593,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7594,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7595,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7596,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7597,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7598,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7599,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7600,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7601,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7602,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7603,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7604,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7605,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7606,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7607,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7608,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7609,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7610,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7611,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7612,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7613,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7614,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7615,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7616,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7617,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7618,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7619,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7620,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7621,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7622,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7623,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7624,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7625,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7626,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7627,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7628,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7629,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7630,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7631,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7632,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7633,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7634,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7635,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7636,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7637,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7638,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7639,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7640,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7641,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7642,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7643,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7644,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7645,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7646,11,9000,268,528 +Rsilicon-2026-05-10,baseline,E,7647,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7648,11,9000,268,531 +Rsilicon-2026-05-10,baseline,E,7649,11,9000,2# step 12/13 rpm=9000 period_us=18 ints=150 count=7649 +Rsilicon-2026-05-10,baseline,D,step_12,2604618337,42,117,207,231,161 +Rsilicon-2026-05-10,baseline,H,step_12,0,0,0 +Rsilicon-2026-05-10,baseline,E,7650,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7651,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7652,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7653,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7654,12,10000,268,531 +Rsilicon-2026-05-10,baseline,E,7655,12,10000,268,531 +Rsilicon-2026-05-10,baseline,E,7656,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7657,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7658,12,10000,268,531 +Rsilicon-2026-05-10,baseline,E,7659,12,10000,268,531 +Rsilicon-2026-05-10,baseline,E,7660,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7661,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7662,12,10000,268,531 +Rsilicon-2026-05-10,baseline,E,7663,12,10000,268,531 +Rsilicon-2026-05-10,baseline,E,7664,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7665,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7666,12,10000,268,531 +Rsilicon-2026-05-10,baseline,E,7667,12,10000,268,531 +Rsilicon-2026-05-10,baseline,E,7668,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7669,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7670,12,10000,268,531 +Rsilicon-2026-05-10,baseline,E,7671,12,10000,268,531 +Rsilicon-2026-05-10,baseline,E,7672,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7673,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7674,12,10000,268,531 +Rsilicon-2026-05-10,baseline,E,7675,12,10000,268,531 +Rsilicon-2026-05-10,baseline,E,7676,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7677,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7678,12,10000,268,531 +Rsilicon-2026-05-10,baseline,E,7679,12,10000,268,531 +Rsilicon-2026-05-10,baseline,E,7680,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7681,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7682,12,10000,268,531 +Rsilicon-2026-05-10,baseline,E,7683,12,10000,268,531 +Rsilicon-2026-05-10,baseline,E,7684,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7685,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7686,12,10000,268,531 +Rsilicon-2026-05-10,baseline,E,7687,12,10000,268,531 +Rsilicon-2026-05-10,baseline,E,7688,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7689,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7690,12,10000,268,531 +Rsilicon-2026-05-10,baseline,E,7691,12,10000,268,531 +Rsilicon-2026-05-10,baseline,E,7692,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7693,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7694,12,10000,268,531 +Rsilicon-2026-05-10,baseline,E,7695,12,10000,268,531 +Rsilicon-2026-05-10,baseline,E,7696,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7697,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7698,12,10000,268,531 +Rsilicon-2026-05-10,baseline,E,7699,12,10000,268,531 +Rsilicon-2026-05-10,baseline,E,7700,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7701,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7702,12,10000,268,531 +Rsilicon-2026-05-10,baseline,E,7703,12,10000,268,531 +Rsilicon-2026-05-10,baseline,E,7704,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7705,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7706,12,10000,268,531 +Rsilicon-2026-05-10,baseline,E,7707,12,10000,268,531 +Rsilicon-2026-05-10,baseline,E,7708,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7709,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7710,12,10000,268,531 +Rsilicon-2026-05-10,baseline,E,7711,12,10000,268,531 +Rsilicon-2026-05-10,baseline,E,7712,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7713,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7714,12,10000,268,531 +Rsilicon-2026-05-10,baseline,E,7715,12,10000,268,531 +Rsilicon-2026-05-10,baseline,E,7716,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7717,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7718,12,10000,268,531 +Rsilicon-2026-05-10,baseline,E,7719,12,10000,268,531 +Rsilicon-2026-05-10,baseline,E,7720,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7721,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7722,12,10000,268,531 +Rsilicon-2026-05-10,baseline,E,7723,12,10000,268,531 +Rsilicon-2026-05-10,baseline,E,7724,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7725,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7726,12,10000,268,531 +Rsilicon-2026-05-10,baseline,E,7727,12,10000,268,531 +Rsilicon-2026-05-10,baseline,E,7728,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7729,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7730,12,10000,268,531 +Rsilicon-2026-05-10,baseline,E,7731,12,10000,268,531 +Rsilicon-2026-05-10,baseline,E,7732,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7733,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7734,12,10000,268,531 +Rsilicon-2026-05-10,baseline,E,7735,12,10000,268,531 +Rsilicon-2026-05-10,baseline,E,7736,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7737,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7738,12,10000,268,531 +Rsilicon-2026-05-10,baseline,E,7739,12,10000,268,531 +Rsilicon-2026-05-10,baseline,E,7740,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7741,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7742,12,10000,268,531 +Rsilicon-2026-05-10,baseline,E,7743,12,10000,268,531 +Rsilicon-2026-05-10,baseline,E,7744,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7745,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7746,12,10000,268,531 +Rsilicon-2026-05-10,baseline,E,7747,12,10000,268,531 +Rsilicon-2026-05-10,baseline,E,7748,12,10000,268,528 +Rsilicon-2026-05-10,baseline,E,7749,12# step 13/13 rpm=10000 period_us=16 ints=100 count=7749 +Rsilicon-2026-05-10,baseline,D,step_13,2643089715,40,232,207,254,204 +Rsilicon-2026-05-10,baseline,H,step_13,0,0,0 +Rsilicon-2026-05-10,baseline,D,end,2644181325,11,2,207,238,48 +Rsilicon-2026-05-10,baseline,H,end,0,0,0 +M,Rsilicon-2026-05-10,baseline,drops,0 +M,Rsilicon-2026-05-10,baseline,samples,7750 +M,Rsilicon-2026-05-10,baseline,END diff --git a/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-b48a81ac-baseline-noadc-systick/firmware.elf b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-b48a81ac-baseline-noadc-systick/firmware.elf new file mode 100755 index 00000000..7451114f Binary files /dev/null and b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-b48a81ac-baseline-noadc-systick/firmware.elf differ diff --git a/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-b48a81ac-baseline-noadc-systick/firmware.elf.sha256 b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-b48a81ac-baseline-noadc-systick/firmware.elf.sha256 new file mode 100644 index 00000000..da61f27f --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-b48a81ac-baseline-noadc-systick/firmware.elf.sha256 @@ -0,0 +1 @@ +bb22aa55cf352ba5a4b8cc46b4cd7f07e7123433f8e2b18b2bda090e3788ebde firmware.elf diff --git a/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-b48a81ac-baseline-noadc-systick/manifest.txt b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-b48a81ac-baseline-noadc-systick/manifest.txt new file mode 100644 index 00000000..18b6e809 --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-b48a81ac-baseline-noadc-systick/manifest.txt @@ -0,0 +1,23 @@ +# Silicon-anchor manifest +# Produced by manual flash/capture pipeline (LTO + control experiments) +captured_at: 2026-05-10T11:22:21Z +board: nucleo_g474re +variant: baseline +adc_enabled: false +dt_overrides: adc1=disabled +tick_source: systick +sweep: long +flash_runner: openocd +gale_sha: b48a81ac69cbcb6c50495d31b603d910f73a85d5 +gale_status: clean +host: Darwin 25.3.0 arm64 +rustc: rustc 1.94.1 (e408947bf 2026-03-25) +zephyr_base: /Volumes/Home/git/pulseengine/zephyr +zephyr_sha: fc4d89c118fc1d0ff0ad31906a4fa4bd252c9ced +sdk_dir: /Volumes/Home/zephyr-sdk/zephyr-sdk-1.0.1 +elf_sha256: bb22aa55cf352ba5a4b8cc46b4cd7f07e7123433f8e2b18b2bda090e3788ebde +csv_sha256: 66892193fe7887b37fe0128775bc024d5f90a8e771970e28d759816b04e84339 +csv_bytes: 169497 +csv_event_lines: 7304 +serial_port: /dev/cu.usbmodem132203 +capture_timeout_s: 1800 diff --git a/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-b48a81ac-baseline-noadc-systick/output.csv b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-b48a81ac-baseline-noadc-systick/output.csv new file mode 100644 index 00000000..fed39241 --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-b48a81ac-baseline-noadc-systick/output.csv @@ -0,0 +1,7349 @@ +b���b���b��� +E,446,0,500,268,528 +E,447,0,500,268,528 +E,448,0,500,268,528 +E,449,0,500,268,528 +E,450,0,500,268,528 +E,451,0,500,268,528 +E,452,0,500,268,528 +E,453,0,500,268,528 +E,454,0,500,268,528 +E,455,0,500,268,528 +E,456,0,500,268,528 +E,457,0,500,268,528 +E,458,0,500,268,528 +E,459,0,500,268,528 +E,460,0,500,268,528 +E,461,0,500,268,528 +E,462,0,500,268,528 +E,463,0,500,268,528 +E,464,0,500,268,528 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+E,7403,10,8000,268,528 +E,7404,10,8000,268,531 +E,7405,10,8000,268,531 +E,7406,10,8000,268,531 +E,7407,10,8000,268,528 +E,7408,10,8000,268,528 +E,7409,10,8000,268,531 +E,7410,10,8000,268,531 +E,7411,10,8000,268,528 +E,7412,10,8000,268,528 +E,7413,10,8000,268,531 +E,7414,10,8000,268,531 +E,7415,10,8000,268,528 +E,7416,10,8000,268,528 +E,7417,10,8000,268,531 +E,7418,10,8000,268,531 +E,7419,10,8000,268,531 +E,7420,10,8000,268,528 +E,7421,10,8000,268,528 +E,7422,10,8000,268,531 +E,7423,10,8000,268,531 +E,7424,10,8000,268,528 +E,7425,10,8000,268,528 +E,7426,10,8000,268,531 +E,7427,10,8000,268,531 +E,7428,10,8000,268,528 +E,7429,10,8000,268,528 +E,7430,10,8000,268,531 +E,7431,10,8000,268,531 +E,7432,10,8000,268,528 +E,7433,10,8000,268,528 +E,7434,10,8000,268,531 +E,7435,10,8000,268,531 +E,7436,10,8000,268,531 +E,7437,10,8000,268,528 +E,7438,10,8000,268,528 +E,7439,10,8000,268,531 +E,7440,10,8000,268,531 +E,7441,10,8000,268,528 +E,7442,10,8000,268,528 +E,7443,10,8000,268,531 +E,7444,10,8000,268,531 +E,7445,10,8000,268,528 +E,7446,10,8000,268,528 +E,7447,10,8000,268,531 +E,7448,10,8000,268,531 +E,7449,10,8000,268,528 +E,7450,10,8000,268,528 +E,7451,10,8000,268,531 +E,7452,10,8000,268,531 +E,7453,10,8000,268,531 +E,7454,10,8000,268,528 +E,7455,10,8000,268,528 +E,7456,10,8000,268,531 +E,7457,10,8000,268,531 +E,7458,10,8000,268,528 +E,7459,10,8000,268,528 +E,7460,10,8000,268,531 +E,7461,10,8000,268,531 +E,7462,10,8000,268,528 +E,7463,10,8000,268,528 +E,7464,10,8000,268,531 +E,7465,10,8000,268,531 +E,7466,10,8000,268,528 +E,7467,10,8000,268,528 +E,7468,10,8000,268,531 +E,7469,10,8000,268,531 +E,7470,10,8000,268,531 +E,7471,10,8000,268,528 +E,7472,10,8000,268,528 +E,7473,10,8000,268,531 +E,7474,10,8000,268,531 +E,7475,10,8000,268,528 +E,7476,10,8000,268,528 +E,7477,10,8000,268,531 +E,7478,10,8000,268,531 +E,7479,10,8000,268,528 +E,7480,10,8000,268,528 +E,7481,10,8000,268,531 +E,7482,10,8000,268,531 +E,7483,10,8000,268,528 +E,7484,10,8000,268,528 +E,7485,10,8000,268,531 +E,7486,10,8000,268,531 +E,7487,10,8000,268,528 +E,7488,10,8000,268,528 +E,7489,10,8000,268,531 +E,7490,10,8000,268,531 +E,7491,10,8000,268,528 +E,7492,10,8000,268,528 +E,7493,10,8000,268,531 +E,7494,10,8000,268,531 +E,7495,10,8000,268,528 +E,7496,10,8000,268,528 +E,7497,10,8000,268,531 +E,7498,10,8000,268,531 +E,7499,10,8000,268,528 +# step 11/13 rpm=8000 period_us=20 ints=200 count=7500 +D,step_11,2549929071,26,31,140,205,123 +H,step_11,0,0,0 +E,7500,11,9000,268,1302 +E,7501,11,9000,268,531 +E,7502,11,9000,268,528 +E,7503,11,9000,268,528 +E,7504,11,9000,268,531 +E,7505,11,9000,268,531 +E,7506,11,9000,268,528 +E,7507,11,9000,268,528 +E,7508,11,9000,268,531 +E,7509,11,9000,268,531 +E,7510,11,9000,268,528 +E,7511,11,9000,268,528 +E,7512,11,9000,268,531 +E,7513,11,9000,268,531 +E,7514,11,9000,268,528 +E,7515,11,9000,268,528 +E,7516,11,9000,268,531 +E,7517,11,9000,268,531 +E,7518,11,9000,268,528 +E,7519,11,9000,268,528 +E,7520,11,9000,268,531 +E,7521,11,9000,268,531 +E,7522,11,9000,268,528 +E,7523,11,9000,268,528 +E,7524,11,9000,268,531 +E,7525,11,9000,268,531 +E,7526,11,9000,268,528 +E,7527,11,9000,268,528 +E,7528,11,9000,268,531 +E,7529,11,9000,268,531 +E,7530,11,9000,268,528 +E,7531,11,9000,268,528 +E,7532,11,9000,268,531 +E,7533,11,9000,268,531 +E,7534,11,9000,268,528 +E,7535,11,9000,268,528 +E,7536,11,9000,268,531 +E,7537,11,9000,268,531 +E,7538,11,9000,268,531 +E,7539,11,9000,268,528 +E,7540,11,9000,268,528 +E,7541,11,9000,268,531 +E,7542,11,9000,268,531 +E,7543,11,9000,268,528 +E,7544,11,9000,268,528 +E,7545,11,9000,268,531 +E,7546,11,9000,268,531 +E,7547,11,9000,268,528 +E,7548,11,9000,268,528 +E,7549,11,9000,268,531 +E,7550,11,9000,268,531 +E,7551,11,9000,268,528 +E,7552,11,9000,268,528 +E,7553,11,9000,268,531 +E,7554,11,9000,268,531 +E,7555,11,9000,268,531 +E,7556,11,9000,268,528 +E,7557,11,9000,268,528 +E,7558,11,9000,268,531 +E,7559,11,9000,268,531 +E,7560,11,9000,268,528 +E,7561,11,9000,268,528 +E,7562,11,9000,268,531 +E,7563,11,9000,268,531 +E,7564,11,9000,268,528 +E,7565,11,9000,268,528 +E,7566,11,9000,268,531 +E,7567,11,9000,268,531 +E,7568,11,9000,268,528 +E,7569,11,9000,268,528 +E,7570,11,9000,268,531 +E,7571,11,9000,268,531 +E,7572,11,9000,268,531 +E,7573,11,9000,268,528 +E,7574,11,9000,268,528 +E,7575,11,9000,268,531 +E,7576,11,9000,268,531 +E,7577,11,9000,268,528 +E,7578,11,9000,268,528 +E,7579,11,9000,268,531 +E,7580,11,9000,268,531 +E,7581,11,9000,268,528 +E,7582,11,9000,268,528 +E,7583,11,9000,268,531 +E,7584,11,9000,268,531 +E,7585,11,9000,268,528 +E,7586,11,9000,268,528 +E,7587,11,9000,268,531 +E,7588,11,9000,268,531 +E,7589,11,9000,268,531 +E,7590,11,9000,268,528 +E,7591,11,9000,268,528 +E,7592,11,9000,268,531 +E,7593,11,9000,268,531 +E,7594,11,9000,268,528 +E,7595,11,9000,268,528 +E,7596,11,9000,268,531 +E,7597,11,9000,268,531 +E,7598,11,9000,268,528 +E,7599,11,9000,268,528 +E,7600,11,9000,268,531 +E,7601,11,9000,268,531 +E,7602,11,9000,268,531 +E,7603,11,9000,268,528 +E,7604,11,9000,268,528 +E,7605,11,9000,268,531 +E,7606,11,9000,268,531 +E,7607,11,9000,268,528 +E,7608,11,9000,268,528 +E,7609,11,9000,268,531 +E,7610,11,9000,268,531 +E,7611,11,9000,268,528 +E,7612,11,9000,268,528 +E,7613,11,9000,268,531 +E,7614,11,9000,268,531 +E,7615,11,9000,268,528 +E,7616,11,9000,268,528 +E,7617,11,9000,268,531 +E,7618,11,9000,268,531 +E,7619,11,9000,268,531 +E,7620,11,9000,268,528 +E,7621,11,9000,268,528 +E,7622,11,9000,268,531 +E,7623,11,9000,268,531 +E,7624,11,9000,268,528 +E,7625,11,9000,268,528 +E,7626,11,9000,268,531 +E,7627,11,9000,268,531 +E,7628,11,9000,268,528 +E,7629,11,9000,268,528 +E,7630,11,9000,268,531 +E,7631,11,9000,268,531 +E,7632,11,9000,268,528 +E,7633,11,9000,268,528 +E,7634,11,9000,268,531 +E,7635,11,9000,268,531 +E,7636,11,9000,268,531 +E,7637,11,9000,268,528 +E,7638,11,9000,268,528 +E,7639,11,9000,268,531 +E,7640,11,9000,268,531 +E,7641,11,9000,268,528 +E,7642,11,9000,268,528 +E,7643,11,9000,268,531 +E,7644,11,9000,268,531 +E,7645,11,9000,268,528 +E,7646,11,9000,268,528 +E,7647,11,9000,268,531 +E,7648,11,9000,268,531 +E,7649,11,9000,2# step 12/13 rpm=9000 period_us=18 ints=150 count=7649 +D,step_12,2604618337,42,117,207,231,161 +H,step_12,0,0,0 +68,528 +E,7650,12,10000,268,528 +E,7651,12,10000,268,528 +E,7652,12,10000,268,528 +E,7653,12,10000,268,528 +E,7654,12,10000,268,531 +E,7655,12,10000,268,531 +E,7656,12,10000,268,528 +E,7657,12,10000,268,528 +E,7658,12,10000,268,531 +E,7659,12,10000,268,531 +E,7660,12,10000,268,528 +E,7661,12,10000,268,528 +E,7662,12,10000,268,531 +E,7663,12,10000,268,531 +E,7664,12,10000,268,528 +E,7665,12,10000,268,528 +E,7666,12,10000,268,531 +E,7667,12,10000,268,531 +E,7668,12,10000,268,528 +E,7669,12,10000,268,528 +E,7670,12,10000,268,531 +E,7671,12,10000,268,531 +E,7672,12,10000,268,528 +E,7673,12,10000,268,528 +E,7674,12,10000,268,531 +E,7675,12,10000,268,531 +E,7676,12,10000,268,528 +E,7677,12,10000,268,528 +E,7678,12,10000,268,531 +E,7679,12,10000,268,531 +E,7680,12,10000,268,528 +E,7681,12,10000,268,528 +E,7682,12,10000,268,531 +E,7683,12,10000,268,531 +E,7684,12,10000,268,528 +E,7685,12,10000,268,528 +E,7686,12,10000,268,531 +E,7687,12,10000,268,531 +E,7688,12,10000,268,528 +E,7689,12,10000,268,528 +E,7690,12,10000,268,531 +E,7691,12,10000,268,531 +E,7692,12,10000,268,528 +E,7693,12,10000,268,528 +E,7694,12,10000,268,531 +E,7695,12,10000,268,531 +E,7696,12,10000,268,528 +E,7697,12,10000,268,528 +E,7698,12,10000,268,531 +E,7699,12,10000,268,531 +E,7700,12,10000,268,528 +E,7701,12,10000,268,528 +E,7702,12,10000,268,531 +E,7703,12,10000,268,531 +E,7704,12,10000,268,528 +E,7705,12,10000,268,528 +E,7706,12,10000,268,531 +E,7707,12,10000,268,531 +E,7708,12,10000,268,528 +E,7709,12,10000,268,528 +E,7710,12,10000,268,531 +E,7711,12,10000,268,531 +E,7712,12,10000,268,528 +E,7713,12,10000,268,528 +E,7714,12,10000,268,531 +E,7715,12,10000,268,531 +E,7716,12,10000,268,528 +E,7717,12,10000,268,528 +E,7718,12,10000,268,531 +E,7719,12,10000,268,531 +E,7720,12,10000,268,528 +E,7721,12,10000,268,528 +E,7722,12,10000,268,531 +E,7723,12,10000,268,531 +E,7724,12,10000,268,528 +E,7725,12,10000,268,528 +E,7726,12,10000,268,531 +E,7727,12,10000,268,531 +E,7728,12,10000,268,528 +E,7729,12,10000,268,528 +E,7730,12,10000,268,531 +E,7731,12,10000,268,531 +E,7732,12,10000,268,528 +E,7733,12,10000,268,528 +E,7734,12,10000,268,531 +E,7735,12,10000,268,531 +E,7736,12,10000,268,528 +E,7737,12,10000,268,528 +E,7738,12,10000,268,531 +E,7739,12,10000,268,531 +E,7740,12,10000,268,528 +E,7741,12,10000,268,528 +E,7742,12,10000,268,531 +E,7743,12,10000,268,531 +E,7744,12,10000,268,528 +E,7745,12,10000,268,528 +E,7746,12,10000,268,531 +E,7747,12,10000,268,531 +E,7748,12,10000,268,528 +E,7749,12# step 13/13 rpm=10000 period_us=16 ints=100 count=7749 +D,step_13,2643089715,40,232,207,254,204 +H,step_13,0,0,0 +,10000,268,528 +D,end,2644181325,11,2,207,238,48 +H,end,0,0,0 +drops,0 +samples,7750 +=== END === diff --git a/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-b48a81ac-gale-lto-noadc-systick/events.csv b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-b48a81ac-gale-lto-noadc-systick/events.csv new file mode 100644 index 00000000..9420ab43 --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-b48a81ac-gale-lto-noadc-systick/events.csv @@ -0,0 +1,7371 @@ +# Rsilicon-2026-05-10 gale-lto: H ready: temp_mC,vref_mV via ADC1 ch16 + ch18; VBAT not wired (always 0) +# Rsilicon-2026-05-10 gale-lto: H cal: TS_CAL1=1034@30C TS_CAL2=1367@130C VREFINT_CAL=1659@3000mV +M,Rsilicon-2026-05-10,gale-lto,build,gale +M,Rsilicon-2026-05-10,gale-lto,cycles_per_sec,170000000 +M,Rsilicon-2026-05-10,gale-lto,target_samples,7750 +# Rsilicon-2026-05-10 gale-lto: event rows: E,,,,, +# Rsilicon-2026-05-10 gale-lto: DWT rows: D,,,,,,, +# Rsilicon-2026-05-10 gale-lto: health rows:H,,,, +Rsilicon-2026-05-10,gale-lto,D,boot,6498982,119,52,0,93,32 +# Rsilicon-2026-05-10 gale-lto: H ready: temp_mC,vref_mV via ADC1 ch16 + ch18; VBAT not wired (always 0) +# Rsilicon-2026-05-10 gale-lto: H cal: TS_CAL1=1034@30C TS_CAL2=1367@130C VREFINT_CAL=1659@3000mV +M,Rsilicon-2026-05-10,gale-lto,build,gale +M,Rsilicon-2026-05-10,gale-lto,cycles_per_sec, +Rsilicon-2026-05-10,gale-lto,E,432,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,433,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,434,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,435,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,436,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,437,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,438,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,439,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,440,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,441,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,442,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,443,0,500,243,471 +Rsilicon-2026-05-10,gale-lto,E,444,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,445,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,446,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,447,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,448,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,449,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,450,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,451,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,452,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,453,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,454,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,455,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,456,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,457,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,458,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,459,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,460,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,461,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,462,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,463,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,464,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,465,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,466,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,467,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,468,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,469,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,470,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,471,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,472,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,473,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,474,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,475,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,476,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,477,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,478,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,479,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,480,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,481,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,482,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,483,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,484,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,485,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,486,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,487,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,488,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,489,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,490,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,491,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,492,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,493,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,494,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,495,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,496,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,497,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,498,0,500,245,471 +Rsilicon-2026-05-10,gale-lto,E,4# step 1/13 rpm=500 period_us=333 ints=500 count=499 +Rsilicon-2026-05-10,gale-lto,D,step_1,160029965,100,117,80,181,25 +Rsilicon-2026-05-10,gale-lto,H,step_1,0,0,0 +Rsilicon-2026-05-10,gale-lto,E,500,1,1000,245,471 +Rsilicon-2026-05-10,gale-lto,E,501,1,1000,245,471 +Rsilicon-2026-05-10,gale-lto,E,502,1,1000,245,471 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+Rsilicon-2026-05-10,gale-lto,E,7293,9,7000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7294,9,7000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7295,9,7000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7296,9,7000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7297,9,7000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7298,9,7000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7299,9,7000,246,471 +# Rsilicon-2026-05-10 gale-lto: step 10/13 rpm=7000 period_us=23 ints=300 count=7300 +Rsilicon-2026-05-10,gale-lto,D,step_10,2477291360,46,233,190,156,42 +Rsilicon-2026-05-10,gale-lto,H,step_10,0,0,0 +Rsilicon-2026-05-10,gale-lto,E,7300,10,8000,246,1301 +Rsilicon-2026-05-10,gale-lto,E,7301,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7302,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7303,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7304,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7305,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7306,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7307,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7308,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7309,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7310,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7311,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7312,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7313,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7314,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7315,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7316,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7317,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7318,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7319,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7320,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7321,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7322,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7323,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7324,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7325,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7326,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7327,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7328,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7329,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7330,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7331,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7332,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7333,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7334,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7335,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7336,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7337,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7338,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7339,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7340,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7341,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7342,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7343,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7344,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7345,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7346,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7347,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7348,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7349,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7350,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7351,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7352,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7353,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7354,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7355,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7356,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7357,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7358,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7359,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7360,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7361,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7362,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7363,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7364,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7365,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7366,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7367,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7368,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7369,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7370,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7371,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7372,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7373,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7374,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7375,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7376,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7377,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7378,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7379,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7380,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7381,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7382,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7383,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7384,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7385,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7386,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7387,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7388,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7389,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7390,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7391,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7392,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7393,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7394,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7395,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7396,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7397,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7398,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7399,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7400,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7401,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7402,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7403,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7404,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7405,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7406,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7407,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7408,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7409,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7410,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7411,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7412,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7413,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7414,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7415,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7416,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7417,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7418,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7419,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7420,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7421,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7422,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7423,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7424,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7425,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7426,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7427,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7428,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7429,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7430,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7431,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7432,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7433,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7434,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7435,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7436,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7437,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7438,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7439,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7440,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7441,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7442,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7443,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7444,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7445,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7446,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7447,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7448,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7449,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7450,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7451,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7452,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7453,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7454,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7455,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7456,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7457,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7458,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7459,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7460,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7461,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7462,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7463,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7464,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7465,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7466,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7467,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7468,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7469,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7470,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7471,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7472,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7473,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7474,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7475,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7476,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7477,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7478,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7479,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7480,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7481,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7482,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7483,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7484,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7485,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7486,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7487,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7488,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7489,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7490,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7491,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7492,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7493,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7494,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7495,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7496,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7497,10,8000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7498,10,8000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7499,10,8000,246,474 +# Rsilicon-2026-05-10 gale-lto: step 11/13 rpm=8000 period_us=20 ints=200 count=7500 +Rsilicon-2026-05-10,gale-lto,D,step_11,2549932111,74,242,41,200,244 +Rsilicon-2026-05-10,gale-lto,H,step_11,0,0,0 +Rsilicon-2026-05-10,gale-lto,E,7500,11,9000,246,1301 +Rsilicon-2026-05-10,gale-lto,E,7501,11,9000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7502,11,9000,246,471 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+Rsilicon-2026-05-10,gale-lto,E,7629,11,9000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7630,11,9000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7631,11,9000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7632,11,9000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7633,11,9000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7634,11,9000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7635,11,9000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7636,11,9000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7637,11,9000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7638,11,9000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7639,11,9000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7640,11,9000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7641,11,9000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7642,11,9000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7643,11,9000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7644,11,9000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7645,11,9000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7646,11,9000,246,474 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+Rsilicon-2026-05-10,gale-lto,E,7680,12,10000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7681,12,10000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7682,12,10000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7683,12,10000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7684,12,10000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7685,12,10000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7686,12,10000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7687,12,10000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7688,12,10000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7689,12,10000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7690,12,10000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7691,12,10000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7692,12,10000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7693,12,10000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7694,12,10000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7695,12,10000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7696,12,10000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7697,12,10000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7698,12,10000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7699,12,10000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7700,12,10000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7701,12,10000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7702,12,10000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7703,12,10000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7704,12,10000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7705,12,10000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7706,12,10000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7707,12,10000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7708,12,10000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7709,12,10000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7710,12,10000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7711,12,10000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7712,12,10000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7713,12,10000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7714,12,10000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7715,12,10000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7716,12,10000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7717,12,10000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7718,12,10000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7719,12,10000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7720,12,10000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7721,12,10000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7722,12,10000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7723,12,10000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7724,12,10000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7725,12,10000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7726,12,10000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7727,12,10000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7728,12,10000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7729,12,10000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7730,12,10000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7731,12,10000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7732,12,10000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7733,12,10000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7734,12,10000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7735,12,10000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7736,12,10000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7737,12,10000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7738,12,10000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7739,12,10000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7740,12,10000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7741,12,10000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7742,12,10000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7743,12,10000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7744,12,10000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7745,12,10000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7746,12,10000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7747,12,10000,246,474 +Rsilicon-2026-05-10,gale-lto,E,7748,12,10000,246,471 +Rsilicon-2026-05-10,gale-lto,E,7749,12# step 13/13 rpm=10000 period_us=16 ints=100 count=7749 +Rsilicon-2026-05-10,gale-lto,D,step_13,2643077998,204,166,89,152,147 +Rsilicon-2026-05-10,gale-lto,H,step_13,0,0,0 +Rsilicon-2026-05-10,gale-lto,D,end,2644169725,30,194,89,87,242 +Rsilicon-2026-05-10,gale-lto,H,end,0,0,0 +M,Rsilicon-2026-05-10,gale-lto,drops,0 +M,Rsilicon-2026-05-10,gale-lto,samples,7750 +M,Rsilicon-2026-05-10,gale-lto,END diff --git a/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-b48a81ac-gale-lto-noadc-systick/firmware.elf b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-b48a81ac-gale-lto-noadc-systick/firmware.elf new file mode 100755 index 00000000..5a3c1496 Binary files /dev/null and b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-b48a81ac-gale-lto-noadc-systick/firmware.elf differ diff --git a/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-b48a81ac-gale-lto-noadc-systick/firmware.elf.sha256 b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-b48a81ac-gale-lto-noadc-systick/firmware.elf.sha256 new file mode 100644 index 00000000..535b3dfc --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-b48a81ac-gale-lto-noadc-systick/firmware.elf.sha256 @@ -0,0 +1 @@ +318f5f46bc3bfa13de908812cb8402f34b0b73910cc64f81cfca6e6dd0bd938d firmware.elf diff --git a/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-b48a81ac-gale-lto-noadc-systick/manifest.txt b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-b48a81ac-gale-lto-noadc-systick/manifest.txt new file mode 100644 index 00000000..397c8eac --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-b48a81ac-gale-lto-noadc-systick/manifest.txt @@ -0,0 +1,23 @@ +# Silicon-anchor manifest +# Produced by manual flash/capture pipeline (LTO + control experiments) +captured_at: 2026-05-10T11:22:21Z +board: nucleo_g474re +variant: gale-lto +adc_enabled: false +dt_overrides: adc1=disabled +tick_source: systick +sweep: long +flash_runner: openocd +gale_sha: b48a81ac69cbcb6c50495d31b603d910f73a85d5 +gale_status: clean +host: Darwin 25.3.0 arm64 +rustc: rustc 1.94.1 (e408947bf 2026-03-25) +zephyr_base: /Volumes/Home/git/pulseengine/zephyr +zephyr_sha: fc4d89c118fc1d0ff0ad31906a4fa4bd252c9ced +sdk_dir: /Volumes/Home/zephyr-sdk/zephyr-sdk-1.0.1 +elf_sha256: 318f5f46bc3bfa13de908812cb8402f34b0b73910cc64f81cfca6e6dd0bd938d +csv_sha256: f6d40f7b487d8d91258de1cca38db825d199aa6d785407cb5e138b0c09cd8115 +csv_bytes: 170676 +csv_event_lines: 7318 +serial_port: /dev/cu.usbmodem132203 +capture_timeout_s: 1800 diff --git a/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-b48a81ac-gale-lto-noadc-systick/output.csv b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-b48a81ac-gale-lto-noadc-systick/output.csv new file mode 100644 index 00000000..07a703eb --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-b48a81ac-gale-lto-noadc-systick/output.csv @@ -0,0 +1,7382 @@ + OS build fc4d89c118fc *** +engine_control bench starting (target 7750 samples, 13 sweep steps) +# H ready: temp_mC,vref_mV via ADC1 ch16 + ch18; VBAT not wired (always 0) +# H cal: TS_CAL1=1034@30C TS_CAL2=1367@130C VREFINT_CAL=1659@3000mV +=== ENGINE-CONTROL BENCH RESULTS === +build,gale +cycles_per_sec,170000000 +target_samples,7750 +# event rows: E,,,,, +# DWT rows: D,,,,,,, +# health rows:H,,,, +D,boot,6498982,119,52,0,93,32 +Unhandled IRQn: 18 +*** Booting Zephyr OS build fc4d89c118fc *** +engine_control bench starting (target 7750 samples, 13 sweep steps) +# H ready: temp_mC,vref_mV via ADC1 ch16 + ch18; VBAT not wired (always 0) +# H cal: TS_CAL1=1034@30C TS_CAL2=1367@130C VREFINT_CAL=1659@3000mV +=== ENGINE-CONTROL BENCH RESULTS === +build,gale +cycles_per_sec, +E,432,0,500,245,471 +E,433,0,500,245,471 +E,434,0,500,245,471 +E,435,0,500,245,471 +E,436,0,500,245,471 +E,437,0,500,245,471 +E,438,0,500,245,471 +E,439,0,500,245,471 +E,440,0,500,245,471 +E,441,0,500,245,471 +E,442,0,500,245,471 +E,443,0,500,243,471 +E,444,0,500,245,471 +E,445,0,500,245,471 +E,446,0,500,245,471 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+E,494,0,500,245,471 +E,495,0,500,245,471 +E,496,0,500,245,471 +E,497,0,500,245,471 +E,498,0,500,245,471 +E,4# step 1/13 rpm=500 period_us=333 ints=500 count=499 +D,step_1,160029965,100,117,80,181,25 +H,step_1,0,0,0 +99,0,500,245,471 +E,500,1,1000,245,471 +E,501,1,1000,245,471 +E,502,1,1000,245,471 +E,503,1,1000,245,471 +E,504,1,1000,245,471 +E,505,1,1000,245,471 +E,506,1,1000,245,471 +E,507,1,1000,245,471 +E,508,1,1000,245,471 +E,509,1,1000,245,471 +E,510,1,1000,245,471 +E,511,1,1000,245,471 +E,512,1,1000,245,471 +E,513,1,1000,245,471 +E,514,1,1000,245,471 +E,515,1,1000,245,471 +E,516,1,1000,245,471 +E,517,1,1000,245,471 +E,518,1,1000,245,471 +E,519,1,1000,245,471 +E,520,1,1000,245,471 +E,521,1,1000,245,471 +E,522,1,1000,245,471 +E,523,1,1000,245,471 +E,524,1,1000,245,471 +E,525,1,1000,245,471 +E,526,1,1000,245,471 +E,527,1,1000,245,471 +E,528,1,1000,245,471 +E,529,1,1000,245,471 +E,530,1,1000,245,471 +E,531,1,1000,245,471 +E,532,1,1000,245,471 +E,533,1,1000,245,471 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+E,7267,9,7000,246,471 +E,7268,9,7000,246,471 +E,7269,9,7000,246,471 +E,7270,9,7000,246,471 +E,7271,9,7000,246,471 +E,7272,9,7000,246,471 +E,7273,9,7000,246,471 +E,7274,9,7000,246,471 +E,7275,9,7000,246,471 +E,7276,9,7000,246,471 +E,7277,9,7000,246,471 +E,7278,9,7000,246,471 +E,7279,9,7000,246,471 +E,7280,9,7000,246,471 +E,7281,9,7000,246,471 +E,7282,9,7000,246,471 +E,7283,9,7000,246,471 +E,7284,9,7000,246,471 +E,7285,9,7000,246,471 +E,7286,9,7000,246,471 +E,7287,9,7000,246,471 +E,7288,9,7000,246,471 +E,7289,9,7000,246,471 +E,7290,9,7000,246,471 +E,7291,9,7000,246,471 +E,7292,9,7000,246,471 +E,7293,9,7000,246,471 +E,7294,9,7000,246,471 +E,7295,9,7000,246,471 +E,7296,9,7000,246,471 +E,7297,9,7000,246,471 +E,7298,9,7000,246,471 +E,7299,9,7000,246,471 +# step 10/13 rpm=7000 period_us=23 ints=300 count=7300 +D,step_10,2477291360,46,233,190,156,42 +H,step_10,0,0,0 +E,7300,10,8000,246,1301 +E,7301,10,8000,246,471 +E,7302,10,8000,246,471 +E,7303,10,8000,246,474 +E,7304,10,8000,246,474 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+E,7346,10,8000,246,471 +E,7347,10,8000,246,471 +E,7348,10,8000,246,474 +E,7349,10,8000,246,474 +E,7350,10,8000,246,474 +E,7351,10,8000,246,471 +E,7352,10,8000,246,471 +E,7353,10,8000,246,474 +E,7354,10,8000,246,474 +E,7355,10,8000,246,474 +E,7356,10,8000,246,474 +E,7357,10,8000,246,471 +E,7358,10,8000,246,471 +E,7359,10,8000,246,474 +E,7360,10,8000,246,474 +E,7361,10,8000,246,474 +E,7362,10,8000,246,474 +E,7363,10,8000,246,471 +E,7364,10,8000,246,471 +E,7365,10,8000,246,474 +E,7366,10,8000,246,474 +E,7367,10,8000,246,474 +E,7368,10,8000,246,471 +E,7369,10,8000,246,471 +E,7370,10,8000,246,474 +E,7371,10,8000,246,474 +E,7372,10,8000,246,474 +E,7373,10,8000,246,474 +E,7374,10,8000,246,471 +E,7375,10,8000,246,471 +E,7376,10,8000,246,474 +E,7377,10,8000,246,474 +E,7378,10,8000,246,474 +E,7379,10,8000,246,474 +E,7380,10,8000,246,471 +E,7381,10,8000,246,471 +E,7382,10,8000,246,474 +E,7383,10,8000,246,474 +E,7384,10,8000,246,474 +E,7385,10,8000,246,471 +E,7386,10,8000,246,471 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+E,7428,10,8000,246,471 +E,7429,10,8000,246,474 +E,7430,10,8000,246,474 +E,7431,10,8000,246,474 +E,7432,10,8000,246,471 +E,7433,10,8000,246,471 +E,7434,10,8000,246,474 +E,7435,10,8000,246,474 +E,7436,10,8000,246,474 +E,7437,10,8000,246,474 +E,7438,10,8000,246,471 +E,7439,10,8000,246,471 +E,7440,10,8000,246,474 +E,7441,10,8000,246,474 +E,7442,10,8000,246,474 +E,7443,10,8000,246,474 +E,7444,10,8000,246,471 +E,7445,10,8000,246,471 +E,7446,10,8000,246,474 +E,7447,10,8000,246,474 +E,7448,10,8000,246,474 +E,7449,10,8000,246,471 +E,7450,10,8000,246,471 +E,7451,10,8000,246,474 +E,7452,10,8000,246,474 +E,7453,10,8000,246,474 +E,7454,10,8000,246,471 +E,7455,10,8000,246,471 +E,7456,10,8000,246,474 +E,7457,10,8000,246,474 +E,7458,10,8000,246,474 +E,7459,10,8000,246,474 +E,7460,10,8000,246,471 +E,7461,10,8000,246,471 +E,7462,10,8000,246,474 +E,7463,10,8000,246,474 +E,7464,10,8000,246,474 +E,7465,10,8000,246,474 +E,7466,10,8000,246,471 +E,7467,10,8000,246,471 +E,7468,10,8000,246,474 +E,7469,10,8000,246,474 +E,7470,10,8000,246,474 +E,7471,10,8000,246,474 +E,7472,10,8000,246,471 +E,7473,10,8000,246,471 +E,7474,10,8000,246,474 +E,7475,10,8000,246,474 +E,7476,10,8000,246,474 +E,7477,10,8000,246,474 +E,7478,10,8000,246,471 +E,7479,10,8000,246,471 +E,7480,10,8000,246,474 +E,7481,10,8000,246,474 +E,7482,10,8000,246,474 +E,7483,10,8000,246,474 +E,7484,10,8000,246,471 +E,7485,10,8000,246,471 +E,7486,10,8000,246,474 +E,7487,10,8000,246,474 +E,7488,10,8000,246,474 +E,7489,10,8000,246,474 +E,7490,10,8000,246,471 +E,7491,10,8000,246,471 +E,7492,10,8000,246,474 +E,7493,10,8000,246,474 +E,7494,10,8000,246,474 +E,7495,10,8000,246,474 +E,7496,10,8000,246,471 +E,7497,10,8000,246,471 +E,7498,10,8000,246,474 +E,7499,10,8000,246,474 +# step 11/13 rpm=8000 period_us=20 ints=200 count=7500 +D,step_11,2549932111,74,242,41,200,244 +H,step_11,0,0,0 +E,7500,11,9000,246,1301 +E,7501,11,9000,246,471 +E,7502,11,9000,246,471 +E,7503,11,9000,246,474 +E,7504,11,9000,246,474 +E,7505,11,9000,246,474 +E,7506,11,9000,246,471 +E,7507,11,9000,246,471 +E,7508,11,9000,246,474 +E,7509,11,9000,246,474 +E,7510,11,9000,246,474 +E,7511,11,9000,246,474 +E,7512,11,9000,246,471 +E,7513,11,9000,246,471 +E,7514,11,9000,246,474 +E,7515,11,9000,246,474 +E,7516,11,9000,246,474 +E,7517,11,9000,246,471 +E,7518,11,9000,246,471 +E,7519,11,9000,246,474 +E,7520,11,9000,246,474 +E,7521,11,9000,246,474 +E,7522,11,9000,246,474 +E,7523,11,9000,246,471 +E,7524,11,9000,246,471 +E,7525,11,9000,246,474 +E,7526,11,9000,246,474 +E,7527,11,9000,246,474 +E,7528,11,9000,246,474 +E,7529,11,9000,246,471 +E,7530,11,9000,246,471 +E,7531,11,9000,246,474 +E,7532,11,9000,246,474 +E,7533,11,9000,246,474 +E,7534,11,9000,246,471 +E,7535,11,9000,246,471 +E,7536,11,9000,246,474 +E,7537,11,9000,246,474 +E,7538,11,9000,246,474 +E,7539,11,9000,246,474 +E,7540,11,9000,246,471 +E,7541,11,9000,246,471 +E,7542,11,9000,246,474 +E,7543,11,9000,246,474 +E,7544,11,9000,246,474 +E,7545,11,9000,246,474 +E,7546,11,9000,246,471 +E,7547,11,9000,246,471 +E,7548,11,9000,246,474 +E,7549,11,9000,246,474 +E,7550,11,9000,246,474 +E,7551,11,9000,246,471 +E,7552,11,9000,246,471 +E,7553,11,9000,246,474 +E,7554,11,9000,246,474 +E,7555,11,9000,246,474 +E,7556,11,9000,246,474 +E,7557,11,9000,246,471 +E,7558,11,9000,246,471 +E,7559,11,9000,246,474 +E,7560,11,9000,246,474 +E,7561,11,9000,246,474 +E,7562,11,9000,246,474 +E,7563,11,9000,246,471 +E,7564,11,9000,246,471 +E,7565,11,9000,246,474 +E,7566,11,9000,246,474 +E,7567,11,9000,246,474 +E,7568,11,9000,246,471 +E,7569,11,9000,246,471 +E,7570,11,9000,246,474 +E,7571,11,9000,246,474 +E,7572,11,9000,246,474 +E,7573,11,9000,246,474 +E,7574,11,9000,246,471 +E,7575,11,9000,246,471 +E,7576,11,9000,246,474 +E,7577,11,9000,246,474 +E,7578,11,9000,246,474 +E,7579,11,9000,246,474 +E,7580,11,9000,246,471 +E,7581,11,9000,246,471 +E,7582,11,9000,246,474 +E,7583,11,9000,246,474 +E,7584,11,9000,246,474 +E,7585,11,9000,246,471 +E,7586,11,9000,246,471 +E,7587,11,9000,246,474 +E,7588,11,9000,246,474 +E,7589,11,9000,246,474 +E,7590,11,9000,246,474 +E,7591,11,9000,246,471 +E,7592,11,9000,246,471 +E,7593,11,9000,246,474 +E,7594,11,9000,246,474 +E,7595,11,9000,246,474 +E,7596,11,9000,246,474 +E,7597,11,9000,246,471 +E,7598,11,9000,246,471 +E,7599,11,9000,246,474 +E,7600,11,9000,246,474 +E,7601,11,9000,246,474 +E,7602,11,9000,246,474 +E,7603,11,9000,246,471 +E,7604,11,9000,246,471 +E,7605,11,9000,246,474 +E,7606,11,9000,246,474 +E,7607,11,9000,246,474 +E,7608,11,9000,246,474 +E,7609,11,9000,246,471 +E,7610,11,9000,246,471 +E,7611,11,9000,246,474 +E,7612,11,9000,246,474 +E,7613,11,9000,246,474 +E,7614,11,9000,246,474 +E,7615,11,9000,246,471 +E,7616,11,9000,246,471 +E,7617,11,9000,246,474 +E,7618,11,9000,246,474 +E,7619,11,9000,246,474 +E,7620,11,9000,246,474 +E,7621,11,9000,246,471 +E,7622,11,9000,246,471 +E,7623,11,9000,246,474 +E,7624,11,9000,246,474 +E,7625,11,9000,246,474 +E,7626,11,9000,246,474 +E,7627,11,9000,246,471 +E,7628,11,9000,246,471 +E,7629,11,9000,246,474 +E,7630,11,9000,246,474 +E,7631,11,9000,246,474 +E,7632,11,9000,246,471 +E,7633,11,9000,246,471 +E,7634,11,9000,246,474 +E,7635,11,9000,246,474 +E,7636,11,9000,246,474 +E,7637,11,9000,246,474 +E,7638,11,9000,246,471 +E,7639,11,9000,246,471 +E,7640,11,9000,246,474 +E,7641,11,9000,246,474 +E,7642,11,9000,246,474 +E,7643,11,9000,246,474 +E,7644,11,9000,246,471 +E,7645,11,9000,246,471 +E,7646,11,9000,246,474 +E,7647,11,9000,246,474 +E,7648,11,9000,246,474 +E,7649,11,9000,2# step 12/13 rpm=9000 period_us=18 ints=150 count=7649 +D,step_12,2604621372,24,100,89,104,181 +H,step_12,0,0,0 +46,471 +E,7650,12,10000,246,471 +E,7651,12,10000,246,471 +E,7652,12,10000,246,471 +E,7653,12,10000,246,471 +E,7654,12,10000,246,474 +E,7655,12,10000,246,474 +E,7656,12,10000,246,474 +E,7657,12,10000,246,471 +E,7658,12,10000,246,471 +E,7659,12,10000,246,474 +E,7660,12,10000,246,474 +E,7661,12,10000,246,474 +E,7662,12,10000,246,474 +E,7663,12,10000,246,471 +E,7664,12,10000,246,471 +E,7665,12,10000,246,474 +E,7666,12,10000,246,474 +E,7667,12,10000,246,474 +E,7668,12,10000,246,474 +E,7669,12,10000,246,471 +E,7670,12,10000,246,471 +E,7671,12,10000,246,474 +E,7672,12,10000,246,474 +E,7673,12,10000,246,474 +E,7674,12,10000,246,474 +E,7675,12,10000,246,471 +E,7676,12,10000,246,471 +E,7677,12,10000,246,474 +E,7678,12,10000,246,474 +E,7679,12,10000,246,474 +E,7680,12,10000,246,471 +E,7681,12,10000,246,471 +E,7682,12,10000,246,474 +E,7683,12,10000,246,474 +E,7684,12,10000,246,474 +E,7685,12,10000,246,471 +E,7686,12,10000,246,471 +E,7687,12,10000,246,474 +E,7688,12,10000,246,474 +E,7689,12,10000,246,474 +E,7690,12,10000,246,474 +E,7691,12,10000,246,471 +E,7692,12,10000,246,471 +E,7693,12,10000,246,474 +E,7694,12,10000,246,474 +E,7695,12,10000,246,474 +E,7696,12,10000,246,474 +E,7697,12,10000,246,471 +E,7698,12,10000,246,471 +E,7699,12,10000,246,474 +E,7700,12,10000,246,474 +E,7701,12,10000,246,474 +E,7702,12,10000,246,474 +E,7703,12,10000,246,471 +E,7704,12,10000,246,471 +E,7705,12,10000,246,474 +E,7706,12,10000,246,474 +E,7707,12,10000,246,474 +E,7708,12,10000,246,474 +E,7709,12,10000,246,471 +E,7710,12,10000,246,471 +E,7711,12,10000,246,474 +E,7712,12,10000,246,474 +E,7713,12,10000,246,474 +E,7714,12,10000,246,471 +E,7715,12,10000,246,471 +E,7716,12,10000,246,474 +E,7717,12,10000,246,474 +E,7718,12,10000,246,474 +E,7719,12,10000,246,474 +E,7720,12,10000,246,471 +E,7721,12,10000,246,471 +E,7722,12,10000,246,474 +E,7723,12,10000,246,474 +E,7724,12,10000,246,474 +E,7725,12,10000,246,474 +E,7726,12,10000,246,471 +E,7727,12,10000,246,471 +E,7728,12,10000,246,474 +E,7729,12,10000,246,474 +E,7730,12,10000,246,474 +E,7731,12,10000,246,471 +E,7732,12,10000,246,471 +E,7733,12,10000,246,474 +E,7734,12,10000,246,474 +E,7735,12,10000,246,474 +E,7736,12,10000,246,474 +E,7737,12,10000,246,471 +E,7738,12,10000,246,471 +E,7739,12,10000,246,474 +E,7740,12,10000,246,474 +E,7741,12,10000,246,474 +E,7742,12,10000,246,474 +E,7743,12,10000,246,471 +E,7744,12,10000,246,471 +E,7745,12,10000,246,474 +E,7746,12,10000,246,474 +E,7747,12,10000,246,474 +E,7748,12,10000,246,471 +E,7749,12# step 13/13 rpm=10000 period_us=16 ints=100 count=7749 +D,step_13,2643077998,204,166,89,152,147 +H,step_13,0,0,0 +,10000,246,471 +D,end,2644169725,30,194,89,87,242 +H,end,0,0,0 +drops,0 +samples,7750 +=== END === diff --git a/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-b48a81ac-gale-noadc-systick/events.csv b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-b48a81ac-gale-noadc-systick/events.csv new file mode 100644 index 00000000..6565a9d6 --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-b48a81ac-gale-noadc-systick/events.csv @@ -0,0 +1,7376 @@ +Rsilicon-2026-05-10,gale,E,414,0,500,268,574 +Rsilicon-2026-05-10,gale,E,415,0,500,268,574 +Rsilicon-2026-05-10,gale,E,416,0,500,268,574 +Rsilicon-2026-05-10,gale,E,417,0,500,268,574 +Rsilicon-2026-05-10,gale,E,418,0,500,268,574 +Rsilicon-2026-05-10,gale,E,419,0,500,268,574 +Rsilicon-2026-05-10,gale,E,420,0,500,268,574 +Rsilicon-2026-05-10,gale,E,421,0,500,268,574 +Rsilicon-2026-05-10,gale,E,422,0,500,268,574 +Rsilicon-2026-05-10,gale,E,423,0,500,268,574 +Rsilicon-2026-05-10,gale,E,424,0,500,268,574 +Rsilicon-2026-05-10,gale,E,425,0,500,268,574 +Rsilicon-2026-05-10,gale,E,426,0,500,268,574 +Rsilicon-2026-05-10,gale,E,427,0,500,268,574 +Rsilicon-2026-05-10,gale,E,428,0,500,268,574 +Rsilicon-2026-05-10,gale,E,429,0,500,268,574 +Rsilicon-2026-05-10,gale,E,430,0,500,268,574 +Rsilicon-2026-05-10,gale,E,431,0,500,268,574 +Rsilicon-2026-05-10,gale,E,432,0,500,268,574 +Rsilicon-2026-05-10,gale,E,433,0,500,268,574 +Rsilicon-2026-05-10,gale,E,434,0,500,268,574 +Rsilicon-2026-05-10,gale,E,435,0,500,268,574 +Rsilicon-2026-05-10,gale,E,436,0,500,268,574 +Rsilicon-2026-05-10,gale,E,437,0,500,268,574 +Rsilicon-2026-05-10,gale,E,438,0,500,268,574 +Rsilicon-2026-05-10,gale,E,439,0,500,268,574 +Rsilicon-2026-05-10,gale,E,440,0,500,268,574 +Rsilicon-2026-05-10,gale,E,441,0,500,268,574 +Rsilicon-2026-05-10,gale,E,442,0,500,268,574 +Rsilicon-2026-05-10,gale,E,443,0,500,268,574 +Rsilicon-2026-05-10,gale,E,444,0,500,268,574 +Rsilicon-2026-05-10,gale,E,445,0,500,268,574 +Rsilicon-2026-05-10,gale,E,446,0,500,268,574 +Rsilicon-2026-05-10,gale,E,447,0,500,268,574 +Rsilicon-2026-05-10,gale,E,448,0,500,268,574 +Rsilicon-2026-05-10,gale,E,449,0,500,268,574 +Rsilicon-2026-05-10,gale,E,450,0,500,268,574 +Rsilicon-2026-05-10,gale,E,451,0,500,268,574 +Rsilicon-2026-05-10,gale,E,452,0,500,268,574 +Rsilicon-2026-05-10,gale,E,453,0,500,268,574 +Rsilicon-2026-05-10,gale,E,454,0,500,268,574 +Rsilicon-2026-05-10,gale,E,455,0,500,268,574 +Rsilicon-2026-05-10,gale,E,456,0,500,268,574 +Rsilicon-2026-05-10,gale,E,457,0,500,268,574 +Rsilicon-2026-05-10,gale,E,458,0,500,268,574 +Rsilicon-2026-05-10,gale,E,459,0,500,268,574 +Rsilicon-2026-05-10,gale,E,460,0,500,268,574 +Rsilicon-2026-05-10,gale,E,461,0,500,268,574 +Rsilicon-2026-05-10,gale,E,462,0,500,268,574 +Rsilicon-2026-05-10,gale,E,463,0,500,268,574 +Rsilicon-2026-05-10,gale,E,464,0,500,268,574 +Rsilicon-2026-05-10,gale,E,465,0,500,268,574 +Rsilicon-2026-05-10,gale,E,466,0,500,268,574 +Rsilicon-2026-05-10,gale,E,467,0,500,268,574 +Rsilicon-2026-05-10,gale,E,468,0,500,268,574 +Rsilicon-2026-05-10,gale,E,469,0,500,268,574 +Rsilicon-2026-05-10,gale,E,470,0,500,268,574 +Rsilicon-2026-05-10,gale,E,471,0,500,268,574 +Rsilicon-2026-05-10,gale,E,472,0,500,268,574 +Rsilicon-2026-05-10,gale,E,473,0,500,268,574 +Rsilicon-2026-05-10,gale,E,474,0,500,268,574 +Rsilicon-2026-05-10,gale,E,475,0,500,268,574 +Rsilicon-2026-05-10,gale,E,476,0,500,268,574 +Rsilicon-2026-05-10,gale,E,477,0,500,268,574 +Rsilicon-2026-05-10,gale,E,478,0,500,268,574 +Rsilicon-2026-05-10,gale,E,479,0,500,268,574 +Rsilicon-2026-05-10,gale,E,480,0,500,268,574 +Rsilicon-2026-05-10,gale,E,481,0,500,268,574 +Rsilicon-2026-05-10,gale,E,482,0,500,268,574 +Rsilicon-2026-05-10,gale,E,483,0,500,268,574 +Rsilicon-2026-05-10,gale,E,484,0,500,268,574 +Rsilicon-2026-05-10,gale,E,485,0,500,268,574 +Rsilicon-2026-05-10,gale,E,486,0,500,268,574 +Rsilicon-2026-05-10,gale,E,487,0,500,268,574 +Rsilicon-2026-05-10,gale,E,488,0,500,268,574 +Rsilicon-2026-05-10,gale,E,489,0,500,268,574 +Rsilicon-2026-05-10,gale,E,490,0,500,268,574 +Rsilicon-2026-05-10,gale,E,491,0,500,268,574 +Rsilicon-2026-05-10,gale,E,492,0,500,268,574 +Rsilicon-2026-05-10,gale,E,493,0,500,268,574 +Rsilicon-2026-05-10,gale,E,494,0,500,268,574 +Rsilicon-2026-05-10,gale,E,495,0,500,268,574 +Rsilicon-2026-05-10,gale,E,496,0,500,268,574 +Rsilicon-2026-05-10,gale,E,497,0,500,268,574 +Rsilicon-2026-05-10,gale,E,498,0,500,268,574 +Rsilicon-2026-05-10,gale,E,49# step 1/13 rpm=500 period_us=333 ints=500 count=499 +Rsilicon-2026-05-10,gale,D,step_1,160044873,129,237,22,173,180 +Rsilicon-2026-05-10,gale,H,step_1,0,0,0 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+Rsilicon-2026-05-10,gale,E,7433,10,8000,268,577 +Rsilicon-2026-05-10,gale,E,7434,10,8000,268,574 +Rsilicon-2026-05-10,gale,E,7435,10,8000,268,574 +Rsilicon-2026-05-10,gale,E,7436,10,8000,268,577 +Rsilicon-2026-05-10,gale,E,7437,10,8000,268,574 +Rsilicon-2026-05-10,gale,E,7438,10,8000,268,574 +Rsilicon-2026-05-10,gale,E,7439,10,8000,268,577 +Rsilicon-2026-05-10,gale,E,7440,10,8000,268,577 +Rsilicon-2026-05-10,gale,E,7441,10,8000,268,574 +Rsilicon-2026-05-10,gale,E,7442,10,8000,268,574 +Rsilicon-2026-05-10,gale,E,7443,10,8000,268,577 +Rsilicon-2026-05-10,gale,E,7444,10,8000,268,574 +Rsilicon-2026-05-10,gale,E,7445,10,8000,268,577 +Rsilicon-2026-05-10,gale,E,7446,10,8000,268,577 +Rsilicon-2026-05-10,gale,E,7447,10,8000,268,574 +Rsilicon-2026-05-10,gale,E,7448,10,8000,268,574 +Rsilicon-2026-05-10,gale,E,7449,10,8000,268,577 +Rsilicon-2026-05-10,gale,E,7450,10,8000,268,574 +Rsilicon-2026-05-10,gale,E,7451,10,8000,268,574 +Rsilicon-2026-05-10,gale,E,7452,10,8000,268,577 +Rsilicon-2026-05-10,gale,E,7453,10,8000,268,574 +Rsilicon-2026-05-10,gale,E,7454,10,8000,268,577 +Rsilicon-2026-05-10,gale,E,7455,10,8000,268,577 +Rsilicon-2026-05-10,gale,E,7456,10,8000,268,574 +Rsilicon-2026-05-10,gale,E,7457,10,8000,268,574 +Rsilicon-2026-05-10,gale,E,7458,10,8000,268,577 +Rsilicon-2026-05-10,gale,E,7459,10,8000,268,574 +Rsilicon-2026-05-10,gale,E,7460,10,8000,268,574 +Rsilicon-2026-05-10,gale,E,7461,10,8000,268,577 +Rsilicon-2026-05-10,gale,E,7462,10,8000,268,574 +Rsilicon-2026-05-10,gale,E,7463,10,8000,268,574 +Rsilicon-2026-05-10,gale,E,7464,10,8000,268,577 +Rsilicon-2026-05-10,gale,E,7465,10,8000,268,574 +Rsilicon-2026-05-10,gale,E,7466,10,8000,268,577 +Rsilicon-2026-05-10,gale,E,7467,10,8000,268,577 +Rsilicon-2026-05-10,gale,E,7468,10,8000,268,574 +Rsilicon-2026-05-10,gale,E,7469,10,8000,268,574 +Rsilicon-2026-05-10,gale,E,7470,10,8000,268,577 +Rsilicon-2026-05-10,gale,E,7471,10,8000,268,574 +Rsilicon-2026-05-10,gale,E,7472,10,8000,268,574 +Rsilicon-2026-05-10,gale,E,7473,10,8000,268,577 +Rsilicon-2026-05-10,gale,E,7474,10,8000,268,574 +Rsilicon-2026-05-10,gale,E,7475,10,8000,268,577 +Rsilicon-2026-05-10,gale,E,7476,10,8000,268,577 +Rsilicon-2026-05-10,gale,E,7477,10,8000,268,574 +Rsilicon-2026-05-10,gale,E,7478,10,8000,268,574 +Rsilicon-2026-05-10,gale,E,7479,10,8000,268,577 +Rsilicon-2026-05-10,gale,E,7480,10,8000,268,574 +Rsilicon-2026-05-10,gale,E,7481,10,8000,268,574 +Rsilicon-2026-05-10,gale,E,7482,10,8000,268,577 +Rsilicon-2026-05-10,gale,E,7483,10,8000,268,574 +Rsilicon-2026-05-10,gale,E,7484,10,8000,268,577 +Rsilicon-2026-05-10,gale,E,7485,10,8000,268,577 +Rsilicon-2026-05-10,gale,E,7486,10,8000,268,574 +Rsilicon-2026-05-10,gale,E,7487,10,8000,268,574 +Rsilicon-2026-05-10,gale,E,7488,10,8000,268,577 +Rsilicon-2026-05-10,gale,E,7489,10,8000,268,574 +Rsilicon-2026-05-10,gale,E,7490,10,8000,268,574 +Rsilicon-2026-05-10,gale,E,7491,10,8000,268,577 +Rsilicon-2026-05-10,gale,E,7492,10,8000,268,574 +Rsilicon-2026-05-10,gale,E,7493,10,8000,268,574 +Rsilicon-2026-05-10,gale,E,7494,10,8000,268,577 +Rsilicon-2026-05-10,gale,E,7495,10,8000,268,574 +Rsilicon-2026-05-10,gale,E,7496,10,8000,268,577 +Rsilicon-2026-05-10,gale,E,7497,10,8000,268,577 +Rsilicon-2026-05-10,gale,E,7498,10,8000,268,574 +Rsilicon-2026-05-10,gale,E,7499,10,8000,268,574 +# Rsilicon-2026-05-10 gale: step 11/13 rpm=8000 period_us=20 ints=200 count=7500 +Rsilicon-2026-05-10,gale,D,step_11,2549858989,75,65,133,219,24 +Rsilicon-2026-05-10,gale,H,step_11,0,0,0 +Rsilicon-2026-05-10,gale,E,7500,11,9000,268,1323 +Rsilicon-2026-05-10,gale,E,7501,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7502,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7503,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7504,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7505,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7506,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7507,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7508,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7509,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7510,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7511,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7512,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7513,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7514,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7515,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7516,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7517,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7518,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7519,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7520,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7521,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7522,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7523,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7524,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7525,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7526,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7527,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7528,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7529,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7530,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7531,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7532,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7533,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7534,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7535,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7536,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7537,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7538,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7539,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7540,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7541,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7542,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7543,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7544,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7545,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7546,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7547,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7548,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7549,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7550,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7551,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7552,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7553,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7554,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7555,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7556,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7557,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7558,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7559,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7560,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7561,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7562,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7563,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7564,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7565,11,9000,268,578 +Rsilicon-2026-05-10,gale,E,7566,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7567,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7568,11,9000,268,577 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+Rsilicon-2026-05-10,gale,E,7589,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7590,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7591,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7592,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7593,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7594,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7595,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7596,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7597,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7598,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7599,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7600,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7601,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7602,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7603,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7604,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7605,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7606,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7607,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7608,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7609,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7610,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7611,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7612,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7613,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7614,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7615,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7616,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7617,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7618,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7619,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7620,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7621,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7622,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7623,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7624,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7625,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7626,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7627,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7628,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7629,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7630,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7631,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7632,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7633,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7634,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7635,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7636,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7637,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7638,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7639,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7640,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7641,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7642,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7643,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7644,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7645,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7646,11,9000,268,577 +Rsilicon-2026-05-10,gale,E,7647,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7648,11,9000,268,574 +Rsilicon-2026-05-10,gale,E,7649,11,9000,2# step 12/13 rpm=9000 period_us=18 ints=150 count=7649 +Rsilicon-2026-05-10,gale,D,step_12,2604533504,233,144,238,204,103 +Rsilicon-2026-05-10,gale,H,step_12,0,0,0 +Rsilicon-2026-05-10,gale,E,7650,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7651,12,10000,268,577 +Rsilicon-2026-05-10,gale,E,7652,12,10000,268,577 +Rsilicon-2026-05-10,gale,E,7653,12,10000,268,577 +Rsilicon-2026-05-10,gale,E,7654,12,10000,268,577 +Rsilicon-2026-05-10,gale,E,7655,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7656,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7657,12,10000,268,577 +Rsilicon-2026-05-10,gale,E,7658,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7659,12,10000,268,577 +Rsilicon-2026-05-10,gale,E,7660,12,10000,268,577 +Rsilicon-2026-05-10,gale,E,7661,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7662,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7663,12,10000,268,577 +Rsilicon-2026-05-10,gale,E,7664,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7665,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7666,12,10000,268,577 +Rsilicon-2026-05-10,gale,E,7667,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7668,12,10000,268,577 +Rsilicon-2026-05-10,gale,E,7669,12,10000,268,577 +Rsilicon-2026-05-10,gale,E,7670,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7671,12,10000,268,577 +Rsilicon-2026-05-10,gale,E,7672,12,10000,268,577 +Rsilicon-2026-05-10,gale,E,7673,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7674,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7675,12,10000,268,577 +Rsilicon-2026-05-10,gale,E,7676,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7677,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7678,12,10000,268,577 +Rsilicon-2026-05-10,gale,E,7679,12,10000,268,577 +Rsilicon-2026-05-10,gale,E,7680,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7681,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7682,12,10000,268,577 +Rsilicon-2026-05-10,gale,E,7683,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7684,12,10000,268,577 +Rsilicon-2026-05-10,gale,E,7685,12,10000,268,577 +Rsilicon-2026-05-10,gale,E,7686,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7687,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7688,12,10000,268,577 +Rsilicon-2026-05-10,gale,E,7689,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7690,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7691,12,10000,268,577 +Rsilicon-2026-05-10,gale,E,7692,12,10000,268,577 +Rsilicon-2026-05-10,gale,E,7693,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7694,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7695,12,10000,268,577 +Rsilicon-2026-05-10,gale,E,7696,12,10000,268,577 +Rsilicon-2026-05-10,gale,E,7697,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7698,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7699,12,10000,268,577 +Rsilicon-2026-05-10,gale,E,7700,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7701,12,10000,268,577 +Rsilicon-2026-05-10,gale,E,7702,12,10000,268,577 +Rsilicon-2026-05-10,gale,E,7703,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7704,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7705,12,10000,268,577 +Rsilicon-2026-05-10,gale,E,7706,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7707,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7708,12,10000,268,577 +Rsilicon-2026-05-10,gale,E,7709,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7710,12,10000,268,577 +Rsilicon-2026-05-10,gale,E,7711,12,10000,268,577 +Rsilicon-2026-05-10,gale,E,7712,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7713,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7714,12,10000,268,577 +Rsilicon-2026-05-10,gale,E,7715,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7716,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7717,12,10000,268,577 +Rsilicon-2026-05-10,gale,E,7718,12,10000,268,577 +Rsilicon-2026-05-10,gale,E,7719,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7720,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7721,12,10000,268,577 +Rsilicon-2026-05-10,gale,E,7722,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7723,12,10000,268,577 +Rsilicon-2026-05-10,gale,E,7724,12,10000,268,577 +Rsilicon-2026-05-10,gale,E,7725,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7726,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7727,12,10000,268,577 +Rsilicon-2026-05-10,gale,E,7728,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7729,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7730,12,10000,268,577 +Rsilicon-2026-05-10,gale,E,7731,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7732,12,10000,268,578 +Rsilicon-2026-05-10,gale,E,7733,12,10000,268,577 +Rsilicon-2026-05-10,gale,E,7734,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7735,12,10000,268,577 +Rsilicon-2026-05-10,gale,E,7736,12,10000,268,577 +Rsilicon-2026-05-10,gale,E,7737,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7738,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7739,12,10000,268,577 +Rsilicon-2026-05-10,gale,E,7740,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7741,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7742,12,10000,268,577 +Rsilicon-2026-05-10,gale,E,7743,12,10000,268,577 +Rsilicon-2026-05-10,gale,E,7744,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7745,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7746,12,10000,268,577 +Rsilicon-2026-05-10,gale,E,7747,12,10000,268,574 +Rsilicon-2026-05-10,gale,E,7748,12,10000,268,577 +Rsilicon-2026-05-10,gale,E,7749,12# step 13/13 rpm=10000 period_us=16 ints=100 count=7749 +Rsilicon-2026-05-10,gale,D,step_13,2643019639,48,211,238,90,234 +Rsilicon-2026-05-10,gale,H,step_13,0,0,0 +Rsilicon-2026-05-10,gale,D,end,2644096572,116,237,238,16,77 +Rsilicon-2026-05-10,gale,H,end,0,0,0 +M,Rsilicon-2026-05-10,gale,drops,0 +M,Rsilicon-2026-05-10,gale,samples,7750 +M,Rsilicon-2026-05-10,gale,END diff --git a/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-b48a81ac-gale-noadc-systick/firmware.elf b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-b48a81ac-gale-noadc-systick/firmware.elf new file mode 100755 index 00000000..324e61f8 Binary files /dev/null and b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-b48a81ac-gale-noadc-systick/firmware.elf differ diff --git a/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-b48a81ac-gale-noadc-systick/firmware.elf.sha256 b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-b48a81ac-gale-noadc-systick/firmware.elf.sha256 new file mode 100644 index 00000000..d5d5c442 --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-b48a81ac-gale-noadc-systick/firmware.elf.sha256 @@ -0,0 +1 @@ +ddca994d3a07571ab2eeb195ff92df3716f7ab4a435fa7bda3e5aa396836f5ac firmware.elf diff --git a/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-b48a81ac-gale-noadc-systick/manifest.txt b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-b48a81ac-gale-noadc-systick/manifest.txt new file mode 100644 index 00000000..3e06d93c --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-b48a81ac-gale-noadc-systick/manifest.txt @@ -0,0 +1,23 @@ +# Silicon-anchor manifest +# Produced by manual flash/capture pipeline (LTO + control experiments) +captured_at: 2026-05-10T11:22:21Z +board: nucleo_g474re +variant: gale +adc_enabled: false +dt_overrides: adc1=disabled +tick_source: systick +sweep: long +flash_runner: openocd +gale_sha: b48a81ac69cbcb6c50495d31b603d910f73a85d5 +gale_status: clean +host: Darwin 25.3.0 arm64 +rustc: rustc 1.94.1 (e408947bf 2026-03-25) +zephyr_base: /Volumes/Home/git/pulseengine/zephyr +zephyr_sha: fc4d89c118fc1d0ff0ad31906a4fa4bd252c9ced +sdk_dir: /Volumes/Home/zephyr-sdk/zephyr-sdk-1.0.1 +elf_sha256: ddca994d3a07571ab2eeb195ff92df3716f7ab4a435fa7bda3e5aa396836f5ac +csv_sha256: 0911366b9cb81ce7cdecd2c0a44884e7c0148d96416562273be91bfc2c9de9bd +csv_bytes: 170137 +csv_event_lines: 7336 +serial_port: /dev/cu.usbmodem132203 +capture_timeout_s: 1800 diff --git a/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-b48a81ac-gale-noadc-systick/output.csv b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-b48a81ac-gale-noadc-systick/output.csv new file mode 100644 index 00000000..183d486e --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-b48a81ac-gale-noadc-systick/output.csv @@ -0,0 +1,7381 @@ +8,574 +E,414,0,500,268,574 +E,415,0,500,268,574 +E,416,0,500,268,574 +E,417,0,500,268,574 +E,418,0,500,268,574 +E,419,0,500,268,574 +E,420,0,500,268,574 +E,421,0,500,268,574 +E,422,0,500,268,574 +E,423,0,500,268,574 +E,424,0,500,268,574 +E,425,0,500,268,574 +E,426,0,500,268,574 +E,427,0,500,268,574 +E,428,0,500,268,574 +E,429,0,500,268,574 +E,430,0,500,268,574 +E,431,0,500,268,574 +E,432,0,500,268,574 +E,433,0,500,268,574 +E,434,0,500,268,574 +E,435,0,500,268,574 +E,436,0,500,268,574 +E,437,0,500,268,574 +E,438,0,500,268,574 +E,439,0,500,268,574 +E,440,0,500,268,574 +E,441,0,500,268,574 +E,442,0,500,268,574 +E,443,0,500,268,574 +E,444,0,500,268,574 +E,445,0,500,268,574 +E,446,0,500,268,574 +E,447,0,500,268,574 +E,448,0,500,268,574 +E,449,0,500,268,574 +E,450,0,500,268,574 +E,451,0,500,268,574 +E,452,0,500,268,574 +E,453,0,500,268,574 +E,454,0,500,268,574 +E,455,0,500,268,574 +E,456,0,500,268,574 +E,457,0,500,268,574 +E,458,0,500,268,574 +E,459,0,500,268,574 +E,460,0,500,268,574 +E,461,0,500,268,574 +E,462,0,500,268,574 +E,463,0,500,268,574 +E,464,0,500,268,574 +E,465,0,500,268,574 +E,466,0,500,268,574 +E,467,0,500,268,574 +E,468,0,500,268,574 +E,469,0,500,268,574 +E,470,0,500,268,574 +E,471,0,500,268,574 +E,472,0,500,268,574 +E,473,0,500,268,574 +E,474,0,500,268,574 +E,475,0,500,268,574 +E,476,0,500,268,574 +E,477,0,500,268,574 +E,478,0,500,268,574 +E,479,0,500,268,574 +E,480,0,500,268,574 +E,481,0,500,268,574 +E,482,0,500,268,574 +E,483,0,500,268,574 +E,484,0,500,268,574 +E,485,0,500,268,574 +E,486,0,500,268,574 +E,487,0,500,268,574 +E,488,0,500,268,574 +E,489,0,500,268,574 +E,490,0,500,268,574 +E,491,0,500,268,574 +E,492,0,500,268,574 +E,493,0,500,268,574 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+E,7224,9,7000,268,574 +E,7225,9,7000,268,574 +E,7226,9,7000,268,574 +E,7227,9,7000,268,574 +E,7228,9,7000,268,574 +E,7229,9,7000,268,574 +E,7230,9,7000,268,574 +E,7231,9,7000,268,574 +E,7232,9,7000,268,574 +E,7233,9,7000,268,574 +E,7234,9,7000,268,574 +E,7235,9,7000,268,574 +E,7236,9,7000,268,574 +E,7237,9,7000,268,574 +E,7238,9,7000,268,574 +E,7239,9,7000,268,574 +E,7240,9,7000,268,574 +E,7241,9,7000,268,574 +E,7242,9,7000,268,574 +E,7243,9,7000,268,574 +E,7244,9,7000,268,574 +E,7245,9,7000,268,574 +E,7246,9,7000,268,574 +E,7247,9,7000,268,574 +E,7248,9,7000,268,574 +E,7249,9,7000,268,574 +E,7250,9,7000,268,574 +E,7251,9,7000,268,574 +E,7252,9,7000,268,574 +E,7253,9,7000,268,574 +E,7254,9,7000,268,574 +E,7255,9,7000,268,574 +E,7256,9,7000,268,574 +E,7257,9,7000,268,574 +E,7258,9,7000,268,574 +E,7259,9,7000,268,574 +E,7260,9,7000,268,574 +E,7261,9,7000,268,574 +E,7262,9,7000,268,574 +E,7263,9,7000,268,574 +E,7264,9,7000,268,574 +E,7265,9,7000,268,574 +E,7266,9,7000,268,574 +E,7267,9,7000,268,574 +E,7268,9,7000,268,574 +E,7269,9,7000,268,574 +E,7270,9,7000,268,574 +E,7271,9,7000,268,574 +E,7272,9,7000,268,574 +E,7273,9,7000,268,574 +E,7274,9,7000,268,574 +E,7275,9,7000,268,574 +E,7276,9,7000,268,574 +E,7277,9,7000,268,574 +E,7278,9,7000,268,574 +E,7279,9,7000,268,574 +E,7280,9,7000,268,574 +E,7281,9,7000,268,574 +E,7282,9,7000,268,574 +E,7283,9,7000,268,574 +E,7284,9,7000,268,574 +E,7285,9,7000,268,574 +E,7286,9,7000,268,574 +E,7287,9,7000,268,574 +E,7288,9,7000,268,574 +E,7289,9,7000,268,574 +E,7290,9,7000,268,574 +E,7291,9,7000,268,574 +E,7292,9,7000,268,574 +E,7293,9,7000,268,574 +E,7294,9,7000,268,574 +E,7295,9,7000,268,574 +E,7296,9,7000,268,574 +E,7297,9,7000,268,574 +E,7298,9,7000,268,574 +E,7299,9,7000,268,574 +# step 10/13 rpm=7000 period_us=23 ints=300 count=7300 +D,step_10,2477216956,115,227,232,1,189 +H,step_10,0,0,0 +E,7300,10,8000,268,1323 +E,7301,10,8000,268,574 +E,7302,10,8000,268,577 +E,7303,10,8000,268,577 +E,7304,10,8000,268,574 +E,7305,10,8000,268,578 +E,7306,10,8000,268,577 +E,7307,10,8000,268,574 +E,7308,10,8000,268,577 +E,7309,10,8000,268,577 +E,7310,10,8000,268,574 +E,7311,10,8000,268,574 +E,7312,10,8000,268,577 +E,7313,10,8000,268,574 +E,7314,10,8000,268,574 +E,7315,10,8000,268,577 +E,7316,10,8000,268,577 +E,7317,10,8000,268,574 +E,7318,10,8000,268,574 +E,7319,10,8000,268,577 +E,7320,10,8000,268,574 +E,7321,10,8000,268,577 +E,7322,10,8000,268,577 +E,7323,10,8000,268,574 +E,7324,10,8000,268,574 +E,7325,10,8000,268,577 +E,7326,10,8000,268,574 +E,7327,10,8000,268,574 +E,7328,10,8000,268,577 +E,7329,10,8000,268,577 +E,7330,10,8000,268,574 +E,7331,10,8000,268,574 +E,7332,10,8000,268,577 +E,7333,10,8000,268,574 +E,7334,10,8000,268,577 +E,7335,10,8000,268,577 +E,7336,10,8000,268,574 +E,7337,10,8000,268,574 +E,7338,10,8000,268,577 +E,7339,10,8000,268,574 +E,7340,10,8000,268,574 +E,7341,10,8000,268,577 +E,7342,10,8000,268,577 +E,7343,10,8000,268,574 +E,7344,10,8000,268,574 +E,7345,10,8000,268,577 +E,7346,10,8000,268,577 +E,7347,10,8000,268,574 +E,7348,10,8000,268,574 +E,7349,10,8000,268,577 +E,7350,10,8000,268,574 +E,7351,10,8000,268,577 +E,7352,10,8000,268,577 +E,7353,10,8000,268,574 +E,7354,10,8000,268,574 +E,7355,10,8000,268,577 +E,7356,10,8000,268,574 +E,7357,10,8000,268,574 +E,7358,10,8000,268,577 +E,7359,10,8000,268,574 +E,7360,10,8000,268,577 +E,7361,10,8000,268,577 +E,7362,10,8000,268,574 +E,7363,10,8000,268,574 +E,7364,10,8000,268,577 +E,7365,10,8000,268,574 +E,7366,10,8000,268,574 +E,7367,10,8000,268,577 +E,7368,10,8000,268,574 +E,7369,10,8000,268,578 +E,7370,10,8000,268,577 +E,7371,10,8000,268,574 +E,7372,10,8000,268,577 +E,7373,10,8000,268,577 +E,7374,10,8000,268,574 +E,7375,10,8000,268,574 +E,7376,10,8000,268,577 +E,7377,10,8000,268,574 +E,7378,10,8000,268,574 +E,7379,10,8000,268,577 +E,7380,10,8000,268,577 +E,7381,10,8000,268,574 +E,7382,10,8000,268,574 +E,7383,10,8000,268,577 +E,7384,10,8000,268,577 +E,7385,10,8000,268,574 +E,7386,10,8000,268,574 +E,7387,10,8000,268,577 +E,7388,10,8000,268,577 +E,7389,10,8000,268,574 +E,7390,10,8000,268,577 +E,7391,10,8000,268,577 +E,7392,10,8000,268,574 +E,7393,10,8000,268,574 +E,7394,10,8000,268,577 +E,7395,10,8000,268,574 +E,7396,10,8000,268,574 +E,7397,10,8000,268,577 +E,7398,10,8000,268,574 +E,7399,10,8000,268,574 +E,7400,10,8000,268,577 +E,7401,10,8000,268,577 +E,7402,10,8000,268,574 +E,7403,10,8000,268,577 +E,7404,10,8000,268,577 +E,7405,10,8000,268,574 +E,7406,10,8000,268,574 +E,7407,10,8000,268,577 +E,7408,10,8000,268,574 +E,7409,10,8000,268,574 +E,7410,10,8000,268,577 +E,7411,10,8000,268,574 +E,7412,10,8000,268,574 +E,7413,10,8000,268,577 +E,7414,10,8000,268,577 +E,7415,10,8000,268,574 +E,7416,10,8000,268,574 +E,7417,10,8000,268,577 +E,7418,10,8000,268,577 +E,7419,10,8000,268,574 +E,7420,10,8000,268,577 +E,7421,10,8000,268,577 +E,7422,10,8000,268,574 +E,7423,10,8000,268,574 +E,7424,10,8000,268,577 +E,7425,10,8000,268,574 +E,7426,10,8000,268,574 +E,7427,10,8000,268,577 +E,7428,10,8000,268,574 +E,7429,10,8000,268,574 +E,7430,10,8000,268,577 +E,7431,10,8000,268,574 +E,7432,10,8000,268,577 +E,7433,10,8000,268,577 +E,7434,10,8000,268,574 +E,7435,10,8000,268,574 +E,7436,10,8000,268,577 +E,7437,10,8000,268,574 +E,7438,10,8000,268,574 +E,7439,10,8000,268,577 +E,7440,10,8000,268,577 +E,7441,10,8000,268,574 +E,7442,10,8000,268,574 +E,7443,10,8000,268,577 +E,7444,10,8000,268,574 +E,7445,10,8000,268,577 +E,7446,10,8000,268,577 +E,7447,10,8000,268,574 +E,7448,10,8000,268,574 +E,7449,10,8000,268,577 +E,7450,10,8000,268,574 +E,7451,10,8000,268,574 +E,7452,10,8000,268,577 +E,7453,10,8000,268,574 +E,7454,10,8000,268,577 +E,7455,10,8000,268,577 +E,7456,10,8000,268,574 +E,7457,10,8000,268,574 +E,7458,10,8000,268,577 +E,7459,10,8000,268,574 +E,7460,10,8000,268,574 +E,7461,10,8000,268,577 +E,7462,10,8000,268,574 +E,7463,10,8000,268,574 +E,7464,10,8000,268,577 +E,7465,10,8000,268,574 +E,7466,10,8000,268,577 +E,7467,10,8000,268,577 +E,7468,10,8000,268,574 +E,7469,10,8000,268,574 +E,7470,10,8000,268,577 +E,7471,10,8000,268,574 +E,7472,10,8000,268,574 +E,7473,10,8000,268,577 +E,7474,10,8000,268,574 +E,7475,10,8000,268,577 +E,7476,10,8000,268,577 +E,7477,10,8000,268,574 +E,7478,10,8000,268,574 +E,7479,10,8000,268,577 +E,7480,10,8000,268,574 +E,7481,10,8000,268,574 +E,7482,10,8000,268,577 +E,7483,10,8000,268,574 +E,7484,10,8000,268,577 +E,7485,10,8000,268,577 +E,7486,10,8000,268,574 +E,7487,10,8000,268,574 +E,7488,10,8000,268,577 +E,7489,10,8000,268,574 +E,7490,10,8000,268,574 +E,7491,10,8000,268,577 +E,7492,10,8000,268,574 +E,7493,10,8000,268,574 +E,7494,10,8000,268,577 +E,7495,10,8000,268,574 +E,7496,10,8000,268,577 +E,7497,10,8000,268,577 +E,7498,10,8000,268,574 +E,7499,10,8000,268,574 +# step 11/13 rpm=8000 period_us=20 ints=200 count=7500 +D,step_11,2549858989,75,65,133,219,24 +H,step_11,0,0,0 +E,7500,11,9000,268,1323 +E,7501,11,9000,268,574 +E,7502,11,9000,268,577 +E,7503,11,9000,268,577 +E,7504,11,9000,268,574 +E,7505,11,9000,268,577 +E,7506,11,9000,268,577 +E,7507,11,9000,268,574 +E,7508,11,9000,268,574 +E,7509,11,9000,268,577 +E,7510,11,9000,268,574 +E,7511,11,9000,268,574 +E,7512,11,9000,268,577 +E,7513,11,9000,268,574 +E,7514,11,9000,268,574 +E,7515,11,9000,268,577 +E,7516,11,9000,268,574 +E,7517,11,9000,268,577 +E,7518,11,9000,268,577 +E,7519,11,9000,268,574 +E,7520,11,9000,268,574 +E,7521,11,9000,268,577 +E,7522,11,9000,268,574 +E,7523,11,9000,268,574 +E,7524,11,9000,268,577 +E,7525,11,9000,268,574 +E,7526,11,9000,268,577 +E,7527,11,9000,268,577 +E,7528,11,9000,268,574 +E,7529,11,9000,268,574 +E,7530,11,9000,268,577 +E,7531,11,9000,268,574 +E,7532,11,9000,268,574 +E,7533,11,9000,268,577 +E,7534,11,9000,268,574 +E,7535,11,9000,268,577 +E,7536,11,9000,268,577 +E,7537,11,9000,268,574 +E,7538,11,9000,268,574 +E,7539,11,9000,268,577 +E,7540,11,9000,268,574 +E,7541,11,9000,268,574 +E,7542,11,9000,268,577 +E,7543,11,9000,268,574 +E,7544,11,9000,268,574 +E,7545,11,9000,268,577 +E,7546,11,9000,268,574 +E,7547,11,9000,268,577 +E,7548,11,9000,268,577 +E,7549,11,9000,268,574 +E,7550,11,9000,268,574 +E,7551,11,9000,268,577 +E,7552,11,9000,268,574 +E,7553,11,9000,268,574 +E,7554,11,9000,268,577 +E,7555,11,9000,268,574 +E,7556,11,9000,268,577 +E,7557,11,9000,268,577 +E,7558,11,9000,268,574 +E,7559,11,9000,268,574 +E,7560,11,9000,268,577 +E,7561,11,9000,268,574 +E,7562,11,9000,268,574 +E,7563,11,9000,268,577 +E,7564,11,9000,268,574 +E,7565,11,9000,268,578 +E,7566,11,9000,268,577 +E,7567,11,9000,268,574 +E,7568,11,9000,268,577 +E,7569,11,9000,268,577 +E,7570,11,9000,268,574 +E,7571,11,9000,268,574 +E,7572,11,9000,268,577 +E,7573,11,9000,268,574 +E,7574,11,9000,268,574 +E,7575,11,9000,268,577 +E,7576,11,9000,268,577 +E,7577,11,9000,268,574 +E,7578,11,9000,268,574 +E,7579,11,9000,268,577 +E,7580,11,9000,268,574 +E,7581,11,9000,268,577 +E,7582,11,9000,268,577 +E,7583,11,9000,268,574 +E,7584,11,9000,268,574 +E,7585,11,9000,268,577 +E,7586,11,9000,268,574 +E,7587,11,9000,268,574 +E,7588,11,9000,268,577 +E,7589,11,9000,268,574 +E,7590,11,9000,268,577 +E,7591,11,9000,268,577 +E,7592,11,9000,268,574 +E,7593,11,9000,268,574 +E,7594,11,9000,268,577 +E,7595,11,9000,268,574 +E,7596,11,9000,268,574 +E,7597,11,9000,268,577 +E,7598,11,9000,268,574 +E,7599,11,9000,268,577 +E,7600,11,9000,268,577 +E,7601,11,9000,268,574 +E,7602,11,9000,268,577 +E,7603,11,9000,268,577 +E,7604,11,9000,268,574 +E,7605,11,9000,268,574 +E,7606,11,9000,268,577 +E,7607,11,9000,268,574 +E,7608,11,9000,268,574 +E,7609,11,9000,268,577 +E,7610,11,9000,268,577 +E,7611,11,9000,268,574 +E,7612,11,9000,268,574 +E,7613,11,9000,268,577 +E,7614,11,9000,268,574 +E,7615,11,9000,268,577 +E,7616,11,9000,268,577 +E,7617,11,9000,268,574 +E,7618,11,9000,268,574 +E,7619,11,9000,268,577 +E,7620,11,9000,268,574 +E,7621,11,9000,268,574 +E,7622,11,9000,268,577 +E,7623,11,9000,268,574 +E,7624,11,9000,268,577 +E,7625,11,9000,268,577 +E,7626,11,9000,268,574 +E,7627,11,9000,268,574 +E,7628,11,9000,268,577 +E,7629,11,9000,268,574 +E,7630,11,9000,268,574 +E,7631,11,9000,268,577 +E,7632,11,9000,268,574 +E,7633,11,9000,268,577 +E,7634,11,9000,268,577 +E,7635,11,9000,268,574 +E,7636,11,9000,268,574 +E,7637,11,9000,268,577 +E,7638,11,9000,268,574 +E,7639,11,9000,268,574 +E,7640,11,9000,268,577 +E,7641,11,9000,268,574 +E,7642,11,9000,268,574 +E,7643,11,9000,268,577 +E,7644,11,9000,268,574 +E,7645,11,9000,268,577 +E,7646,11,9000,268,577 +E,7647,11,9000,268,574 +E,7648,11,9000,268,574 +E,7649,11,9000,2# step 12/13 rpm=9000 period_us=18 ints=150 count=7649 +D,step_12,2604533504,233,144,238,204,103 +H,step_12,0,0,0 +68,577 +E,7650,12,10000,268,574 +E,7651,12,10000,268,577 +E,7652,12,10000,268,577 +E,7653,12,10000,268,577 +E,7654,12,10000,268,577 +E,7655,12,10000,268,574 +E,7656,12,10000,268,574 +E,7657,12,10000,268,577 +E,7658,12,10000,268,574 +E,7659,12,10000,268,577 +E,7660,12,10000,268,577 +E,7661,12,10000,268,574 +E,7662,12,10000,268,574 +E,7663,12,10000,268,577 +E,7664,12,10000,268,574 +E,7665,12,10000,268,574 +E,7666,12,10000,268,577 +E,7667,12,10000,268,574 +E,7668,12,10000,268,577 +E,7669,12,10000,268,577 +E,7670,12,10000,268,574 +E,7671,12,10000,268,577 +E,7672,12,10000,268,577 +E,7673,12,10000,268,574 +E,7674,12,10000,268,574 +E,7675,12,10000,268,577 +E,7676,12,10000,268,574 +E,7677,12,10000,268,574 +E,7678,12,10000,268,577 +E,7679,12,10000,268,577 +E,7680,12,10000,268,574 +E,7681,12,10000,268,574 +E,7682,12,10000,268,577 +E,7683,12,10000,268,574 +E,7684,12,10000,268,577 +E,7685,12,10000,268,577 +E,7686,12,10000,268,574 +E,7687,12,10000,268,574 +E,7688,12,10000,268,577 +E,7689,12,10000,268,574 +E,7690,12,10000,268,574 +E,7691,12,10000,268,577 +E,7692,12,10000,268,577 +E,7693,12,10000,268,574 +E,7694,12,10000,268,574 +E,7695,12,10000,268,577 +E,7696,12,10000,268,577 +E,7697,12,10000,268,574 +E,7698,12,10000,268,574 +E,7699,12,10000,268,577 +E,7700,12,10000,268,574 +E,7701,12,10000,268,577 +E,7702,12,10000,268,577 +E,7703,12,10000,268,574 +E,7704,12,10000,268,574 +E,7705,12,10000,268,577 +E,7706,12,10000,268,574 +E,7707,12,10000,268,574 +E,7708,12,10000,268,577 +E,7709,12,10000,268,574 +E,7710,12,10000,268,577 +E,7711,12,10000,268,577 +E,7712,12,10000,268,574 +E,7713,12,10000,268,574 +E,7714,12,10000,268,577 +E,7715,12,10000,268,574 +E,7716,12,10000,268,574 +E,7717,12,10000,268,577 +E,7718,12,10000,268,577 +E,7719,12,10000,268,574 +E,7720,12,10000,268,574 +E,7721,12,10000,268,577 +E,7722,12,10000,268,574 +E,7723,12,10000,268,577 +E,7724,12,10000,268,577 +E,7725,12,10000,268,574 +E,7726,12,10000,268,574 +E,7727,12,10000,268,577 +E,7728,12,10000,268,574 +E,7729,12,10000,268,574 +E,7730,12,10000,268,577 +E,7731,12,10000,268,574 +E,7732,12,10000,268,578 +E,7733,12,10000,268,577 +E,7734,12,10000,268,574 +E,7735,12,10000,268,577 +E,7736,12,10000,268,577 +E,7737,12,10000,268,574 +E,7738,12,10000,268,574 +E,7739,12,10000,268,577 +E,7740,12,10000,268,574 +E,7741,12,10000,268,574 +E,7742,12,10000,268,577 +E,7743,12,10000,268,577 +E,7744,12,10000,268,574 +E,7745,12,10000,268,574 +E,7746,12,10000,268,577 +E,7747,12,10000,268,574 +E,7748,12,10000,268,577 +E,7749,12# step 13/13 rpm=10000 period_us=16 ints=100 count=7749 +D,step_13,2643019639,48,211,238,90,234 +H,step_13,0,0,0 +,10000,268,577 +D,end,2644096572,116,237,238,16,77 +H,end,0,0,0 +drops,0 +samples,7750 +=== END === diff --git a/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-f6f61281-gale-lto-systick/events.csv b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-f6f61281-gale-lto-systick/events.csv new file mode 100644 index 00000000..c027320b --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-f6f61281-gale-lto-systick/events.csv @@ -0,0 +1,7360 @@ +Rsilicon-2026-05-10,gale-lto,E,429,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,430,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,431,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,432,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,433,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,434,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,435,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,436,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,437,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,438,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,439,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,440,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,441,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,442,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,443,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,444,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,445,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,446,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,447,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,448,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,449,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,450,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,451,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,452,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,453,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,454,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,455,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,456,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,457,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,458,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,459,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,460,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,461,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,462,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,463,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,464,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,465,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,466,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,467,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,468,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,469,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,470,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,471,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,472,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,473,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,474,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,475,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,476,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,477,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,478,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,479,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,480,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,481,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,482,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,483,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,484,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,485,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,486,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,487,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,488,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,489,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,490,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,491,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,492,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,493,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,494,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,495,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,496,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,497,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,498,0,500,243,558 +Rsilicon-2026-05-10,gale-lto,E,499# step 1/13 rpm=500 period_us=333 ints=500 count=499 +Rsilicon-2026-05-10,gale-lto,D,step_1,161216984,175,190,218,24,167 +Rsilicon-2026-05-10,gale-lto,H,step_1,214984,26614,0 +Rsilicon-2026-05-10,gale-lto,E,500,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,501,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,502,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,503,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,504,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,505,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,506,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,507,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,508,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,509,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,510,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,511,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,512,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,513,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,514,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,515,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,516,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,517,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,518,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,519,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,520,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,521,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,522,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,523,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,524,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,525,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,526,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,527,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,528,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,529,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,530,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,531,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,532,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,533,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,534,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,535,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,536,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,537,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,538,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,539,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,540,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,541,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,542,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,543,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,544,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,545,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,546,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,547,1,1000,243,558 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+Rsilicon-2026-05-10,gale-lto,E,567,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,568,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,569,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,570,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,571,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,572,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,573,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,574,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,575,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,576,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,577,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,578,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,579,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,580,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,581,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,582,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,583,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,584,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,585,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,586,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,587,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,588,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,589,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,590,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,591,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,592,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,593,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,594,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,595,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,596,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,597,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,598,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,599,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,600,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,601,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,602,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,603,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,604,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,605,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,606,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,607,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,608,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,609,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,610,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,611,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,612,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,613,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,614,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,615,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,616,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,617,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,618,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,619,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,620,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,621,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,622,1,1000,243,558 +Rsilicon-2026-05-10,gale-lto,E,623,1,1000,243,558 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+Rsilicon-2026-05-10,gale-lto,E,7459,10,8000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7460,10,8000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7461,10,8000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7462,10,8000,244,561 +Rsilicon-2026-05-10,gale-lto,E,7463,10,8000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7464,10,8000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7465,10,8000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7466,10,8000,244,558 +Rsilicon-2026-05-10,gale-lto,E,7467,10,8000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7468,10,8000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7469,10,8000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7470,10,8000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7471,10,8000,244,561 +Rsilicon-2026-05-10,gale-lto,E,7472,10,8000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7473,10,8000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7474,10,8000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7475,10,8000,244,558 +Rsilicon-2026-05-10,gale-lto,E,7476,10,8000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7477,10,8000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7478,10,8000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7479,10,8000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7480,10,8000,244,561 +Rsilicon-2026-05-10,gale-lto,E,7481,10,8000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7482,10,8000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7483,10,8000,244,561 +Rsilicon-2026-05-10,gale-lto,E,7484,10,8000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7485,10,8000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7486,10,8000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7487,10,8000,244,558 +Rsilicon-2026-05-10,gale-lto,E,7488,10,8000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7489,10,8000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7490,10,8000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7491,10,8000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7492,10,8000,244,561 +Rsilicon-2026-05-10,gale-lto,E,7493,10,8000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7494,10,8000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7495,10,8000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7496,10,8000,244,558 +Rsilicon-2026-05-10,gale-lto,E,7497,10,8000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7498,10,8000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7499,10,8000,241,558 +# Rsilicon-2026-05-10 gale-lto: step 11/13 rpm=8000 period_us=20 ints=200 count=7500 +Rsilicon-2026-05-10,gale-lto,D,step_11,2552390321,175,70,25,67,113 +Rsilicon-2026-05-10,gale-lto,H,step_11,177447,26614,0 +Rsilicon-2026-05-10,gale-lto,E,7500,11,9000,244,558 +Rsilicon-2026-05-10,gale-lto,E,7501,11,9000,244,561 +Rsilicon-2026-05-10,gale-lto,E,7502,11,9000,244,561 +Rsilicon-2026-05-10,gale-lto,E,7503,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7504,11,9000,244,558 +Rsilicon-2026-05-10,gale-lto,E,7505,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7506,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7507,11,9000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7508,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7509,11,9000,244,561 +Rsilicon-2026-05-10,gale-lto,E,7510,11,9000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7511,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7512,11,9000,244,561 +Rsilicon-2026-05-10,gale-lto,E,7513,11,9000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7514,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7515,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7516,11,9000,244,558 +Rsilicon-2026-05-10,gale-lto,E,7517,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7518,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7519,11,9000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7520,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7521,11,9000,244,561 +Rsilicon-2026-05-10,gale-lto,E,7522,11,9000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7523,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7524,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7525,11,9000,244,558 +Rsilicon-2026-05-10,gale-lto,E,7526,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7527,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7528,11,9000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7529,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7530,11,9000,244,561 +Rsilicon-2026-05-10,gale-lto,E,7531,11,9000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7532,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7533,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7534,11,9000,244,558 +Rsilicon-2026-05-10,gale-lto,E,7535,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7536,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7537,11,9000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7538,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7539,11,9000,244,561 +Rsilicon-2026-05-10,gale-lto,E,7540,11,9000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7541,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7542,11,9000,244,561 +Rsilicon-2026-05-10,gale-lto,E,7543,11,9000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7544,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7545,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7546,11,9000,244,558 +Rsilicon-2026-05-10,gale-lto,E,7547,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7548,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7549,11,9000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7550,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7551,11,9000,244,561 +Rsilicon-2026-05-10,gale-lto,E,7552,11,9000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7553,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7554,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7555,11,9000,244,558 +Rsilicon-2026-05-10,gale-lto,E,7556,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7557,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7558,11,9000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7559,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7560,11,9000,244,561 +Rsilicon-2026-05-10,gale-lto,E,7561,11,9000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7562,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7563,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7564,11,9000,244,558 +Rsilicon-2026-05-10,gale-lto,E,7565,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7566,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7567,11,9000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7568,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7569,11,9000,244,561 +Rsilicon-2026-05-10,gale-lto,E,7570,11,9000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7571,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7572,11,9000,244,561 +Rsilicon-2026-05-10,gale-lto,E,7573,11,9000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7574,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7575,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7576,11,9000,244,558 +Rsilicon-2026-05-10,gale-lto,E,7577,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7578,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7579,11,9000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7580,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7581,11,9000,244,561 +Rsilicon-2026-05-10,gale-lto,E,7582,11,9000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7583,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7584,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7585,11,9000,244,558 +Rsilicon-2026-05-10,gale-lto,E,7586,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7587,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7588,11,9000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7589,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7590,11,9000,244,561 +Rsilicon-2026-05-10,gale-lto,E,7591,11,9000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7592,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7593,11,9000,244,561 +Rsilicon-2026-05-10,gale-lto,E,7594,11,9000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7595,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7596,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7597,11,9000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7598,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7599,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7600,11,9000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7601,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7602,11,9000,244,561 +Rsilicon-2026-05-10,gale-lto,E,7603,11,9000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7604,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7605,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7606,11,9000,244,558 +Rsilicon-2026-05-10,gale-lto,E,7607,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7608,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7609,11,9000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7610,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7611,11,9000,244,561 +Rsilicon-2026-05-10,gale-lto,E,7612,11,9000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7613,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7614,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7615,11,9000,244,558 +Rsilicon-2026-05-10,gale-lto,E,7616,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7617,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7618,11,9000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7619,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7620,11,9000,244,561 +Rsilicon-2026-05-10,gale-lto,E,7621,11,9000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7622,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7623,11,9000,244,561 +Rsilicon-2026-05-10,gale-lto,E,7624,11,9000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7625,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7626,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7627,11,9000,244,558 +Rsilicon-2026-05-10,gale-lto,E,7628,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7629,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7630,11,9000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7631,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7632,11,9000,244,561 +Rsilicon-2026-05-10,gale-lto,E,7633,11,9000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7634,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7635,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7636,11,9000,244,558 +Rsilicon-2026-05-10,gale-lto,E,7637,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7638,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7639,11,9000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7640,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7641,11,9000,244,561 +Rsilicon-2026-05-10,gale-lto,E,7642,11,9000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7643,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7644,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7645,11,9000,244,558 +Rsilicon-2026-05-10,gale-lto,E,7646,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7647,11,9000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7648,11,9000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7649,11,9000,24# step 12/13 rpm=9000 period_us=18 ints=150 count=7649 +Rsilicon-2026-05-10,gale-lto,D,step_12,2607197645,93,166,25,92,21 +Rsilicon-2026-05-10,gale-lto,H,step_12,162732,27346,0 +Rsilicon-2026-05-10,gale-lto,E,7650,12,10000,244,558 +Rsilicon-2026-05-10,gale-lto,E,7651,12,10000,244,561 +Rsilicon-2026-05-10,gale-lto,E,7652,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7653,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7654,12,10000,244,558 +Rsilicon-2026-05-10,gale-lto,E,7655,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7656,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7657,12,10000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7658,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7659,12,10000,244,561 +Rsilicon-2026-05-10,gale-lto,E,7660,12,10000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7661,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7662,12,10000,244,561 +Rsilicon-2026-05-10,gale-lto,E,7663,12,10000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7664,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7665,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7666,12,10000,244,558 +Rsilicon-2026-05-10,gale-lto,E,7667,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7668,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7669,12,10000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7670,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7671,12,10000,244,561 +Rsilicon-2026-05-10,gale-lto,E,7672,12,10000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7673,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7674,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7675,12,10000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7676,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7677,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7678,12,10000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7679,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7680,12,10000,244,561 +Rsilicon-2026-05-10,gale-lto,E,7681,12,10000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7682,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7683,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7684,12,10000,244,558 +Rsilicon-2026-05-10,gale-lto,E,7685,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7686,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7687,12,10000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7688,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7689,12,10000,244,561 +Rsilicon-2026-05-10,gale-lto,E,7690,12,10000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7691,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7692,12,10000,244,561 +Rsilicon-2026-05-10,gale-lto,E,7693,12,10000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7694,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7695,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7696,12,10000,244,558 +Rsilicon-2026-05-10,gale-lto,E,7697,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7698,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7699,12,10000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7700,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7701,12,10000,244,561 +Rsilicon-2026-05-10,gale-lto,E,7702,12,10000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7703,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7704,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7705,12,10000,244,558 +Rsilicon-2026-05-10,gale-lto,E,7706,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7707,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7708,12,10000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7709,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7710,12,10000,244,561 +Rsilicon-2026-05-10,gale-lto,E,7711,12,10000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7712,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7713,12,10000,244,561 +Rsilicon-2026-05-10,gale-lto,E,7714,12,10000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7715,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7716,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7717,12,10000,244,558 +Rsilicon-2026-05-10,gale-lto,E,7718,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7719,12,10000,244,561 +Rsilicon-2026-05-10,gale-lto,E,7720,12,10000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7721,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7722,12,10000,244,561 +Rsilicon-2026-05-10,gale-lto,E,7723,12,10000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7724,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7725,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7726,12,10000,244,558 +Rsilicon-2026-05-10,gale-lto,E,7727,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7728,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7729,12,10000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7730,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7731,12,10000,244,561 +Rsilicon-2026-05-10,gale-lto,E,7732,12,10000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7733,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7734,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7735,12,10000,244,558 +Rsilicon-2026-05-10,gale-lto,E,7736,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7737,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7738,12,10000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7739,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7740,12,10000,244,561 +Rsilicon-2026-05-10,gale-lto,E,7741,12,10000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7742,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7743,12,10000,244,561 +Rsilicon-2026-05-10,gale-lto,E,7744,12,10000,241,558 +Rsilicon-2026-05-10,gale-lto,E,7745,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7746,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7747,12,10000,244,558 +Rsilicon-2026-05-10,gale-lto,E,7748,12,10000,241,561 +Rsilicon-2026-05-10,gale-lto,E,7749,12,# step 13/13 rpm=10000 period_us=16 ints=100 count=7749 +Rsilicon-2026-05-10,gale-lto,D,step_13,2645757560,51,151,25,18,143 +Rsilicon-2026-05-10,gale-lto,H,step_13,133603,27960,0 +Rsilicon-2026-05-10,gale-lto,D,end,2646937830,84,68,25,95,114 +Rsilicon-2026-05-10,gale-lto,H,end,29700,28440,0 +M,Rsilicon-2026-05-10,gale-lto,drops,0 +M,Rsilicon-2026-05-10,gale-lto,samples,7750 +M,Rsilicon-2026-05-10,gale-lto,END diff --git a/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-f6f61281-gale-lto-systick/firmware.elf b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-f6f61281-gale-lto-systick/firmware.elf new file mode 100755 index 00000000..4e3f74d7 Binary files /dev/null and b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-f6f61281-gale-lto-systick/firmware.elf differ diff --git a/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-f6f61281-gale-lto-systick/firmware.elf.sha256 b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-f6f61281-gale-lto-systick/firmware.elf.sha256 new file mode 100644 index 00000000..5d64de3c --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-f6f61281-gale-lto-systick/firmware.elf.sha256 @@ -0,0 +1 @@ +93eadb36a246706b867ebfff74c439640c5de7e28e58e39f9b0720e679e109c0 firmware.elf diff --git a/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-f6f61281-gale-lto-systick/manifest.txt b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-f6f61281-gale-lto-systick/manifest.txt new file mode 100644 index 00000000..7046faa1 --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-f6f61281-gale-lto-systick/manifest.txt @@ -0,0 +1,22 @@ +# Silicon-anchor manifest +# LTO build with ADC=y, ISR_TABLES_LOCAL_DECLARATION dropped (the fix) +captured_at: 2026-05-10T12:22:09Z +board: nucleo_g474re +variant: gale-lto +adc_enabled: true +lto_overlay_modified: CONFIG_ISR_TABLES_LOCAL_DECLARATION removed (was the boot-crash trigger) +tick_source: systick +sweep: long +flash_runner: openocd +gale_sha: f6f6128148d12e33603a5bf2b386a0a569e0c234 +host: Darwin 25.3.0 arm64 +clang: Homebrew clang version 21.1.8 +lld: Homebrew LLD 21.1.8 (compatible with GNU linkers) +rustc: rustc 1.94.1 (e408947bf 2026-03-25) +zephyr_sha: fc4d89c118fc1d0ff0ad31906a4fa4bd252c9ced +sdk_dir: /Volumes/Home/zephyr-sdk/zephyr-sdk-1.0.1 +elf_sha256: 93eadb36a246706b867ebfff74c439640c5de7e28e58e39f9b0720e679e109c0 +csv_sha256: 52e5babfcdd81c5eab4ef9edb2254a23cc69561c956c9ed12f471441a4791931 +csv_bytes: 169963 +csv_event_lines: 7321 +serial_port: /dev/cu.usbmodem132203 diff --git a/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-f6f61281-gale-lto-systick/output.csv b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-f6f61281-gale-lto-systick/output.csv new file mode 100644 index 00000000..eb4f2e4d --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-05-10-nucleo_g474re-f6f61281-gale-lto-systick/output.csv @@ -0,0 +1,7366 @@ +,428,0,500,243,558 +E,429,0,500,243,558 +E,430,0,500,243,558 +E,431,0,500,243,558 +E,432,0,500,243,558 +E,433,0,500,243,558 +E,434,0,500,243,558 +E,435,0,500,243,558 +E,436,0,500,243,558 +E,437,0,500,243,558 +E,438,0,500,243,558 +E,439,0,500,243,558 +E,440,0,500,243,558 +E,441,0,500,243,558 +E,442,0,500,243,558 +E,443,0,500,243,558 +E,444,0,500,243,558 +E,445,0,500,243,558 +E,446,0,500,243,558 +E,447,0,500,243,558 +E,448,0,500,243,558 +E,449,0,500,243,558 +E,450,0,500,243,558 +E,451,0,500,243,558 +E,452,0,500,243,558 +E,453,0,500,243,558 +E,454,0,500,243,558 +E,455,0,500,243,558 +E,456,0,500,243,558 +E,457,0,500,243,558 +E,458,0,500,243,558 +E,459,0,500,243,558 +E,460,0,500,243,558 +E,461,0,500,243,558 +E,462,0,500,243,558 +E,463,0,500,243,558 +E,464,0,500,243,558 +E,465,0,500,243,558 +E,466,0,500,243,558 +E,467,0,500,243,558 +E,468,0,500,243,558 +E,469,0,500,243,558 +E,470,0,500,243,558 +E,471,0,500,243,558 +E,472,0,500,243,558 +E,473,0,500,243,558 +E,474,0,500,243,558 +E,475,0,500,243,558 +E,476,0,500,243,558 +E,477,0,500,243,558 +E,478,0,500,243,558 +E,479,0,500,243,558 +E,480,0,500,243,558 +E,481,0,500,243,558 +E,482,0,500,243,558 +E,483,0,500,243,558 +E,484,0,500,243,558 +E,485,0,500,243,558 +E,486,0,500,243,558 +E,487,0,500,243,558 +E,488,0,500,243,558 +E,489,0,500,243,558 +E,490,0,500,243,558 +E,491,0,500,243,558 +E,492,0,500,243,558 +E,493,0,500,243,558 +E,494,0,500,243,558 +E,495,0,500,243,558 +E,496,0,500,243,558 +E,497,0,500,243,558 +E,498,0,500,243,558 +E,499# step 1/13 rpm=500 period_us=333 ints=500 count=499 +D,step_1,161216984,175,190,218,24,167 +H,step_1,214984,26614,0 +,0,500,243,558 +E,500,1,1000,243,558 +E,501,1,1000,243,558 +E,502,1,1000,243,558 +E,503,1,1000,243,558 +E,504,1,1000,243,558 +E,505,1,1000,243,558 +E,506,1,1000,243,558 +E,507,1,1000,243,558 +E,508,1,1000,243,558 +E,509,1,1000,243,558 +E,510,1,1000,243,558 +E,511,1,1000,243,558 +E,512,1,1000,243,558 +E,513,1,1000,243,558 +E,514,1,1000,243,558 +E,515,1,1000,243,558 +E,516,1,1000,243,558 +E,517,1,1000,243,558 +E,518,1,1000,243,558 +E,519,1,1000,243,558 +E,520,1,1000,243,558 +E,521,1,1000,243,558 +E,522,1,1000,243,558 +E,523,1,1000,243,558 +E,524,1,1000,243,558 +E,525,1,1000,243,558 +E,526,1,1000,243,558 +E,527,1,1000,243,558 +E,528,1,1000,243,558 +E,529,1,1000,243,558 +E,530,1,1000,243,558 +E,531,1,1000,243,558 +E,532,1,1000,243,558 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+E,7265,9,7000,241,558 +E,7266,9,7000,241,558 +E,7267,9,7000,244,558 +E,7268,9,7000,241,558 +E,7269,9,7000,244,558 +E,7270,9,7000,241,558 +E,7271,9,7000,241,558 +E,7272,9,7000,244,558 +E,7273,9,7000,241,558 +E,7274,9,7000,241,558 +E,7275,9,7000,244,558 +E,7276,9,7000,241,558 +E,7277,9,7000,241,558 +E,7278,9,7000,244,558 +E,7279,9,7000,241,558 +E,7280,9,7000,241,558 +E,7281,9,7000,244,558 +E,7282,9,7000,241,558 +E,7283,9,7000,241,558 +E,7284,9,7000,244,558 +E,7285,9,7000,241,558 +E,7286,9,7000,241,558 +E,7287,9,7000,244,558 +E,7288,9,7000,241,558 +E,7289,9,7000,241,558 +E,7290,9,7000,244,558 +E,7291,9,7000,241,558 +E,7292,9,7000,244,558 +E,7293,9,7000,244,558 +E,7294,9,7000,241,558 +E,7295,9,7000,244,558 +E,7296,9,7000,241,558 +E,7297,9,7000,241,558 +E,7298,9,7000,244,558 +E,7299,9,7000,241,5# step 10/13 rpm=7000 period_us=23 ints=300 count=7299 +D,step_10,2479606342,133,217,25,151,211 +H,step_10,209279,27650,0 +58 +E,7300,10,8000,244,558 +E,7301,10,8000,244,561 +E,7302,10,8000,241,561 +E,7303,10,8000,241,561 +E,7304,10,8000,244,558 +E,7305,10,8000,241,561 +E,7306,10,8000,241,561 +E,7307,10,8000,241,558 +E,7308,10,8000,241,561 +E,7309,10,8000,244,561 +E,7310,10,8000,241,558 +E,7311,10,8000,241,561 +E,7312,10,8000,241,561 +E,7313,10,8000,241,558 +E,7314,10,8000,241,561 +E,7315,10,8000,241,561 +E,7316,10,8000,244,558 +E,7317,10,8000,241,561 +E,7318,10,8000,241,561 +E,7319,10,8000,241,558 +E,7320,10,8000,241,561 +E,7321,10,8000,244,561 +E,7322,10,8000,241,558 +E,7323,10,8000,241,561 +E,7324,10,8000,241,561 +E,7325,10,8000,244,558 +E,7326,10,8000,241,561 +E,7327,10,8000,241,561 +E,7328,10,8000,241,558 +E,7329,10,8000,241,561 +E,7330,10,8000,244,561 +E,7331,10,8000,241,558 +E,7332,10,8000,241,561 +E,7333,10,8000,241,561 +E,7334,10,8000,244,558 +E,7335,10,8000,241,561 +E,7336,10,8000,241,561 +E,7337,10,8000,241,558 +E,7338,10,8000,241,561 +E,7339,10,8000,244,561 +E,7340,10,8000,241,558 +E,7341,10,8000,241,561 +E,7342,10,8000,244,561 +E,7343,10,8000,241,558 +E,7344,10,8000,241,561 +E,7345,10,8000,241,561 +E,7346,10,8000,244,558 +E,7347,10,8000,241,561 +E,7348,10,8000,241,561 +E,7349,10,8000,241,558 +E,7350,10,8000,241,561 +E,7351,10,8000,244,561 +E,7352,10,8000,241,558 +E,7353,10,8000,241,561 +E,7354,10,8000,241,561 +E,7355,10,8000,244,558 +E,7356,10,8000,241,561 +E,7357,10,8000,241,561 +E,7358,10,8000,241,558 +E,7359,10,8000,241,561 +E,7360,10,8000,244,561 +E,7361,10,8000,241,558 +E,7362,10,8000,241,561 +E,7363,10,8000,244,561 +E,7364,10,8000,241,558 +E,7365,10,8000,241,561 +E,7366,10,8000,241,561 +E,7367,10,8000,244,558 +E,7368,10,8000,241,561 +E,7369,10,8000,244,561 +E,7370,10,8000,241,558 +E,7371,10,8000,241,561 +E,7372,10,8000,244,561 +E,7373,10,8000,241,558 +E,7374,10,8000,241,561 +E,7375,10,8000,241,561 +E,7376,10,8000,244,558 +E,7377,10,8000,241,561 +E,7378,10,8000,241,561 +E,7379,10,8000,241,558 +E,7380,10,8000,241,561 +E,7381,10,8000,244,561 +E,7382,10,8000,241,558 +E,7383,10,8000,241,561 +E,7384,10,8000,241,561 +E,7385,10,8000,244,558 +E,7386,10,8000,241,561 +E,7387,10,8000,241,561 +E,7388,10,8000,241,558 +E,7389,10,8000,241,561 +E,7390,10,8000,244,561 +E,7391,10,8000,241,558 +E,7392,10,8000,241,561 +E,7393,10,8000,244,561 +E,7394,10,8000,241,558 +E,7395,10,8000,241,561 +E,7396,10,8000,241,561 +E,7397,10,8000,244,558 +E,7398,10,8000,241,561 +E,7399,10,8000,244,561 +E,7400,10,8000,241,558 +E,7401,10,8000,241,561 +E,7402,10,8000,244,561 +E,7403,10,8000,241,558 +E,7404,10,8000,241,561 +E,7405,10,8000,241,561 +E,7406,10,8000,244,558 +E,7407,10,8000,241,561 +E,7408,10,8000,241,561 +E,7409,10,8000,241,558 +E,7410,10,8000,241,561 +E,7411,10,8000,244,561 +E,7412,10,8000,241,558 +E,7413,10,8000,241,561 +E,7414,10,8000,241,561 +E,7415,10,8000,241,558 +E,7416,10,8000,241,561 +E,7417,10,8000,241,561 +E,7418,10,8000,241,558 +E,7419,10,8000,241,561 +E,7420,10,8000,244,561 +E,7421,10,8000,241,558 +E,7422,10,8000,241,561 +E,7423,10,8000,244,561 +E,7424,10,8000,241,558 +E,7425,10,8000,241,561 +E,7426,10,8000,241,561 +E,7427,10,8000,244,558 +E,7428,10,8000,241,561 +E,7429,10,8000,241,561 +E,7430,10,8000,241,558 +E,7431,10,8000,241,561 +E,7432,10,8000,244,561 +E,7433,10,8000,241,558 +E,7434,10,8000,241,561 +E,7435,10,8000,241,561 +E,7436,10,8000,244,558 +E,7437,10,8000,241,561 +E,7438,10,8000,241,561 +E,7439,10,8000,241,558 +E,7440,10,8000,241,561 +E,7441,10,8000,244,561 +E,7442,10,8000,241,558 +E,7443,10,8000,241,561 +E,7444,10,8000,241,561 +E,7445,10,8000,244,558 +E,7446,10,8000,241,561 +E,7447,10,8000,241,561 +E,7448,10,8000,241,558 +E,7449,10,8000,241,561 +E,7450,10,8000,244,561 +E,7451,10,8000,241,558 +E,7452,10,8000,241,561 +E,7453,10,8000,244,561 +E,7454,10,8000,241,558 +E,7455,10,8000,241,561 +E,7456,10,8000,241,561 +E,7457,10,8000,244,558 +E,7458,10,8000,241,561 +E,7459,10,8000,241,561 +E,7460,10,8000,241,558 +E,7461,10,8000,241,561 +E,7462,10,8000,244,561 +E,7463,10,8000,241,558 +E,7464,10,8000,241,561 +E,7465,10,8000,241,561 +E,7466,10,8000,244,558 +E,7467,10,8000,241,561 +E,7468,10,8000,241,561 +E,7469,10,8000,241,558 +E,7470,10,8000,241,561 +E,7471,10,8000,244,561 +E,7472,10,8000,241,558 +E,7473,10,8000,241,561 +E,7474,10,8000,241,561 +E,7475,10,8000,244,558 +E,7476,10,8000,241,561 +E,7477,10,8000,241,561 +E,7478,10,8000,241,558 +E,7479,10,8000,241,561 +E,7480,10,8000,244,561 +E,7481,10,8000,241,558 +E,7482,10,8000,241,561 +E,7483,10,8000,244,561 +E,7484,10,8000,241,558 +E,7485,10,8000,241,561 +E,7486,10,8000,241,561 +E,7487,10,8000,244,558 +E,7488,10,8000,241,561 +E,7489,10,8000,241,561 +E,7490,10,8000,241,558 +E,7491,10,8000,241,561 +E,7492,10,8000,244,561 +E,7493,10,8000,241,558 +E,7494,10,8000,241,561 +E,7495,10,8000,241,561 +E,7496,10,8000,244,558 +E,7497,10,8000,241,561 +E,7498,10,8000,241,561 +E,7499,10,8000,241,558 +# step 11/13 rpm=8000 period_us=20 ints=200 count=7500 +D,step_11,2552390321,175,70,25,67,113 +H,step_11,177447,26614,0 +E,7500,11,9000,244,558 +E,7501,11,9000,244,561 +E,7502,11,9000,244,561 +E,7503,11,9000,241,561 +E,7504,11,9000,244,558 +E,7505,11,9000,241,561 +E,7506,11,9000,241,561 +E,7507,11,9000,241,558 +E,7508,11,9000,241,561 +E,7509,11,9000,244,561 +E,7510,11,9000,241,558 +E,7511,11,9000,241,561 +E,7512,11,9000,244,561 +E,7513,11,9000,241,558 +E,7514,11,9000,241,561 +E,7515,11,9000,241,561 +E,7516,11,9000,244,558 +E,7517,11,9000,241,561 +E,7518,11,9000,241,561 +E,7519,11,9000,241,558 +E,7520,11,9000,241,561 +E,7521,11,9000,244,561 +E,7522,11,9000,241,558 +E,7523,11,9000,241,561 +E,7524,11,9000,241,561 +E,7525,11,9000,244,558 +E,7526,11,9000,241,561 +E,7527,11,9000,241,561 +E,7528,11,9000,241,558 +E,7529,11,9000,241,561 +E,7530,11,9000,244,561 +E,7531,11,9000,241,558 +E,7532,11,9000,241,561 +E,7533,11,9000,241,561 +E,7534,11,9000,244,558 +E,7535,11,9000,241,561 +E,7536,11,9000,241,561 +E,7537,11,9000,241,558 +E,7538,11,9000,241,561 +E,7539,11,9000,244,561 +E,7540,11,9000,241,558 +E,7541,11,9000,241,561 +E,7542,11,9000,244,561 +E,7543,11,9000,241,558 +E,7544,11,9000,241,561 +E,7545,11,9000,241,561 +E,7546,11,9000,244,558 +E,7547,11,9000,241,561 +E,7548,11,9000,241,561 +E,7549,11,9000,241,558 +E,7550,11,9000,241,561 +E,7551,11,9000,244,561 +E,7552,11,9000,241,558 +E,7553,11,9000,241,561 +E,7554,11,9000,241,561 +E,7555,11,9000,244,558 +E,7556,11,9000,241,561 +E,7557,11,9000,241,561 +E,7558,11,9000,241,558 +E,7559,11,9000,241,561 +E,7560,11,9000,244,561 +E,7561,11,9000,241,558 +E,7562,11,9000,241,561 +E,7563,11,9000,241,561 +E,7564,11,9000,244,558 +E,7565,11,9000,241,561 +E,7566,11,9000,241,561 +E,7567,11,9000,241,558 +E,7568,11,9000,241,561 +E,7569,11,9000,244,561 +E,7570,11,9000,241,558 +E,7571,11,9000,241,561 +E,7572,11,9000,244,561 +E,7573,11,9000,241,558 +E,7574,11,9000,241,561 +E,7575,11,9000,241,561 +E,7576,11,9000,244,558 +E,7577,11,9000,241,561 +E,7578,11,9000,241,561 +E,7579,11,9000,241,558 +E,7580,11,9000,241,561 +E,7581,11,9000,244,561 +E,7582,11,9000,241,558 +E,7583,11,9000,241,561 +E,7584,11,9000,241,561 +E,7585,11,9000,244,558 +E,7586,11,9000,241,561 +E,7587,11,9000,241,561 +E,7588,11,9000,241,558 +E,7589,11,9000,241,561 +E,7590,11,9000,244,561 +E,7591,11,9000,241,558 +E,7592,11,9000,241,561 +E,7593,11,9000,244,561 +E,7594,11,9000,241,558 +E,7595,11,9000,241,561 +E,7596,11,9000,241,561 +E,7597,11,9000,241,558 +E,7598,11,9000,241,561 +E,7599,11,9000,241,561 +E,7600,11,9000,241,558 +E,7601,11,9000,241,561 +E,7602,11,9000,244,561 +E,7603,11,9000,241,558 +E,7604,11,9000,241,561 +E,7605,11,9000,241,561 +E,7606,11,9000,244,558 +E,7607,11,9000,241,561 +E,7608,11,9000,241,561 +E,7609,11,9000,241,558 +E,7610,11,9000,241,561 +E,7611,11,9000,244,561 +E,7612,11,9000,241,558 +E,7613,11,9000,241,561 +E,7614,11,9000,241,561 +E,7615,11,9000,244,558 +E,7616,11,9000,241,561 +E,7617,11,9000,241,561 +E,7618,11,9000,241,558 +E,7619,11,9000,241,561 +E,7620,11,9000,244,561 +E,7621,11,9000,241,558 +E,7622,11,9000,241,561 +E,7623,11,9000,244,561 +E,7624,11,9000,241,558 +E,7625,11,9000,241,561 +E,7626,11,9000,241,561 +E,7627,11,9000,244,558 +E,7628,11,9000,241,561 +E,7629,11,9000,241,561 +E,7630,11,9000,241,558 +E,7631,11,9000,241,561 +E,7632,11,9000,244,561 +E,7633,11,9000,241,558 +E,7634,11,9000,241,561 +E,7635,11,9000,241,561 +E,7636,11,9000,244,558 +E,7637,11,9000,241,561 +E,7638,11,9000,241,561 +E,7639,11,9000,241,558 +E,7640,11,9000,241,561 +E,7641,11,9000,244,561 +E,7642,11,9000,241,558 +E,7643,11,9000,241,561 +E,7644,11,9000,241,561 +E,7645,11,9000,244,558 +E,7646,11,9000,241,561 +E,7647,11,9000,241,561 +E,7648,11,9000,241,558 +E,7649,11,9000,24# step 12/13 rpm=9000 period_us=18 ints=150 count=7649 +D,step_12,2607197645,93,166,25,92,21 +H,step_12,162732,27346,0 +1,561 +E,7650,12,10000,244,558 +E,7651,12,10000,244,561 +E,7652,12,10000,241,561 +E,7653,12,10000,241,561 +E,7654,12,10000,244,558 +E,7655,12,10000,241,561 +E,7656,12,10000,241,561 +E,7657,12,10000,241,558 +E,7658,12,10000,241,561 +E,7659,12,10000,244,561 +E,7660,12,10000,241,558 +E,7661,12,10000,241,561 +E,7662,12,10000,244,561 +E,7663,12,10000,241,558 +E,7664,12,10000,241,561 +E,7665,12,10000,241,561 +E,7666,12,10000,244,558 +E,7667,12,10000,241,561 +E,7668,12,10000,241,561 +E,7669,12,10000,241,558 +E,7670,12,10000,241,561 +E,7671,12,10000,244,561 +E,7672,12,10000,241,558 +E,7673,12,10000,241,561 +E,7674,12,10000,241,561 +E,7675,12,10000,241,558 +E,7676,12,10000,241,561 +E,7677,12,10000,241,561 +E,7678,12,10000,241,558 +E,7679,12,10000,241,561 +E,7680,12,10000,244,561 +E,7681,12,10000,241,558 +E,7682,12,10000,241,561 +E,7683,12,10000,241,561 +E,7684,12,10000,244,558 +E,7685,12,10000,241,561 +E,7686,12,10000,241,561 +E,7687,12,10000,241,558 +E,7688,12,10000,241,561 +E,7689,12,10000,244,561 +E,7690,12,10000,241,558 +E,7691,12,10000,241,561 +E,7692,12,10000,244,561 +E,7693,12,10000,241,558 +E,7694,12,10000,241,561 +E,7695,12,10000,241,561 +E,7696,12,10000,244,558 +E,7697,12,10000,241,561 +E,7698,12,10000,241,561 +E,7699,12,10000,241,558 +E,7700,12,10000,241,561 +E,7701,12,10000,244,561 +E,7702,12,10000,241,558 +E,7703,12,10000,241,561 +E,7704,12,10000,241,561 +E,7705,12,10000,244,558 +E,7706,12,10000,241,561 +E,7707,12,10000,241,561 +E,7708,12,10000,241,558 +E,7709,12,10000,241,561 +E,7710,12,10000,244,561 +E,7711,12,10000,241,558 +E,7712,12,10000,241,561 +E,7713,12,10000,244,561 +E,7714,12,10000,241,558 +E,7715,12,10000,241,561 +E,7716,12,10000,241,561 +E,7717,12,10000,244,558 +E,7718,12,10000,241,561 +E,7719,12,10000,244,561 +E,7720,12,10000,241,558 +E,7721,12,10000,241,561 +E,7722,12,10000,244,561 +E,7723,12,10000,241,558 +E,7724,12,10000,241,561 +E,7725,12,10000,241,561 +E,7726,12,10000,244,558 +E,7727,12,10000,241,561 +E,7728,12,10000,241,561 +E,7729,12,10000,241,558 +E,7730,12,10000,241,561 +E,7731,12,10000,244,561 +E,7732,12,10000,241,558 +E,7733,12,10000,241,561 +E,7734,12,10000,241,561 +E,7735,12,10000,244,558 +E,7736,12,10000,241,561 +E,7737,12,10000,241,561 +E,7738,12,10000,241,558 +E,7739,12,10000,241,561 +E,7740,12,10000,244,561 +E,7741,12,10000,241,558 +E,7742,12,10000,241,561 +E,7743,12,10000,244,561 +E,7744,12,10000,241,558 +E,7745,12,10000,241,561 +E,7746,12,10000,241,561 +E,7747,12,10000,244,558 +E,7748,12,10000,241,561 +E,7749,12,# step 13/13 rpm=10000 period_us=16 ints=100 count=7749 +D,step_13,2645757560,51,151,25,18,143 +H,step_13,133603,27960,0 +10000,244,561 +D,end,2646937830,84,68,25,95,114 +H,end,29700,28440,0 +drops,0 +samples,7750 +=== END === diff --git a/benches/engine_control/silicon/runs/2026-05-31-nucleo_g474re-wasm-cross-lto-e8488f0c/manifest.txt b/benches/engine_control/silicon/runs/2026-05-31-nucleo_g474re-wasm-cross-lto-e8488f0c/manifest.txt new file mode 100644 index 00000000..79fdae9b --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-05-31-nucleo_g474re-wasm-cross-lto-e8488f0c/manifest.txt @@ -0,0 +1,11 @@ +variant: wasm-cross-LTO (seam dissolved: loom inline gale_k_sem_give_decide into z_impl, synth-compiled) +board: nucleo_g474re +date: 2026-05-31 +synth: v0.11.14 (e8488f0c) +loom: v1.1.5 (95a5f982) +zephyr: v4.4.0 + gale (gale/sem-replacement) +toolchain: clang wasm32 shim + gale-ffi wasm32 -> wasm-ld -> loom --passes inline -> synth --relocatable +integration: fp=0 trampoline + out-of-line kernel-API wrappers (gale_wasm_wrappers.c) + GALE_WASM_LTO_SEM_LIB +handoff_cycles: median 907 (steady), min 904, max 1607 (cold), n=148 +algo_cycles: 259 +drops: 0 diff --git a/benches/engine_control/silicon/runs/2026-05-31-nucleo_g474re-wasm-cross-lto-e8488f0c/output.csv b/benches/engine_control/silicon/runs/2026-05-31-nucleo_g474re-wasm-cross-lto-e8488f0c/output.csv new file mode 100644 index 00000000..340eb827 --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-05-31-nucleo_g474re-wasm-cross-lto-e8488f0c/output.csv @@ -0,0 +1,183 @@ +*** Booting Zephyr OS build v4.4.0-7-g719cc4890346 *** +engine_control bench starting (target 150 samples, 5 sweep steps) +# H ready: temp_mC,vref_mV via ADC1 ch16 + ch18; VBAT not wired (always 0) +# H cal: TS_CAL1=1034@30C TS_CAL2=1367@130C VREFINT_CAL=1659@3000mV +=== ENGINE-CONTROL BENCH RESULTS === +build,gale +cycles_per_sec,170000000 +target_samples,150 +# event rows: E,,,,, +# DWT rows: D,,,,,,, +# health rows:H,,,, +D,boot,6484207,17,53,0,22,149 +H,boot,284654,30533,0 +E,0,0,1000,259,1607 +E,1,0,1000,259,907 +E,2,0,1000,259,907 +E,3,0,1000,259,907 +E,4,0,1000,259,907 +E,5,0,1000,259,907 +E,6,0,1000,259,907 +E,7,0,1000,259,907 +E,8,0,1000,259,907 +E,9,0,1000,259,907 +E,10,0,1000,259,907 +E,11,0,1000,259,907 +E,12,0,1000,259,907 +E,13,0,1000,259,907 +E,14,0,1000,259,907 +E,15,0,1000,259,907 +E,16,0,1000,259,907 +E,17,0,1000,259,907 +E,18,0,1000,259,907 +E,19,0,1000,259,907 +E,20,0,1000,259,907 +E,21,0,1000,259,907 +E,22,0,1000,259,907 +E,23,0,1000,259,907 +E,24,0,1000,259,907 +E,25,0,1000,259,907 +E,26,0,1000,259,907 +E,27,0,1000,259,907 +E,28,0,1000,259,907 +E,29,0,1000,259,907 +# step 1/5 rpm=1000 period_us=166 ints=30 count=30 +D,step_1,17434279,179,34,96,214,76 +H,step_1,106576,29981,0 +E,30,1,2000,259,1607 +E,31,1,2000,259,907 +E,32,1,2000,259,907 +E,33,1,2000,259,907 +E,34,1,2000,259,907 +E,35,1,2000,259,907 +E,36,1,2000,259,907 +E,37,1,2000,259,907 +E,38,1,2000,259,907 +E,39,1,2000,259,907 +E,40,1,2000,259,907 +E,41,1,2000,259,907 +E,42,1,2000,259,907 +E,43,1,2000,259,907 +E,44,1,2000,259,907 +E,45,1,2000,259,907 +E,46,1,2000,259,907 +E,47,1,2000,259,907 +E,48,1,2000,259,907 +E,49,1,2000,259,907 +E,50,1,2000,259,907 +E,51,1,2000,259,907 +E,52,1,2000,259,907 +E,53,1,2000,259,907 +E,54,1,2000,259,907 +E,55,1,2000,259,907 +E,56,1,2000,259,907 +E,57,1,2000,259,907 +E,58,1,2000,259,907 +E,59,1,2000,259,907 +# step 2/5 rpm=2000 period_us=83 ints=30 count=60 +D,step_2,28469588,223,232,181,125,22 +H,step_2,61831,28278,0 +E,60,2,4000,259,1607 +E,61,2,4000,259,907 +E,62,2,4000,259,907 +E,63,2,4000,259,907 +E,64,2,4000,259,907 +E,65,2,4000,259,907 +E,66,2,4000,259,907 +E,67,2,4000,259,907 +E,68,2,4000,259,907 +E,69,2,4000,259,907 +E,70,2,4000,259,907 +E,71,2,4000,259,907 +E,72,2,4000,259,907 +E,73,2,4000,259,907 +E,74,2,4000,259,907 +E,75,2,4000,259,907 +E,76,2,4000,259,907 +E,77,2,4000,259,907 +E,78,2,4000,259,907 +E,79,2,4000,259,907 +E,80,2,4000,259,907 +E,81,2,4000,259,907 +E,82,2,4000,259,907 +E,83,2,4000,259,907 +E,84,2,4000,259,907 +E,85,2,4000,259,907 +E,86,2,4000,259,907 +E,87,2,4000,259,907 +E,88,2,4000,259,907 +E,89,2,4000,259,907 +# step 3/5 rpm=4000 period_us=41 ints=30 count=90 +D,step_3,39519656,232,171,120,102,227 +H,step_3,63933,28440,0 +E,90,3,6000,259,1607 +E,91,3,6000,259,907 +E,92,3,6000,259,910 +E,93,3,6000,259,910 +E,94,3,6000,259,907 +E,95,3,6000,259,907 +E,96,3,6000,259,907 +E,97,3,6000,259,907 +E,98,3,6000,259,907 +E,99,3,6000,259,907 +E,100,3,6000,259,907 +E,101,3,6000,259,907 +E,102,3,6000,259,907 +E,103,3,6000,259,907 +E,104,3,6000,259,907 +E,105,3,6000,259,907 +E,106,3,6000,259,907 +E,107,3,6000,259,907 +E,108,3,6000,259,907 +E,109,3,6000,259,907 +E,110,3,6000,259,907 +E,111,3,6000,259,907 +E,112,3,6000,259,907 +E,113,3,6000,259,907 +E,114,3,6000,259,907 +E,115,3,6000,259,907 +E,116,3,6000,259,907 +E,117,3,6000,259,907 +E,118,3,6000,259,907 +E,119,3,# step 4/5 rpm=6000 period_us=27 ints=30 count=119 +D,step_4,50616886,207,77,153,10,149 +H,step_4,72942,30722,0 +6000,259,907 +E,120,4,10000,259,907 +E,121,4,10000,259,910 +E,122,4,10000,259,910 +E,123,4,10000,261,904 +E,124,4,10000,259,907 +E,125,4,10000,259,907 +E,126,4,10000,261,904 +E,127,4,10000,259,907 +E,128,4,10000,259,907 +E,129,4,10000,261,904 +E,130,4,10000,259,907 +E,131,4,10000,259,907 +E,132,4,10000,261,904 +E,133,4,10000,259,907 +E,134,4,10000,259,907 +E,135,4,10000,261,904 +E,136,4,10000,259,907 +E,137,4,10000,259,907 +E,138,4,10000,261,904 +E,139,4,10000,259,907 +E,140,4,10000,259,907 +E,141,4,10000,261,904 +E,142,4,10000,259,907 +E,143,4,10000,259,907 +E,144,4,10000,261,904 +E,145,4,10000,259,907 +E,146,4,10000,259,907 +E,147,4,10000,261,904 +E,148,4,10000,259,907 +E,149,4,10000,# step 5/5 rpm=10000 period_us=16 ints=30 count=149 +D,step_5,62555264,168,185,153,86,223 +H,step_5,72642,28936,0 +259,907 +D,end,63602696,32,97,153,129,164 +H,end,20091,30347,0 +drops,0 +samples,150 +=== END === diff --git a/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-control_step-engine-algo-synth-v0.11.16/manifest.txt b/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-control_step-engine-algo-synth-v0.11.16/manifest.txt new file mode 100644 index 00000000..c3af2fd6 --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-control_step-engine-algo-synth-v0.11.16/manifest.txt @@ -0,0 +1,19 @@ +Run: engine control_step (the second silicon data point) — wasm-cross-LTO vs native gcc +Board: NUCLEO-G474RE (Cortex-M4F @170 MHz); synth v0.11.16 (a804390, #193 param-clobber FIX); loom v1.1.8 (no-op, single fn) +Build: /tmp/cs-bench (links synth control_algo.116x.o; gale_tables blob @ [fp+0x10000] via asm trampoline + gale_call_control that sets fp=&gale_tables-0x10000 then blx control_step_decide). Native = control_step_native + reading the real tables.c arrays, called via volatile fn-ptr. DWT min/200, ovh=min/200 (=1). +UNBLOCKED BY: synth v0.11.16 fixing the #210/#193 call-free param-register clobber (coolant was clobbered pre-fix). + +RESULT (net cycles, vector 3000,50,40,0): + synth (wasm-cross-LTO) 188 cyc + native gcc -O2 80 cyc + ratio 2.35x +Functional: synth == native == 0x00210a55 (fuel 2645) on hardware — coolant enrichment now CORRECT. +Note: synth path includes the fp-setup trampoline (~6-8 cyc, part of the linmem->native integration); native is + a direct call. Gap (~108 cyc) = 4x udiv (binning /500 /5 /80 /1000) + table addressing + regalloc/CSE (synth#209 Opt1/Opt3). + +Silicon comparison table to date: + k_sem_give handoff : 907 (synth) vs 471 LLVM-LTO = 1.92x + filter_axis : 46 (synth) vs 19 native = 2.42x + control_step : 188 (synth) vs 80 native = 2.35x <-- this run diff --git a/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-control_step-engine-algo-synth-v0.11.16/output.txt b/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-control_step-engine-algo-synth-v0.11.16/output.txt new file mode 100644 index 00000000..2597e8d4 --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-control_step-engine-algo-synth-v0.11.16/output.txt @@ -0,0 +1,4 @@ +*** Booting Zephyr OS build v4.4.0-7-g719cc4890346 *** +SELFCHECK synth=0x00210a55 native=0x00210a55 (exp 0x00210a55 for 3000,50,40,0) +E,control_step,synth=188,native=80,ovh=1,sink=866133200 +=== END === diff --git a/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-control_step-v0.11.17-guard-elision/manifest.txt b/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-control_step-v0.11.17-guard-elision/manifest.txt new file mode 100644 index 00000000..a92d05c7 --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-control_step-v0.11.17-guard-elision/manifest.txt @@ -0,0 +1,3 @@ +control_step on synth v0.11.17 (Opt1 guard-elision). NUCLEO-G474RE, DWT min/200. +synth=174 (was 188 on v0.11.16) -> -14 cyc from dead-guard elision. native=81. ratio 174/81=2.15x (was 2.35x). +Correct (0x00210a55). text 390->364 B. The big mover (reciprocal-mul) is Opt1b, pending. diff --git a/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-control_step-v0.11.17-guard-elision/output.txt b/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-control_step-v0.11.17-guard-elision/output.txt new file mode 100644 index 00000000..978d2f42 --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-control_step-v0.11.17-guard-elision/output.txt @@ -0,0 +1,4 @@ +*** Booting Zephyr OS build v4.4.0-7-g719cc4890346 *** +SELFCHECK synth=0x00210a55 native=0x00210a55 (exp 0x00210a55 for 3000,50,40,0) +E,control_step,synth=174,native=81,ovh=1,sink=866133200 +=== END === diff --git a/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-control_step-v0.11.18/manifest.txt b/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-control_step-v0.11.18/manifest.txt new file mode 100644 index 00000000..8ff6341d --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-control_step-v0.11.18/manifest.txt @@ -0,0 +1 @@ +control_step v0.11.18: synth=172 native=80 ratio=2.15x; correct on HW; guard-elision (Opt1) + #215 fix diff --git a/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-control_step-v0.11.18/output.txt b/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-control_step-v0.11.18/output.txt new file mode 100644 index 00000000..9c6b28a2 --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-control_step-v0.11.18/output.txt @@ -0,0 +1,4 @@ +*** Booting Zephyr OS build v4.4.0-7-g719cc4890346 *** +SELFCHECK synth=0x00210a55 native=0x00210a55 (exp 0x00210a55 for 3000,50,40,0) +E,control_step,synth=172,native=80,ovh=1,sink=866133200 +=== END === diff --git a/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-control_step-v0.11.20-Opt1b-reciprocal-mul/manifest.txt b/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-control_step-v0.11.20-Opt1b-reciprocal-mul/manifest.txt new file mode 100644 index 00000000..d5e9b77d --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-control_step-v0.11.20-Opt1b-reciprocal-mul/manifest.txt @@ -0,0 +1,7 @@ +control_step on synth v0.11.20 (Opt1b: UMULL reciprocal-multiply, all 4 unsigned divides; #217 cost-gate fix). +NUCLEO-G474RE, DWT min/200. synth=168 native=81. correct (0x00210a55). udiv:0 umull:4. text 350->410B. +Trajectory: 188(v16 guards+udiv) -> 172(v18 guard-elision) -> 168(v20 reciprocal-mul). Opt1b = only -4 cyc. +KEY FINDING: Cortex-M4 has FAST hardware udiv (~2-12 cyc), so reciprocal-multiply is near-neutral on M4 +(it's a big win only on cores w/o HW divide, e.g. M0/M0+). The remaining 168/81=2.07x gap is GENERAL CODEGEN +(regalloc/CSE/spilling = #209 Opt3), NOT division — consistent with the filter_axis decomposition (~17cyc base +codegen vs ~10cyc divide). So Opt3 (regalloc/CSE) is the real lever, not more division work. diff --git a/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-control_step-v0.11.20-Opt1b-reciprocal-mul/output.txt b/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-control_step-v0.11.20-Opt1b-reciprocal-mul/output.txt new file mode 100644 index 00000000..175583ce --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-control_step-v0.11.20-Opt1b-reciprocal-mul/output.txt @@ -0,0 +1,4 @@ +*** Booting Zephyr OS build v4.4.0-7-g719cc4890346 *** +SELFCHECK synth=0x00210a55 native=0x00210a55 (exp 0x00210a55 for 3000,50,40,0) +E,control_step,synth=168,native=81,ovh=1,sink=866133200 +=== END === diff --git a/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-filter-axis-wasm-vs-native-v0.11.15/manifest.txt b/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-filter-axis-wasm-vs-native-v0.11.15/manifest.txt new file mode 100644 index 00000000..660b9357 --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-filter-axis-wasm-vs-native-v0.11.15/manifest.txt @@ -0,0 +1,19 @@ +Run: filter_axis_decide (flight_control complementary-filter hot math) — wasm-cross-LTO vs native gcc +Board: NUCLEO-G474RE (STM32G474RE, Cortex-M4F @170 MHz) +Date: 2026-06-02 +synth: v0.11.15 (control via clang->wasm-ld->loom v1.1.5->synth, --target cortex-m4f --relocatable) +native: arm-zephyr-eabi-gcc -O2 (Zephyr SDK), identical C source +Zephyr: v4.4.0-7-g719cc4890346 (gale/sem-replacement-4.4.0) +Method: DWT CYCCNT, min over 200 iterations per vector, both functions called via volatile + function pointer (identical call overhead), overhead (back-to-back CYCCNT read) subtracted. +App: /tmp/filter-bench (standalone; links /tmp/wasm-algo-poc/filter_algo.o) + +RESULT (net cycles): + vector synth native ratio + (1000,100,500) 41 21 1.95x + (-2000,50,-300) 41 21 1.95x + (0,2,0) 39 19 2.05x + (0,0,0) 36 16 2.25x +Functional: synth selfcheck 1088,-1917 correct on hardware (matches native + wasmtime). +Gap attribution: synth emits sdiv + 2 dead guards (div-by-zero + INT_MIN/-1) for /1000; + gcc strength-reduces to reciprocal-multiply. See synth#210 Opt 1. diff --git a/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-filter-axis-wasm-vs-native-v0.11.15/output.txt b/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-filter-axis-wasm-vs-native-v0.11.15/output.txt new file mode 100644 index 00000000..5fb40c4f --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-filter-axis-wasm-vs-native-v0.11.15/output.txt @@ -0,0 +1,8 @@ +*** Booting Zephyr OS build v4.4.0-7-g719cc4890346 *** +SELFCHECK synth: 1088,-1917 (exp 1088,-1917) native: 1088 (exp 1088) +E,v0,synth_net=36,native_net=16,ovh=5 +E,v1,synth_net=41,native_net=21,ovh=5 +E,v2,synth_net=41,native_net=21,ovh=5 +E,v3,synth_net=39,native_net=19,ovh=5 +SINK=-331200 +=== END === diff --git a/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-filter-decomposition-v0.11.15/manifest.txt b/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-filter-decomposition-v0.11.15/manifest.txt new file mode 100644 index 00000000..8062065a --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-filter-decomposition-v0.11.15/manifest.txt @@ -0,0 +1,17 @@ +Run: filter_axis gap decomposition — wasm-cross-LTO vs native gcc, by operation +Board: NUCLEO-G474RE (Cortex-M4F @170 MHz); synth v0.11.15; loom v1.1.5; gcc -O2 (Zephyr SDK) +Method: DWT CYCCNT, min/200 iters; overhead = min/200 back-to-back CYCCNT (=1 cyc); both fns via + volatile fn-ptr (identical call overhead). Reproduced identically across two flashes. +App: /tmp/filter-bench linking /tmp/wasm-algo-poc/fv_algo.o (v_full/v_nodiv/v_div). + +RESULT (net cycles): + variant synth native ratio + full ((p+g)*980+a*20)/1000 46 19 2.42x + nodiv ((p+g)*980+a*20) 29 12 2.42x + div x/1000 40 15 2.67x +Decomposition of the 27-cyc gap on `full`: + base codegen (mul+add): 29-12 = 17 cyc (spills, no constant CSE) <- LARGER contributor + divide handling: (46-29)-(19-12) = 17-7 = 10 cyc (sdiv+2 dead guards vs reciprocal-mul) +CORRECTION to earlier note: the gap is NOT dominated by the divide; base codegen is bigger. +Functional: synth full=1088, div=-1917 correct on HW. Supersedes the 1.95x figure (that used an + overestimated single-sample overhead of 5; true ovh=1). diff --git a/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-filter-decomposition-v0.11.15/output.txt b/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-filter-decomposition-v0.11.15/output.txt new file mode 100644 index 00000000..e6a63a06 --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-filter-decomposition-v0.11.15/output.txt @@ -0,0 +1,7 @@ +*** Booting Zephyr OS build v4.4.0-7-g719cc4890346 *** +SELFCHECK full s=1088 n=1088 (exp 1088) div s=-1917 n=-1917 (exp -1917) +E,full ,synth=46,native=19 +E,nodiv,synth=29,native=12 +E,div ,synth=40,native=15 +SINK=436128800 ovh=1 +=== END === diff --git a/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-flight_algo-FULLY-DISSOLVED-loom1.1.10-synth0.11.16/manifest.txt b/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-flight_algo-FULLY-DISSOLVED-loom1.1.10-synth0.11.16/manifest.txt new file mode 100644 index 00000000..d8c76687 --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-flight_algo-FULLY-DISSOLVED-loom1.1.10-synth0.11.16/manifest.txt @@ -0,0 +1,23 @@ +Run: flight_control COMPOSED algo (filter_step + controller_step) FULLY DISSOLVED — wasm-cross-LTO vs native +Board: NUCLEO-G474RE (Cortex-M4F @170MHz). loom v1.1.10 (full dissolution: both fns inline -> 0 calls, Z3-proven), + synth v0.11.16 (#193 fix). flight_algo = ONE flat 784B function. fp=0 trampoline (native ptr deref). +Native = flat (gcc-inlined) flat_flight_native, volatile fn-ptr. DWT min/200, ovh=1. +THE BIGGER EXAMPLE composed algo, measured end-to-end. + +RESULT (vector st={1000,-500,200,upd7}, s={gx100,gy-50,gz30,ax300,ay-200}): + synth (wasm-cross-LTO, fully dissolved) 332 cyc + native gcc -O2 (flat) 99 cyc + ratio 3.35x +Functional: synth == native == 0x07fdf307 (CORRECT on hardware). +Note: synth path includes ~8-cyc fp=0 trampoline; native ~3-cyc indirect call. Gap larger than the +single-fn algos (sem 1.92x, filter_axis 2.42x, control_step 2.35x) because the fused function has +multiple divides (filter /1000 x2) + high register pressure -> synth#209 Opt1b (reciprocal-mul) + regalloc. + +CORRECTION: fp=0 + real pointers WORKS on HW (earlier "silence" was capture flakiness, not a fault). +The composed-algo HW number was NOT blocked by a pointer/linmem ABI issue after all. + +Full silicon table: + k_sem_give handoff : 907 / 471 LLVM-LTO = 1.92x + filter_axis : 46 / 19 = 2.42x + control_step : 188 / 80 = 2.35x + flight_algo (composed, fully dissolved) : 332 / 99 = 3.35x diff --git a/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-flight_algo-FULLY-DISSOLVED-loom1.1.10-synth0.11.16/output.txt b/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-flight_algo-FULLY-DISSOLVED-loom1.1.10-synth0.11.16/output.txt new file mode 100644 index 00000000..5b4f0c7c --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-flight_algo-FULLY-DISSOLVED-loom1.1.10-synth0.11.16/output.txt @@ -0,0 +1,5 @@ +*** Booting Zephyr OS build v4.4.0-7-g719cc4890346 *** +BOOT-OK: main reached, about to call flight_algo +SELFCHECK synth=0x07fdf307 native=0x07fdf307 (exp 0x07fdf307) +E,flat_flight,synth=332,native=99,ovh=1,sink=2093726448 +=== END === diff --git a/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-flight_algo-composed-v0.11.18/manifest.txt b/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-flight_algo-composed-v0.11.18/manifest.txt new file mode 100644 index 00000000..67e23368 --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-flight_algo-composed-v0.11.18/manifest.txt @@ -0,0 +1 @@ +flight_algo-composed v0.11.18: synth=315 native=99 ratio=3.18x; correct on HW; guard-elision (Opt1) + #215 fix diff --git a/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-flight_algo-composed-v0.11.18/output.txt b/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-flight_algo-composed-v0.11.18/output.txt new file mode 100644 index 00000000..d1027241 --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-flight_algo-composed-v0.11.18/output.txt @@ -0,0 +1,5 @@ +*** Booting Zephyr OS build v4.4.0-7-g719cc4890346 *** +BOOT-OK: main reached, about to call flight_algo +SELFCHECK synth=0x07fdf307 native=0x07fdf307 (exp 0x07fdf307) +E,flat_flight,synth=315,native=99,ovh=1,sink=2093726448 +=== END === diff --git a/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-flight_control-native-baseline/manifest.txt b/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-flight_control-native-baseline/manifest.txt new file mode 100644 index 00000000..d158a35e --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-flight_control-native-baseline/manifest.txt @@ -0,0 +1,12 @@ +Run: flight_control composed bench (5 primitives) — NATIVE baseline, first silicon run +Board: NUCLEO-G474RE (Cortex-M4F @170 MHz); Zephyr v4.4.0-7-g719cc4890346; build=baseline +Build: west build -b nucleo_g474re (gale/benches/flight_control, unmodified). FLASH 23728B RAM 52800B. +Purpose: stand up the "bigger example" on silicon; capture native baseline before wasm-cross-LTO. + +RESULT: boots + runs. Step 1/5 (sensor_hz=500, contention=0, payload=16) produced 6 events: + algo=141 handoff=1307 t_lock=339 t_post=858 t_round=1987 t_bcast=748/-1 (cycles) +STALL: step 2/5 (sensor_hz=1000, payload=32) -> count=0 [drain_timeout]; sweep did not reach === END ===. + This is a flight_control bench-logic issue at the higher sensor rate (actuator-drain path), NOT a + synth/loom matter. Flag for the bench owner; the short sweep's 1000 Hz cell needs the drain fix. +NOTE: the bench `algo` segment (141 cyc) = filter_step+controller_step — the same math wasm-ified in + /tmp/wasm-algo-poc (controller_step + filter_axis). wasm-cross-LTO comparison would swap that segment. diff --git a/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-flight_control-native-baseline/output.txt b/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-flight_control-native-baseline/output.txt new file mode 100644 index 00000000..4a0a35f0 --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-06-02-nucleo_g474re-flight_control-native-baseline/output.txt @@ -0,0 +1,27 @@ +*** Booting Zephyr OS build v4.4.0-7-g719cc4890346 *** +flight_control bench starting (target 50 samples, 5 sweep steps) +=== FLIGHT-CONTROL BENCH RESULTS === +build,baseline +cycles_per_sec,170000000 +target_samples,50 +# event rows: E,,,,,,,,, +E,4,0,500,141,1307,339,858,1987,-1 +E,9,0,500,141,1307,339,858,1987,748 +E,14,0,500,141,1307,339,858,1987,-1 +E,19,0,500,141,1307,339,858,1987,748 +E,24,0,500,141,1307,339,858,1987,-1 +E,29,0,500,141,1307,339,858,1937,748 +# step 1/5 sensor_hz=500 contention=0 payload=16 ints=30 expected=6 count=6 +# step 2/5 sensor_hz=1000 contention=0 payload=32 ints=30 expected=3 count=0 [drain_timeout] +# step 3/5 sensor_hz=1000 contention=1 payload=32 ints=30 expected=3 count=0 [drain_timeout] +E,67,2,2000,141,1307,339,870,4017,-1 +E,77,2,2000,141,1307,4122,870,3233,-1 +E,87,2,2000,141,1307,4092,870,3208,-1 +E,89,2,2000,141,1307,3826,870,3214,281 +E,102,3,2000,141,1# step 4/5 sensor_hz=2000 contention=0 payload=32 ints=30 expected=1 count=4 +# step 5/5 sensor_hz=2000 contention=2 payload=64 ints=30 expected=1 count=0 [drain_timeout] +307,339,858,1962,-1 +E,119,3,18384,141,1307,342,882,6090,736 +E,129,4,18384,141,1307,339,882,6052,777 +E,149,4,18384,141,1307,339,858,1937,311 +final drain timeout; count=14 diff --git a/benches/engine_control/silicon/runs/2026-06-11-nucleo_g474re-wasm-cross-lto-v0.11.37-faithful/capture.log b/benches/engine_control/silicon/runs/2026-06-11-nucleo_g474re-wasm-cross-lto-v0.11.37-faithful/capture.log new file mode 100644 index 00000000..9accaa77 --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-06-11-nucleo_g474re-wasm-cross-lto-v0.11.37-faithful/capture.log @@ -0,0 +1,184 @@ +*** Booting Zephyr OS build v4.4.0-7-g719cc4890346 *** +engine_control bench starting (target 150 samples, 5 sweep steps) +# H temp_mC,vref_mV,vbat_mV: not available on this target (stub backend) +=== ENGINE-CONTROL BENCH RESULTS === +build,gale +cycles_per_sec,170000000 +target_samples,150 +overhead_cycles,60 +# event rows: E,,,,, +# algo / handoff cycles are AFTER subtracting overhead_cycles +# DWT rows: D,,,,,,, +# health rows:H,,,, +D,boot,6789047,217,52,0,62,220 +H,boot,0,0,0 +E,0,0,1000,208,1586 +E,1,0,1000,208,860 +E,2,0,1000,208,860 +E,3,0,1000,208,860 +E,4,0,1000,208,860 +E,5,0,1000,208,860 +E,6,0,1000,208,860 +E,7,0,1000,208,860 +E,8,0,1000,208,860 +E,9,0,1000,208,860 +E,10,0,1000,208,860 +E,11,0,1000,208,860 +E,12,0,1000,208,860 +E,13,0,1000,208,860 +E,14,0,1000,208,860 +E,15,0,1000,208,860 +E,16,0,1000,208,860 +E,17,0,1000,208,860 +E,18,0,1000,208,860 +E,19,0,1000,208,860 +E,20,0,1000,208,860 +E,21,0,1000,208,860 +E,22,0,1000,208,860 +E,23,0,1000,208,860 +E,24,0,1000,208,860 +E,25,0,1000,208,860 +E,26,0,1000,208,860 +E,27,0,1000,208,860 +E,28,0,1000,208,860 +E,29,0,1000,208,860 +# step 1/5 rpm=1000 period_us=166 ints=30 count=30 +D,step_1,17620228,80,139,190,153,53 +H,step_1,0,0,0 +E,30,1,2000,208,1586 +E,31,1,2000,208,860 +E,32,1,2000,208,860 +E,33,1,2000,208,860 +E,34,1,2000,208,860 +E,35,1,2000,208,860 +E,36,1,2000,208,860 +E,37,1,2000,208,860 +E,38,1,2000,208,860 +E,39,1,2000,208,860 +E,40,1,2000,208,860 +E,41,1,2000,208,860 +E,42,1,2000,208,860 +E,43,1,2000,208,860 +E,44,1,2000,208,860 +E,45,1,2000,208,860 +E,46,1,2000,208,860 +E,47,1,2000,208,860 +E,48,1,2000,208,860 +E,49,1,2000,208,860 +E,50,1,2000,208,860 +E,51,1,2000,208,860 +E,52,1,2000,208,860 +E,53,1,2000,208,860 +E,54,1,2000,208,860 +E,55,1,2000,208,860 +E,56,1,2000,208,860 +E,57,1,2000,208,860 +E,58,1,2000,208,860 +E,59,1,2000,208,860 +# step 2/5 rpm=2000 period_us=83 ints=30 count=60 +D,step_2,28536444,8,177,50,123,159 +H,step_2,0,0,0 +E,60,2,4000,208,1586 +E,61,2,4000,208,860 +E,62,2,4000,208,860 +E,63,2,4000,208,860 +E,64,2,4000,208,860 +E,65,2,4000,208,860 +E,66,2,4000,208,860 +E,67,2,4000,208,860 +E,68,2,4000,208,860 +E,69,2,4000,208,860 +E,70,2,4000,208,860 +E,71,2,4000,208,860 +E,72,2,4000,208,860 +E,73,2,4000,208,860 +E,74,2,4000,208,860 +E,75,2,4000,208,860 +E,76,2,4000,208,860 +E,77,2,4000,208,860 +E,78,2,4000,208,860 +E,79,2,4000,208,860 +E,80,2,4000,208,860 +E,81,2,4000,208,860 +E,82,2,4000,208,860 +E,83,2,4000,208,860 +E,84,2,4000,208,860 +E,85,2,4000,208,860 +E,86,2,4000,208,860 +E,87,2,4000,208,860 +E,88,2,4000,208,860 +E,89,2,4000,208,860 +# step 3/5 rpm=4000 period_us=41 ints=30 count=90 +D,step_3,39438518,81,219,59,122,8 +H,step_3,0,0,0 +E,90,3,6000,208,1586 +E,91,3,6000,208,860 +E,92,3,6000,208,860 +E,93,3,6000,208,860 +E,94,3,6000,208,860 +E,95,3,6000,208,860 +E,96,3,6000,208,860 +E,97,3,6000,208,860 +E,98,3,6000,208,860 +E,99,3,6000,208,860 +E,100,3,6000,208,860 +E,101,3,6000,208,860 +E,102,3,6000,208,860 +E,103,3,6000,208,860 +E,104,3,6000,208,860 +E,105,3,6000,208,860 +E,106,3,6000,208,860 +E,107,3,6000,208,860 +E,108,3,6000,208,860 +E,109,3,6000,208,860 +E,110,3,6000,208,860 +E,111,3,6000,208,860 +E,112,3,6000,208,860 +E,113,3,6000,208,860 +E,114,3,6000,208,860 +E,115,3,6000,208,860 +E,116,3,6000,208,860 +E,117,3,6000,208,860 +E,118,3,6000,208,860 +E,119,3,# step 4/5 rpm=6000 period_us=27 ints=30 count=119 +D,step_4,50358666,122,239,4,37,137 +H,step_4,0,0,0 +6000,208,860 +E,120,4,10000,208,860 +E,121,4,10000,208,860 +E,122,4,10000,208,863 +E,123,4,10000,208,863 +E,124,4,10000,208,860 +E,125,4,10000,208,860 +E,126,4,10000,208,863 +E,127,4,10000,208,860 +E,128,4,10000,208,860 +E,129,4,10000,208,863 +E,130,4,10000,208,860 +E,131,4,10000,208,860 +E,132,4,10000,208,863 +E,133,4,10000,208,860 +E,134,4,10000,208,860 +E,135,4,10000,208,863 +E,136,4,10000,208,860 +E,137,4,10000,208,860 +E,138,4,10000,208,863 +E,139,4,10000,208,860 +E,140,4,10000,208,860 +E,141,4,10000,208,863 +E,142,4,10000,208,860 +E,143,4,10000,208,860 +E,144,4,10000,208,863 +E,145,4,10000,208,860 +E,146,4,10000,208,860 +E,147,4,10000,208,863 +E,148,4,10000,208,860 +E,149,4,10000,# step 5/5 rpm=10000 period_us=16 ints=30 count=149 +D,step_5,62164223,255,162,4,131,169 +H,step_5,0,0,0 +208,860 +D,end,63078861,147,188,4,42,248 +H,end,0,0,0 +drops,0 +samples,150 +=== END === diff --git a/benches/engine_control/silicon/runs/2026-06-11-nucleo_g474re-wasm-cross-lto-v0.11.37-faithful/manifest.txt b/benches/engine_control/silicon/runs/2026-06-11-nucleo_g474re-wasm-cross-lto-v0.11.37-faithful/manifest.txt new file mode 100644 index 00000000..119cca76 --- /dev/null +++ b/benches/engine_control/silicon/runs/2026-06-11-nucleo_g474re-wasm-cross-lto-v0.11.37-faithful/manifest.txt @@ -0,0 +1,13 @@ +variant: wasm-cross-LTO sem (FAITHFUL shim: real k_sem layout + real wait_q; old 907 shim was unsound) +board: nucleo_g474re +date: 2026-06-11 +synth: v0.11.37 (all three #311 i64 fixes + #237 sizing + realloc-ON + dead-save elim) +loom: v1.1.13 +zephyr: v4.4.0 final + gale (gale/sem-replacement @719cc4890) +integration: r11=0 trampoline + gale_w_* wrappers + GALE_WASM_LTO_SEM_LIB; CONFIG_ADC=n + (ADC health stubbed: the ADC IRQ-path interaction hangs the wasm-sem build — + pre-existing class, see engine_control CMakeLists comment re LTO variants; tracked separately) +handoff_cycles: median 860 (steady), min 860, max 1586 (cold), n=148 +drops: 0 +references: old UNSOUND number 907 (v0.11.14, NULL-wait_q shim); baseline ~528; rustc-direct ~574; LLVM-LTO ~471 +ratio: 860/471 = 1.83x LLVM-LTO (was 1.92x); sound wake path included for the first time diff --git a/benches/engine_control/silicon/wasm-testbed/FLIGHT-CONTROL-PHASE5-READINESS.md b/benches/engine_control/silicon/wasm-testbed/FLIGHT-CONTROL-PHASE5-READINESS.md new file mode 100644 index 00000000..b7f7557e --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/FLIGHT-CONTROL-PHASE5-READINESS.md @@ -0,0 +1,60 @@ +# flight_control (Phase 5) — wasm-cross-LTO readiness + +The `flat_flight` testbed function is the dissolved value-in/value-out composition of the +**real** `benches/flight_control/src/control.c` algorithm (`filter_step` + `controller_step`). +This note records that the actual bench algorithm — not just the testbed shim — is +wasm-cross-LTO-ready on both backends, so wiring a wasm variant into the bench is de-risked. + +## Verified 2026-06-03 (synth v0.11.27, loom v1.1.10) + +**1. The real bench `control.c` dissolves + compiles on both synth backends:** + +| function | wasm→loom→synth ARM (cortex-m4f) | synth RISC-V (rv32imac) | +|----------|----------------------------------|--------------------------| +| `filter_step` (ptr in/out) | 202 B | 336 B | +| `controller_step` (ptr in) | 420 B | 476 B | + +Pipeline: `clang --target=wasm32 -O2 -Isrc -c control.c` → `wasm-ld --export=filter_step +--export=controller_step` → `loom optimize --passes inline` (594 B) → `synth compile` +(`--target cortex-m4f` and `-b riscv -t rv32imac`). Both exports present as symbols in both objects. + +**2. Functionally identical to the validated `flat_flight`:** +native `control.c` with the flat_flight vector (st pitch=1000 roll=−500 yaw=200 updates=7; +imu gyro=100,−50,30 accel=300,−200) → `cmd=0x07FDF307`, state pitch=937 roll=−396 yaw=230 — +**exactly** flat_flight's ground truth. So flat_flight's prior validation transfers directly: +- ARM silicon (G474RE, loom v1.1.10 full dissolution): 315 cyc vs 99 native = 3.18× +- RV32 qemu-icount (v0.11.27): 181 vs 75 = 2.41× (0 callee-saved spills) +- Functional: correct on ARM (unicorn) + RV32 (qemu) + +## Remaining to stand up the bench's wasm variant +- A `GALE_WASM_LTO` CMake path in `benches/flight_control/CMakeLists.txt` that links the dissolved + `control.o` (ARM) in place of the native `control.c`, with the fp/s11 pointer trampoline (the + `flat_flight` harness already proves the s11=0 / fp=0 native-deref trampoline works for these + pointer-arg functions). +- ABI: synth passes args in registers r0..r7 (ARM) / a0..a7 (RV32), not AAPCS stack — the + trampoline/caller must match (see `arm_funccheck.py`). `filter_step`/`controller_step` are + ≤2 ptr args so this is moot for them, but noted for the composed entry. +- Then measure on silicon as the flight-control second data point (the algo segment must stay + byte-identical baseline-vs-gale to pass the bench's <10% algo-delta integrity assert). + +## UPDATE — bench verified functional + dissolved path validated end-to-end (2026-06-03) + +**The bench itself is stood up:** `west build -b qemu_cortex_m3` builds clean and runs — it boots, +drives the 100 Hz loop, and emits the event stream `E,,,,,,, +,,`. Baseline `algo` (filter_step+controller_step in the ISR) ≈ **53 cyc** +on qemu_cortex_m3 — the reference the wasm-cross-LTO path will be compared against. + +**The dissolved real `control.c` runs correctly end-to-end with the pointer trampoline (ARM, unicorn):** +set up `flight_state`/`imu_sample` in memory, `fp(r11)=0` for native `[fp+ptr]=[ptr]` deref, then call +the synth-compiled `filter_step(&st,&s)` (mutates st → pitch=937 roll=−396 yaw=230) and +`controller_step(&st)` (→ `cmd=0x07FDF307`). **Exact match** to flat_flight ground truth. This closes the +last functional gap: the bench's two real pointer-arg functions work through clang→wasm-ld→loom→synth→ARM +with the fp trampoline, not just the value-in/out shim. + +**Phase-5 readiness checklist:** +- [x] real `control.c` dissolves (loom) + compiles both backends (ARM + RV32) +- [x] functionally identical to validated flat_flight (native ground truth) +- [x] dissolved ARM path correct end-to-end with the fp=0 pointer trampoline (unicorn) +- [x] bench builds + runs in qemu (baseline algo ≈ 53 cyc) +- [ ] `GALE_WASM_LTO` CMake path: build `control.o` (synth ARM) + fp-trampoline `.S`, link in place of `control.c` +- [ ] silicon measurement on nucleo_g474re (DWT), algo byte-identity preserved for the <10% integrity assert diff --git a/benches/engine_control/silicon/wasm-testbed/README.md b/benches/engine_control/silicon/wasm-testbed/README.md new file mode 100644 index 00000000..b5a25c02 --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/README.md @@ -0,0 +1,119 @@ +# wasm-cross-LTO testbed + +**Quick regression check:** `./run_testbed.sh` — rebuilds all 3 algorithm functions from source and verifies both synth-compiles (catches codegen regressions, e.g. v0.11.19 register-exhaustion) and wasmtime functional correctness vs verified ground-truth vectors. Exit 0 = ALL GREEN. Run on every new synth/loom release. + + +A three-layer testbed for validating and benchmarking the +`clang → wasm-ld → loom → synth → ARM` pipeline that dissolves the C↔Rust / +caller↔callee seam for Cortex-M kernel/algorithm code. Built while driving the +on-silicon `wasm-cross-LTO` work (see `../boards/nucleo_g474re/NOTES-wasm-cross-lto-spike.md`). + +Each layer answers a different question, cheap → expensive: + +| Layer | Tool | Question | Needs HW? | +|-------|------|----------|-----------| +| 1. Functional (wasm) | `wasm_oracle.sh` (wasmtime) | Does the wasm compute the right values? | no | +| 2. Functional (ARM) | `arm_harness.py` (unicorn) | Does **synth's Cortex-M output** compute the right values? | no | +| 3. Performance | `silicon-microbench/` (Zephyr + DWT) | How many **cycles** on real silicon, vs native gcc? | NUCLEO-G474RE | + +The point: layers 1–2 catch functional bugs (and isolate whether a fault is in +our wasm vs synth's lowering) **without** a board; layer 3 is reserved for the +actual cycle measurement once functionality is proven. + +## Pipeline (per function) + +```sh +clang --target=wasm32-unknown-unknown -O2 -nostdlib -c fn.c -o fn.o +wasm-ld --no-entry --export= --allow-undefined --gc-sections fn.o [tables.o] -o fn.wasm +loom optimize fn.wasm --passes inline --attestation false -o fn.loom.wasm # dissolves caller↔callee seams (loom ≥ v1.1.6 for memory-reading callees) +synth compile fn.loom.wasm --target cortex-m4f --all-exports --relocatable -o fn.o # ARM ET_REL +``` + +## Layer 1 — wasm functional oracle (`wasm_oracle.sh`) + +Runs each exported function in wasmtime and diffs against a native reference. +Covers `control_step_decide` (engine), `controller_step_decide` + `filter_axis` +(flight). **Caveat:** `wasmtime --invoke` must be one-shot per process — capturing +it inside a shell loop returns empty; call each vector explicitly. + +## Layer 2 — ARM functional harness (`arm_harness.py`) + +Executes synth's Thumb-2 output under unicorn. Validated against a trivial +`add3(a,b,c)=60`, so a divergence is a real synth-lowering bug, not a harness +artifact. Memory model: code @ 0x08000000, RAM @ 0x20000000; for table/pointer +functions, `fp(r11)` = linear-memory base (the **fp=0 trampoline** makes +`[fp+ptr]` a native deref). This layer is how we pinned synth#210 (a live +pointer/param register is clobbered mid-body during memory access — generalizes +from the engine tables to pointer-struct reads like `filter_step`). + +## Layer 3 — silicon micro-bench (`silicon-microbench/`) + +A standalone Zephyr app that links a synth ET_REL object and times the function +with DWT CYCCNT @170 MHz, head-to-head vs the native gcc build of identical C +(both called via a volatile fn-pointer with the Thumb bit set — synth#170 emits +no `$t` symbol — so call overhead is identical and the delta is pure codegen). +Overhead floor = min over 200 back-to-back CYCCNT reads (= 1 cyc; do **not** use +a single sample). Build/flash: + +```sh +export ZEPHYR_BASE=.../pulseengine/zephyr +west build -b nucleo_g474re -d /tmp/build silicon-microbench # edit CMakeLists link target to your fn.o +# capture BEFORE reset: python3 ../capture.py --port --sentinel "=== END ===" --out cap.txt & +openocd -f interface/stlink.cfg -f target/stm32g4x.cfg -c "program build/zephyr/zephyr.elf verify reset exit" +``` + +## Results to date (NUCLEO-G474RE, synth v0.11.20 / loom v1.1.10) + +| function | synth (wasm-cross-LTO) | native | ratio | status | +|----------|------------------------|--------|-------|--------| +| `k_sem_give` handoff | 907 cyc | 471 (LLVM-LTO) | 1.92× | on silicon | +| `filter_axis` | 46 cyc | 19 | 2.42× | on silicon | +| `control_step` (engine algo) | 168 cyc | 81 | 2.07× | on silicon (full Opt 1: guard-elision + reciprocal-mul) | +| `flight_algo` (filter+controller, fully dissolved) | 315 cyc | 99 | 3.18× | on silicon (loom v1.1.10 full dissolution) | + +All four functionally correct on hardware. **Synth correctness fixed** (#210 param-clobber, +#212/#215 R12-scratch — all closed). **Key perf finding:** Opt 1b (reciprocal-multiply) is +near-neutral on Cortex-M4 (−4 cyc on control_step) because M4 has a fast HW `udiv`; the ~2× +gap is **general codegen — register allocation + constant-CSE (Opt 3)**, confirmed by the +filter_axis decomposition (~17 cyc base-codegen vs ~10 cyc divide) and by control_step staying +2× with divides fully optimized. Remaining synth work (issue #209): **Opt 3** — constant-CSE +(control_step is ~28% constant materialization, ~1/3 redundant) + reclaim r9/r10 (both free). + +## Adding a function + +1. Write `fn.c` as scalar-in/scalar-out where possible (avoid host pointers; pack + multiple outputs into a return). Pointer/table functions need the fp trampoline + and are currently synth#210-blocked. +2. Run the pipeline above → add a vector set to `wasm_oracle.sh` and `arm_harness.py`. +3. Only once layers 1–2 pass, wire it into `silicon-microbench/` and measure. + +## Multi-target layout (`arch/`) — shared front-half vs per-target back-half + +The shared front-half lives at the testbed root (algorithm C sources, the wasm modules, loom dissolution, +the wasmtime oracle + verified vectors — all architecture-independent). The per-target **back-half** is a +small adapter under `arch//`: + +- **`arch/riscv/run_rv_funccheck.sh`** — RV32 **functional regression lane**: dissolves each leaf, compiles + the actual `synth -b riscv` output, links it into a qemu harness and **asserts wasmtime-verified values + across 10 vectors** (zero / positive / negative / ±127-saturation / signed-div-overflow / 4 table cells) — + the per-axis input edges a const-CSE or liveness miscompile is most likely to break on only a subset of + inputs. Exit 0 = all RV32 outputs correct. This is the lane the wasmtime/ARM-only checks lacked — it + auto-caught synth #232 (the v0.11.26 `i32.div_s` dividend-clobber) as `FAIL filter_axis got=0`. Run on + every new synth release alongside `../../run_testbed.sh`. +- **`arm_funccheck.py`** — the ARM (Cortex-M4 Thumb-2, unicorn) analogue of the RV32 lane: same edge vectors + for `filter_axis`/`controller_step`. Also documents synth's ARM arg convention — **args in registers + r0..r7** (RISC-V a0..a7 style), NOT AAPCS r0-r3+stack (a 7-arg fn pushes `{r4-r8,lr}` and reads args 5-7 + from the saved r4/r5/r6 slots). So a >4-arg dissolved function needs a caller matching that, not stock + AAPCS. ALL GREEN on v0.11.27. +- **`arch/riscv/`** — RISC-V adapter. `run_native.sh` builds the shared algorithm sources with + `riscv64-elf-gcc -march=rv32imac_zicsr`, links synth's `riscv-runtime` (startup.c + linker.ld), and runs + on `qemu-system-riscv32 virt -icount` with an `mcycle`-CSR harness (`main.c`). NATIVE baseline (qemu + `-icount` = instruction-count proxy, **not** silicon cycles): filter_axis 17, control_step 62, flat_flight 75 + (all correct). For the synth path: `synth compile .loom.wasm -b riscv -t rv32imac` and link its `.o` + in place of the native obj (RISC-V linear-memory base = `s11`, the analogue of ARM `r11`). Real RV silicon + cycles need ESP32-C3 or Renode (neither currently wired here). +- **arch/arm** — the ARM adapter is the existing `../silicon-microbench/` (Cortex-M Zephyr + DWT CYCCNT on + NUCLEO-G474RE) + the `arm_harness.py` unicorn layer. + +So: write+verify the wasm/oracle **once**; retarget by swapping only the `arch//` adapter +(synth backend `-b arm`/`-b riscv`, the linmem-base trampoline register, the runtime/linker, and the cycle harness). diff --git a/benches/engine_control/silicon/wasm-testbed/RESULTS-SUMMARY.md b/benches/engine_control/silicon/wasm-testbed/RESULTS-SUMMARY.md new file mode 100644 index 00000000..8e1d5165 --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/RESULTS-SUMMARY.md @@ -0,0 +1,69 @@ +# wasm-cross-LTO — consolidated results + +The `clang → wasm-ld → loom (dissolve seam) → synth → ELF` pipeline, measured against the +native/LLVM-LTO/rustc-direct alternatives. ARM = real NUCLEO-G474RE silicon, DWT CYCCNT @170 MHz, +min-over-200 (or bench median where noted). RISC-V = `qemu_riscv32 -icount` (instruction-count +**proxy**, not silicon cycles). Single source of truth; see NOTES-wasm-cross-lto-spike.md for provenance. + +## Kernel primitive (the headline) + +| primitive | wasm-cross-LTO | LLVM-LTO | native gale | notes | +|-----------|---------------|----------|-------------|-------| +| `k_sem_give` handoff (ARM silicon) | **860** cyc | 471 | — | 1.83×; **sound re-baseline** (faithful Zephyr v4.4.0 shim, v0.11.37, n=148, drops=0, ADC path bypassed). **Supersedes the unsound 907** (NULL `wait_q` + skewed layout — semantically wrong). Seam folded (no `bl ..._decide`). 21% of the 165-insn body is `[sp]` spills (see synth#209 / VCR-RA). | +| `k_mutex_unlock` (ARM silicon) | **472** cyc | — | **124** (ref) | 3.81×; **re-measured 2026-06-14 on synth v0.11.43** (#345 `.bss`+PC-relative fix; module merged via gale PR #60). Down from 501 (v0.11.41) — −29 cyc / −5.8% across 0.11.41→0.11.43. SELFCHECK rc=0 owner=0 OK. Full `mutex_api` suite 9/9 PASS on G474RE (not just no-waiter). Worst ratio in suite — 34% of the 167-insn dissolved body is `[sp]` spills (see synth#209 — the lever). | + +## Algorithm functions (value-in/value-out — dissolve cleanly, both backends) + +| function | ARM silicon (synth / native) | RISC-V icount v0.11.27 (synth / native) | +|----------|------------------------------|------------------------------------------| +| `filter_axis` | 46 / 19 = **2.42×** | 23 / 17 = **1.35×** | +| `control_step` (engine algo) | 151 / 67 = **2.25×**§ (#283 −7) | 129 / 62 = **2.08×** | +| `controller_step` (7-arg) | 150 / 61 = **2.46×**† | 100 / 49 = **2.04×** | +| `flat_flight` (flight algo, composed) | 241 / 103 = **2.34×**‡ (#283 in-place select −14) (262→261 #250 AND, →255 #262 clamp) | 181 / 75 = **2.41×** | + +All functionally correct on both backends (RV32 funccheck 10/10, ARM funccheck 6/6, wasmtime oracle). + +‡ `flat_flight` ARM **re-measured 2026-06-13 on G474RE at the current toolchain (synth 0.11.40 + loom 1.1.13): 241/103 = 2.34×**, SELFCHECK 0x07fdf307 OK, reproducible `flat_flight-microbench/build.sh` + `RESULT-2026-06-13-g474re-v0.11.40.txt`. Stable vs v0.11.35 (241); down from 262 (v0.11.30, 2026-06-04) and 315 (v0.11.18, stale). 241 includes the fp-setup trampoline (~8 cyc); body ~233. Composed flight algo (filter_step+controller_step). + +§ `control_step` ARM **re-measured 2026-06-13 on G474RE at the current toolchain (synth 0.11.40 + loom 1.1.13): 151/67 = 2.25×**, SELFCHECK 2165333 OK, reproducible `control-step-microbench/build.sh` + `RESULT-2026-06-13-g474re.txt`. Down from 158/67 (v0.11.34, 2026-06-05) — ~5 cyc (~3%) from codegen improvements between 0.11.34→0.11.40. Prior 168/81 was an older synth. Buffer-harness (tables copied into a RAM linmem buffer, r11=base). This 151 is the hardware-locked "before" baseline for the synth#209 flag-fold/spill-reduction kill-criterion (target ~127). + +† `controller_step` has 7 args; synth’s cortex-m convention passes args in **r0–r7** (not AAPCS r0–r3+stack), so a C/Zephyr caller needs an arg-shuffle trampoline (`controller-microbench/ctl_tramp.S`). Arc 169→168 (#250 AND)→162 (#258 clamp)→**150** (#283 in-place select); the 150 includes the ~8-cyc arg-shuffle (native called directly). SELFCHECK 0x05e33e81 == native on G474RE. **Re-confirmed 2026-06-13 on synth 0.11.41: 150/61 = 2.46x** (down from 169 @ v0.11.30; 6 flag-fold round-trips / 3 spills in the 99-insn body -> flag-fold-dominated). +flight_control bench wasm-LTO variant builds + runs the dissolved algorithm on G474RE (Phase 5). + +## Bigger example — flight_control macro bench (Phase 5, composed) + +The flight_control bench composes 5 Zephyr primitives (ring_buf, sem, mutex, msgq, condvar) on a +100 Hz loop; `GALE_FC_WASM_LTO=ON` dissolves the ISR-side flight algo (`filter_step`+`controller_step`) +via wasm-cross-LTO. On real G474RE silicon, full 5-step sweep, **no fault**, **re-confirmed +2026-06-13 on the current toolchain (synth 0.11.41 + loom 1.1.13): in-bench `algo` = 157 cyc, +perfectly stable (min=median=max, n=9 across the sweep)** — unchanged from the first measurement +(synth 0.11.30), so the composed-context result holds on the post-#331 toolchain: + +| metric (in-bench `algo`) | wasm-cross-LTO | native | ratio | +|--------------------------|----------------|--------|-------| +| ISR filter precompute | **157** cyc | 141 | **1.11×** | + +The in-context overhead is only **~11%** — far tighter than the isolated microbenches (flat_flight 2.54×, +controller 2.77×), because the dissolved algo is a fraction of per-sample work (handoff/lock/post/round +are common to both builds). The bigger example is a working testbed for functionality *and* optimization. + +## The two open optimization/expansion levers (maintainer-side) + +1. **const-CSE + cross-statement local promotion (synth#209)** — the composed path's remaining gap. + `flat_flight` (262 cyc ARM, current) is 61% redundant constant materializations (34 const-loads / 13 distinct; clamp + bounds `#0x7e`/`#0x7f` ×6 each) + 17 stack spills (refreshed on loom 1.1.10 + synth 0.11.29); the v0.11.27 caller-saved-preference fix nearly halved the leaves (filter 2.18→1.35×) but + barely moved the composed path (2.57→2.41×). const-CSE is the next lever. +2. **native-call ABI / `--native-pointer-abi` (synth#237, v0.11.29 in progress)** — unblocks + host-pointer primitive drop-ins (mutex, sem) by emitting wasm statics as base-independent + `.data`/`MOVW-MOVT` relocations while host-pointer args stay `base=0`. Re-measure staged + (`mutex-microbench/remeasure_wasm_lto.sh`) — one command when the flag lands. + +## Headline +The PulseEngine pipeline dissolves the C↔Rust seam at wasm-IR level and produces correct silicon +output at ~2–2.6× native (widening with composition), with LLVM-LTO-parity codegen shape. The gap is +general codegen (regalloc/const-CSE = #209), confirmed cross-target on ARM **and** RISC-V — the +single retargetable lever. Host-pointer primitive drop-ins await the native-call ABI (#237). + +> **Composed dissolved testbed (2026-06-14, G474RE):** flight_control bench with GALE_FC_WASM_LTO=ON + CONFIG_GALE_WASM_LTO_SEM=y runs algo+sem **both dissolved**, full 5-step sweep, no fault, functionally == native (drain_timeouts bench-inherent, confirmed by native comparison). In-bench **handoff: native 1374 → dissolved-sem 1661 cyc (+287, +21%)**; dissolved algo 157 both. The dissolved sem works in a composed real-bench context. + +> **Composed testbed COMPLETE (2026-06-14, G474RE):** flight_control with algo+sem+**mutex** all dissolved (GALE_FC_WASM_LTO=ON + CONFIG_GALE_WASM_LTO_SEM=y + CONFIG_GALE_WASM_LTO_MUTEX=y) — full sweep, **no fault**. In-bench: t_lock native 486 → dissolved-mutex **887 (+401, +82%)**; handoff native 1374 → dissolved-sem ~1719; algo ~146-157. The +82%/+21% in-context deltas are the synth#209 spill-reduction target. diff --git a/benches/engine_control/silicon/wasm-testbed/arch/riscv/control.h b/benches/engine_control/silicon/wasm-testbed/arch/riscv/control.h new file mode 100644 index 00000000..79c54bbf --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/arch/riscv/control.h @@ -0,0 +1,73 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * Copyright (c) 2026 PulseEngine + * + * Flight-control macro benchmark — shared types. + * + * The bench composes five Zephyr primitives (ring_buf, sem, mutex, + * msgq, condvar) on a 100 Hz fixed-rate flight-control loop. See + * docs/research/macro-bench-design.md for the design contract. + * + * Pure C, no float (CONFIG_FPU stays off) — measurements must be + * stable across builds, the algo segment must be byte-identical + * baseline vs gale, same constraint as engine_control. + */ + +#ifndef GALE_FLIGHT_CONTROL_H +#define GALE_FLIGHT_CONTROL_H + +#include + +/* + * Per-sensor-ISR sample published into the SPSC ring_buf and consumed + * by the fusion thread. Mirrors crank_sample's role in engine_control: + * carries the in-ISR cycle delta (algo) and a sequence number that + * keys the side-channel slot for handoff_cycles. Step is the sweep + * triple index (sensor_hz × contention × payload). + */ +struct imu_sample { + int16_t gyro_x; /* milli-deg/s */ + int16_t gyro_y; + int16_t gyro_z; + int16_t accel_x; /* milli-g */ + int16_t accel_y; + int16_t accel_z; + uint32_t algo_cycles; /* in-ISR filter math (t_algo - t_entry) */ + uint16_t seq; /* wraps; indexes side-channel slot */ + uint8_t step; /* sweep index (0..SWEEP_STEPS-1) */ + uint8_t _pad; +}; + +/* + * Vehicle attitude / rates — protected by the contended state mutex. + * Updated by fusion, read by controller + telemetry. Plain integers, + * no float (CONFIG_FPU off), keeps the algo deterministic across + * baseline and gale builds. + */ +struct flight_state { + int32_t pitch_mdeg; /* milli-degrees */ + int32_t roll_mdeg; + int32_t yaw_mdeg; + int32_t pitch_rate; /* milli-deg/s */ + int32_t roll_rate; + int32_t yaw_rate; + uint32_t updates; /* monotonic — fusion increments under mutex */ +}; + +/* + * Complementary-filter step: integrates gyro rates and biases toward + * the accelerometer-derived attitude. Pure integer math, no divides + * inside the ISR (the only divide is by GYRO_DT_INV_PERMILLE, taken + * outside the hot path). Identity across builds — passes engine_control's + * algo-delta-< 10 % integrity check. + */ +void filter_step(struct flight_state *st, const struct imu_sample *s); + +/* + * Trivial integer-only attitude controller. Computes a 32-bit packed + * "command" (effort encoded in 3 channels: aileron / elevator / rudder). + * Identity across builds. + */ +uint32_t controller_step(const struct flight_state *st); + +#endif /* GALE_FLIGHT_CONTROL_H */ diff --git a/benches/engine_control/silicon/wasm-testbed/arch/riscv/control_native.c b/benches/engine_control/silicon/wasm-testbed/arch/riscv/control_native.c new file mode 100644 index 00000000..e32196be --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/arch/riscv/control_native.c @@ -0,0 +1,12 @@ +#include +#define RB 20 +#define LB 20 +extern const int8_t spark_advance_table[RB][LB]; +extern const uint16_t fuel_duration_table[RB][LB]; +static inline uint8_t rb_(uint32_t r){uint32_t b=r/500;if(b>=RB)b=RB-1;return b;} +static inline uint8_t lb_(uint16_t l){uint16_t b=l/5;if(b>=LB)b=LB-1;return b;} +static inline uint32_t enr_(int16_t c){if(c>=80)return 0;if(c<=0)return 300;return (uint32_t)((80-c)*300/80);} +uint32_t control_step_native(uint32_t rpm,uint32_t load,int32_t cool,uint32_t kn){ + uint8_t r=rb_(rpm),l=lb_((uint16_t)load);int16_t a=(int16_t)spark_advance_table[r][l];a-=(int16_t)kn;if(a<0)a=0; + uint32_t bf=fuel_duration_table[r][l],e=enr_((int16_t)cool),c=bf+(bf*e/1000U);if(c>65535)c=65535; + return ((uint32_t)(uint16_t)a<<16)|(uint16_t)c;} diff --git a/benches/engine_control/silicon/wasm-testbed/arch/riscv/funccheck_main.c b/benches/engine_control/silicon/wasm-testbed/arch/riscv/funccheck_main.c new file mode 100644 index 00000000..3ea801b7 --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/arch/riscv/funccheck_main.c @@ -0,0 +1,45 @@ +/* RV32 functional regression harness: runs synth's RISC-V output for each + * dissolved leaf and asserts the verified-correct value. Catches RV32 + * miscompiles that the wasmtime/ARM-only testbed lanes miss (e.g. synth + * #232: i32.div_s overflow guard clobbered the dividend on v0.11.26). + * control_step reaches its tables via the s11 trampoline (rv_cs_call); + * filter/controller are pure-register (0 memory ops) so called directly. */ +#include +uint32_t rv_cs_call(uint32_t,uint32_t,int32_t,uint32_t); /* synth control_step via s11 tramp */ +int32_t filter_axis_decide(int32_t,int32_t,int32_t); /* synth, direct */ +uint32_t controller_step_decide(int32_t,int32_t,int32_t,int32_t,int32_t,int32_t,uint32_t); +#define UART (*(volatile uint8_t*)0x10000000u) +static void pc_(char c){UART=(uint8_t)c;} +static void ps_(const char*s){while(*s)pc_(*s++);} +static void pd_(uint32_t u){char b[12];int i=0;if(!u)b[i++]='0';while(u){b[i++]='0'+u%10;u/=10;}while(i)pc_(b[--i]);} +static void chk(const char*nm,uint32_t got,uint32_t exp){ + ps_(got==exp?"PASS ":"FAIL ");ps_(nm);ps_(" got=");pd_(got);ps_(" exp=");pd_(exp);pc_('\n'); +} +int main(void){ + /* Multi-vector coverage: each function exercised across the input edges that + * per-axis const-CSE dedup is most likely to break (saturation ±127, signed-div + * negatives, table cells). Expecteds are run_testbed.sh's verified ground truth + * (native == wasmtime == on-silicon). A const-CSE miscompile that reuses a + * clobbered constant register typically only shows on a subset of inputs, so + * single-vector coverage would miss it — hence the spread. */ + + /* filter_axis: signed mul + signed div by 1000. Zero, positive, negative. */ + chk("filter_axis(0,0,0)", (uint32_t)filter_axis_decide(0,0,0), 0u); + chk("filter_axis(1000,100,500)", (uint32_t)filter_axis_decide(1000,100,500), 1088u); + chk("filter_axis(-2000,50,-300)", (uint32_t)filter_axis_decide(-2000,50,-300), (uint32_t)(int32_t)-1917); + + /* controller_step: SAR + ±127 saturation + 8-bit pack. Zero, the packed + * mid-range vector, and an over-range vector that drives all 3 axes past the + * clamp (each axis re-materializes ±127 — the prime const-CSE dedup site). */ + chk("controller_step(0..0)", controller_step_decide(0,0,0,0,0,0,0), 0u); + chk("controller_step(6400..5)", controller_step_decide(6400,0,-12800,0,3200,0,5), 97419164u); + chk("controller_step(satclamp)", controller_step_decide(99999,99999,-99999,-99999,99999,-99999,255), + /* a=-127 e=+127 r=-127, updates=255 -> 0xFF817F81 (wasmtime-verified) */ 0xFF817F81u); + + /* control_step: 2 unsigned-const divides + 2 tables (via s11 tramp). 4 cells. */ + chk("control_step(3000,50,90,0)", rv_cs_call(3000,50,90,0), 2164988u); + chk("control_step(3000,50,40,0)", rv_cs_call(3000,50,40,0), 2165333u); + chk("control_step(3000,50,0,0)", rv_cs_call(3000,50,0,0), 2165678u); + chk("control_step(6000,80,40,3)", rv_cs_call(6000,80,40,3), 2230501u); + ps_("=== END ===\n");for(;;){} +} diff --git a/benches/engine_control/silicon/wasm-testbed/arch/riscv/fw.elf b/benches/engine_control/silicon/wasm-testbed/arch/riscv/fw.elf new file mode 100755 index 00000000..b962be29 Binary files /dev/null and b/benches/engine_control/silicon/wasm-testbed/arch/riscv/fw.elf differ diff --git a/benches/engine_control/silicon/wasm-testbed/arch/riscv/fw_cs.elf b/benches/engine_control/silicon/wasm-testbed/arch/riscv/fw_cs.elf new file mode 100755 index 00000000..aa746908 Binary files /dev/null and b/benches/engine_control/silicon/wasm-testbed/arch/riscv/fw_cs.elf differ diff --git a/benches/engine_control/silicon/wasm-testbed/arch/riscv/fw_funccheck.elf b/benches/engine_control/silicon/wasm-testbed/arch/riscv/fw_funccheck.elf new file mode 100755 index 00000000..263d1aa2 Binary files /dev/null and b/benches/engine_control/silicon/wasm-testbed/arch/riscv/fw_funccheck.elf differ diff --git a/benches/engine_control/silicon/wasm-testbed/arch/riscv/gale_tables.c b/benches/engine_control/silicon/wasm-testbed/arch/riscv/gale_tables.c new file mode 100644 index 00000000..0ceb5ff8 --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/arch/riscv/gale_tables.c @@ -0,0 +1,80 @@ +/* Auto-generated from tables.blob: spark_advance_table[20][20] (int8, +0x0) then + fuel_duration_table[20][20] (u16 LE, +0x190). Placed at linmem 0x10000; the + trampoline sets fp = &gale_tables - 0x10000 so synth's [fp+0x10000]/[fp+0x10190] hit it. */ +const unsigned char gale_tables[1200] __attribute__((aligned(4))) = { + 10,10,10,10,10,12,12,12,12,12,14,14,14,14,14,14, + 14,14,14,14,12,12,12,13,13,14,14,14,15,15,16,16, + 16,17,17,18,18,18,18,18,15,15,16,16,17,17,18,18, + 19,19,20,20,20,21,21,22,22,22,22,22,18,18,19,19, + 20,20,21,21,22,22,23,23,23,24,24,25,25,25,25,25, + 20,21,21,22,23,23,24,24,25,26,26,27,27,28,28,29, + 29,29,29,28,22,23,24,25,26,26,27,28,28,29,30,30, + 31,31,32,32,32,32,31,30,24,25,26,27,28,29,30,30, + 31,32,33,33,34,34,35,35,35,34,33,32,26,27,28,29, + 30,31,32,33,34,34,35,36,36,37,37,37,36,35,34,33, + 28,29,30,31,32,33,34,35,36,37,37,38,38,39,39,38, + 37,36,35,34,29,30,31,32,33,34,35,36,37,38,38,39, + 39,40,39,38,37,36,35,34,30,31,32,33,34,35,36,37, + 38,39,39,40,40,40,39,38,37,36,35,34,31,32,33,34, + 35,36,37,38,39,39,40,40,40,40,39,38,37,36,35,34, + 32,33,34,35,36,37,38,39,39,40,40,40,40,40,39,38, + 37,36,35,34,33,34,35,36,37,38,38,39,40,40,40,40, + 40,39,39,38,37,36,35,34,34,35,36,37,38,38,39,39, + 40,40,40,40,40,39,38,37,36,35,34,33,35,36,37,37, + 38,39,39,40,40,40,40,39,39,38,38,37,36,35,34,33, + 36,36,37,38,38,39,39,40,40,40,39,39,38,38,37,36, + 35,34,33,32,36,37,37,38,38,39,39,40,40,39,39,38, + 38,37,36,35,34,33,32,31,36,37,37,38,38,39,39,39, + 39,39,38,38,37,36,35,34,33,32,31,30,35,36,37,37, + 38,38,38,39,38,38,37,37,36,35,34,33,32,31,30,29, + 176,4,120,5,64,6,8,7,208,7,152,8,96,9,40,10, + 240,10,184,11,128,12,72,13,16,14,216,14,160,15,104,16, + 48,17,248,17,192,18,136,19,126,4,60,5,250,5,184,6, + 118,7,52,8,242,8,176,9,110,10,44,11,234,11,168,12, + 102,13,36,14,226,14,160,15,94,16,28,17,218,17,152,18, + 76,4,0,5,180,5,104,6,28,7,208,7,132,8,56,9, + 236,9,160,10,84,11,8,12,188,12,112,13,36,14,216,14, + 140,15,64,16,244,16,168,17,26,4,196,4,110,5,24,6, + 194,6,108,7,22,8,192,8,106,9,20,10,190,10,104,11, + 18,12,188,12,102,13,16,14,186,14,100,15,14,16,184,16, + 232,3,136,4,40,5,200,5,104,6,8,7,168,7,72,8, + 232,8,136,9,40,10,200,10,104,11,8,12,168,12,72,13, + 232,13,136,14,40,15,200,15,182,3,76,4,226,4,120,5, + 14,6,164,6,58,7,208,7,102,8,252,8,146,9,40,10, + 190,10,84,11,234,11,128,12,22,13,172,13,66,14,216,14, + 132,3,16,4,156,4,40,5,180,5,64,6,204,6,88,7, + 228,7,112,8,252,8,136,9,20,10,160,10,44,11,184,11, + 68,12,208,12,92,13,232,13,92,3,222,3,96,4,226,4, + 100,5,230,5,104,6,234,6,108,7,238,7,112,8,242,8, + 116,9,246,9,120,10,250,10,124,11,254,11,128,12,2,13, + 52,3,172,3,36,4,156,4,20,5,140,5,4,6,124,6, + 244,6,108,7,228,7,92,8,212,8,76,9,196,9,60,10, + 180,10,44,11,164,11,28,12,22,3,132,3,242,3,96,4, + 206,4,60,5,170,5,24,6,134,6,244,6,98,7,208,7, + 62,8,172,8,26,9,136,9,246,9,100,10,210,10,64,11, + 248,2,92,3,192,3,36,4,136,4,236,4,80,5,180,5, + 24,6,124,6,224,6,68,7,168,7,12,8,112,8,212,8, + 56,9,156,9,0,10,100,10,218,2,52,3,142,3,232,3, + 66,4,156,4,246,4,80,5,170,5,4,6,94,6,184,6, + 18,7,108,7,198,7,32,8,122,8,212,8,46,9,136,9, + 188,2,12,3,92,3,172,3,252,3,76,4,156,4,236,4, + 60,5,140,5,220,5,44,6,124,6,204,6,28,7,108,7, + 188,7,12,8,92,8,172,8,163,2,238,2,57,3,132,3, + 207,3,26,4,101,4,176,4,251,4,70,5,145,5,220,5, + 39,6,114,6,189,6,8,7,83,7,158,7,233,7,52,8, + 138,2,208,2,22,3,92,3,162,3,232,3,46,4,116,4, + 186,4,0,5,70,5,140,5,210,5,24,6,94,6,164,6, + 234,6,48,7,118,7,188,7,113,2,178,2,243,2,52,3, + 117,3,182,3,247,3,56,4,121,4,186,4,251,4,60,5, + 125,5,190,5,255,5,64,6,129,6,194,6,3,7,68,7, + 88,2,148,2,208,2,12,3,72,3,132,3,192,3,252,3, + 56,4,116,4,176,4,236,4,40,5,100,5,160,5,220,5, + 24,6,84,6,144,6,204,6,68,2,124,2,180,2,236,2, + 36,3,92,3,148,3,204,3,4,4,60,4,116,4,172,4, + 228,4,28,5,84,5,140,5,196,5,252,5,52,6,108,6, + 48,2,102,2,156,2,210,2,8,3,62,3,116,3,170,3, + 224,3,22,4,76,4,130,4,184,4,238,4,36,5,90,5, + 144,5,198,5,252,5,50,6,28,2,80,2,132,2,184,2, + 236,2,32,3,84,3,136,3,188,3,240,3,36,4,88,4, + 140,4,192,4,244,4,40,5,92,5,144,5,196,5,248,5, +}; diff --git a/benches/engine_control/silicon/wasm-testbed/arch/riscv/linker.ld b/benches/engine_control/silicon/wasm-testbed/arch/riscv/linker.ld new file mode 100644 index 00000000..49eca605 --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/arch/riscv/linker.ld @@ -0,0 +1,65 @@ +/* RISC-V Linker Script + * Generated by synth-backend-riscv + * Flash: 0x80000000 (64 KB), RAM: 0x80010000 (64 KB) + * Linear memory: 4 KB, stack: 8 KB + */ + +OUTPUT_ARCH("riscv") +ENTRY(_reset) + +MEMORY { + flash (rx) : ORIGIN = 0x80000000, LENGTH = 64K + ram (rwx) : ORIGIN = 0x80010000, LENGTH = 64K +} + +SECTIONS { + .text : { + KEEP(*(.text._reset)) + . = ALIGN(64); + KEEP(*(.text._trap_entry)) + *(.text*) + } > flash + + .rodata : { + *(.rodata*) + *(.srodata*) + . = ALIGN(4); + PROVIDE(_data_load = .); + } > flash + + .data : AT(_data_load) { + . = ALIGN(4); + PROVIDE(_data_start = .); + *(.data*) + *(.sdata*) + . = ALIGN(4); + PROVIDE(_data_end = .); + } > ram + + .bss (NOLOAD) : { + . = ALIGN(4); + PROVIDE(_bss_start = .); + *(.bss*) + *(.sbss*) + *(COMMON) + . = ALIGN(4); + PROVIDE(_bss_end = .); + } > ram + + /* Wasm linear memory — selector loads/stores use s11 = this */ + .linear_memory (NOLOAD) : ALIGN(16) { + PROVIDE(__linear_memory_base = .); + . += 4096; + PROVIDE(__linear_memory_end = .); + } > ram + + /* Stack grows down from end of RAM */ + .stack (NOLOAD) : ALIGN(16) { + . += 8192; + PROVIDE(_stack_top = .); + } > ram + + /* Global pointer — points 0x800 above .sdata for short-form RV access */ + PROVIDE(__global_pointer$ = _data_start + 0x800); + +} diff --git a/benches/engine_control/silicon/wasm-testbed/arch/riscv/main.c b/benches/engine_control/silicon/wasm-testbed/arch/riscv/main.c new file mode 100644 index 00000000..a808ff42 --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/arch/riscv/main.c @@ -0,0 +1,26 @@ +#include +#include "control.h" +int32_t filter_axis_decide(int32_t,int32_t,int32_t); +uint32_t control_step_decide(uint32_t,uint32_t,int32_t,uint32_t); +uint32_t flat_flight(struct flight_state*, const struct imu_sample*); +#define UART (*(volatile uint8_t*)0x10000000u) +static void pc_(char c){UART=(uint8_t)c;} +static void ps_(const char*s){while(*s)pc_(*s++);} +static void pd_(int32_t v){char b[12];int i=0,neg=0;uint32_t u;if(v<0){neg=1;u=-v;}else u=v;if(!u)b[i++]='0';while(u){b[i++]='0'+u%10;u/=10;}if(neg)pc_('-');while(i)pc_(b[--i]);} +static inline uint32_t rc(void){uint32_t c;__asm__ volatile("csrr %0, mcycle":"=r"(c));return c;} +static uint32_t ovh; static volatile int32_t sink; +static uint32_t meas_f(int32_t(*f)(int32_t,int32_t,int32_t),int32_t a,int32_t b,int32_t c){uint32_t best=~0u;for(int i=0;i<200;i++){uint32_t t0=rc();sink+=f(a,b,c);uint32_t t1=rc();uint32_t d=t1-t0;if(d=0;n-=4){int d=(r>>n)&0xf;pc_(d<10?'0'+d:'a'+d-10);}ps_(" (exp 0x07fdf307)\n");} + ps_("=== END ===\n");for(;;){} +} diff --git a/benches/engine_control/silicon/wasm-testbed/arch/riscv/main_cs.c b/benches/engine_control/silicon/wasm-testbed/arch/riscv/main_cs.c new file mode 100644 index 00000000..8a89ec9c --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/arch/riscv/main_cs.c @@ -0,0 +1,16 @@ +#include +uint32_t rv_cs_call(uint32_t,uint32_t,int32_t,uint32_t); /* synth control_step via s11 tramp */ +uint32_t control_step_native(uint32_t,uint32_t,int32_t,uint32_t); +#define UART (*(volatile uint8_t*)0x10000000u) +static void pc_(char c){UART=(uint8_t)c;}static void ps_(const char*s){while(*s)pc_(*s++);} +static void pd_(int32_t v){char b[12];int i=0;uint32_t u=v;if(!u)b[i++]='0';while(u){b[i++]='0'+u%10;u/=10;}while(i)pc_(b[--i]);} +static inline uint32_t rc(void){uint32_t c;__asm__ volatile("csrr %0, mcycle":"=r"(c));return c;} +int main(void){ + uint32_t s=rv_cs_call(3000,50,40,0), n=control_step_native(3000,50,40,0); + ps_("SYNTH-RV32 control_step=");pd_(s);ps_(" native=");pd_(n);ps_(" (exp 2165333)\n"); + uint32_t ovh=~0u;for(int i=0;i<200;i++){uint32_t a=rc(),b=rc();uint32_t d=b-a;if(d.loom.wasm -b riscv -t rv32imac` and link its .o in place of the +# native obj (s11 = linear-memory base; trampoline analogous to ARM's r11). +set -u +RV="${RV:-/Volumes/Home/git/zephyr/zephyr-sdk-0.17.4/riscv64-zephyr-elf/bin/riscv64-zephyr-elf-gcc}" +QEMU="${QEMU:-/opt/homebrew/bin/qemu-system-riscv32}" +SRC=../.. +synth riscv-runtime -t rv32imac --flash-origin 0x80000000 --ram-origin 0x80010000 \ + --linear-memory-size 4096 --stack-size 8192 -o . >/dev/null 2>&1 +$RV -march=rv32imac_zicsr -mabi=ilp32 -O2 -nostartfiles -nostdlib -ffreestanding -T linker.ld -I. \ + -o fw.elf startup.c main.c $SRC/filter_wasm.c $SRC/control_wasm.c $SRC/tables.c $SRC/flat_flight.c || { echo BUILD-FAIL; exit 1; } +$QEMU -machine virt -bios none -nographic -icount shift=0 -kernel fw.elf >/tmp/rv_run.txt 2>&1 & QP=$! +sleep 5; kill $QP 2>/dev/null; wait $QP 2>/dev/null +grep -E 'E,|RV-NATIVE' /tmp/rv_run.txt +echo "(qemu -icount = instruction-count proxy, NOT silicon cycles; real RV cycles via ESP32-C3/Renode)" diff --git a/benches/engine_control/silicon/wasm-testbed/arch/riscv/run_rv_funccheck.sh b/benches/engine_control/silicon/wasm-testbed/arch/riscv/run_rv_funccheck.sh new file mode 100755 index 00000000..50588b26 --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/arch/riscv/run_rv_funccheck.sh @@ -0,0 +1,35 @@ +#!/usr/bin/env bash +# RV32 FUNCTIONAL regression lane for the wasm-cross-LTO testbed. +# For each dissolved leaf: clang->wasm-ld->loom->`synth compile -b riscv`, link the +# actual RV32 output into a qemu harness, and ASSERT the verified-correct value. +# This is the lane that would have caught synth #232 (filter_axis signed-div +# miscompile on v0.11.26) automatically. Exit 0 = all RV32 outputs correct. +# Tools: clang+wasm-ld, loom, synth, riscv64-*-gcc, qemu-system-riscv32. +set -u +CLANG="${CLANG:-/opt/homebrew/opt/llvm/bin/clang}"; WASMLD="${WASMLD:-/opt/homebrew/bin/wasm-ld}" +RV="${RV:-/Volumes/Home/git/zephyr/zephyr-sdk-0.17.4/riscv64-zephyr-elf/bin/riscv64-zephyr-elf-gcc}" +QEMU="${QEMU:-/opt/homebrew/bin/qemu-system-riscv32}" +SRC=../..; t=$(mktemp -d) +echo "== RV32 funccheck (synth $(synth --version|head -1|awk '{print $2}'), loom $(loom --version|head -1|awk '{print $2}')) ==" +synth riscv-runtime -t rv32imac --flash-origin 0x80000000 --ram-origin 0x80010000 \ + --linear-memory-size 4096 --stack-size 8192 -o . >/dev/null 2>&1 +dissolve() { # name export src... + local name="$1" exp="$2"; shift 2; local objs="" + for s in "$@"; do $CLANG --target=wasm32-unknown-unknown -O2 -nostdlib -c "$SRC/$s" -o "$t/${s%.c}.o" 2>/dev/null || return 1; objs="$objs $t/${s%.c}.o"; done + $WASMLD --no-entry --export=$exp --allow-undefined --gc-sections $objs -o "$t/$name.wasm" 2>/dev/null || return 1 + loom optimize "$t/$name.wasm" --passes inline --attestation false -o "$t/$name.loom.wasm" >/dev/null 2>&1 || return 1 + synth compile "$t/$name.loom.wasm" -b riscv -t rv32imac --relocatable -o "$t/$name.o" >/dev/null 2>&1 || return 1 +} +dissolve filter filter_axis_decide filter_wasm.c || { echo "BUILD-FAIL filter"; exit 1; } +dissolve controller controller_step_decide controller_wasm.c || { echo "BUILD-FAIL controller"; exit 1; } +dissolve control control_step_decide control_wasm.c tables.c || { echo "BUILD-FAIL control"; exit 1; } +$RV -march=rv32imac_zicsr -mabi=ilp32 -O2 -nostartfiles -nostdlib -ffreestanding -T linker.ld -I. \ + -o fw_funccheck.elf startup.c funccheck_main.c rv_cs_tramp.S gale_tables.c \ + "$t/filter.o" "$t/controller.o" "$t/control.o" 2>/dev/null || { echo BUILD-FAIL link; exit 1; } +"$QEMU" -machine virt -bios none -nographic -icount shift=0 -kernel fw_funccheck.elf >/tmp/rv_fc.txt 2>&1 & p=$! +sleep 5; kill $p 2>/dev/null; wait $p 2>/dev/null +grep -E 'PASS|FAIL' /tmp/rv_fc.txt +rm -rf "$t" +if grep -q FAIL /tmp/rv_fc.txt; then echo "== RV32 FUNCCHECK: FAILURES (synth RV32 miscompile) =="; exit 1 +elif grep -q 'PASS control_step' /tmp/rv_fc.txt; then echo "== RV32 FUNCCHECK: ALL GREEN =="; exit 0 +else echo "== RV32 FUNCCHECK: no output (qemu/capture issue) =="; exit 2; fi diff --git a/benches/engine_control/silicon/wasm-testbed/arch/riscv/run_synth.sh b/benches/engine_control/silicon/wasm-testbed/arch/riscv/run_synth.sh new file mode 100755 index 00000000..4a773f1b --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/arch/riscv/run_synth.sh @@ -0,0 +1,21 @@ +#!/usr/bin/env bash +# RISC-V SYNTH path: wasm→loom→`synth -b riscv`→RV32 on qemu_riscv32. control_step via s11 table trampoline. +# Regenerates control.loom.wasm from shared sources, compiles with the riscv backend, links + runs. +# WORKING: filter_axis (direct) + control_step (s11=&gale_tables-0x10000 tramp). controller/flat_flight pending #226/v0.11.25. +set -u +RV="${RV:-/Volumes/Home/git/zephyr/zephyr-sdk-0.17.4/riscv64-zephyr-elf/bin/riscv64-zephyr-elf-gcc}" +CLANG="${CLANG:-/opt/homebrew/opt/llvm/bin/clang}"; WASMLD="${WASMLD:-/opt/homebrew/bin/wasm-ld}" +QEMU="${QEMU:-/opt/homebrew/bin/qemu-system-riscv32}"; SRC=../..; t=$(mktemp -d) +synth riscv-runtime -t rv32imac --flash-origin 0x80000000 --ram-origin 0x80010000 --linear-memory-size 4096 --stack-size 8192 -o . >/dev/null 2>&1 +# dissolve control_step from shared sources -> wasm +$CLANG --target=wasm32-unknown-unknown -O2 -nostdlib -c $SRC/control_wasm.c -o $t/c.o +$CLANG --target=wasm32-unknown-unknown -O2 -nostdlib -c $SRC/tables.c -o $t/tb.o +$WASMLD --no-entry --export=control_step_decide --allow-undefined --gc-sections $t/c.o $t/tb.o -o $t/cs.wasm +loom optimize $t/cs.wasm --passes inline --attestation false -o $t/cs.loom.wasm >/dev/null 2>&1 +synth compile $t/cs.loom.wasm -b riscv -t rv32imac --relocatable -o $t/cs_rv.o 2>&1 | grep -iE 'error|skip' && echo "control_step synth -b riscv FAILED (check synth#223/#226)" +$RV -march=rv32imac_zicsr -mabi=ilp32 -O2 -nostartfiles -nostdlib -ffreestanding -T linker.ld \ + -o fw_cs.elf startup.c main_cs.c control_native.c $SRC/tables.c gale_tables.c rv_cs_tramp.S $t/cs_rv.o 2>/dev/null || { echo BUILD-FAIL; exit 1; } +"$QEMU" -machine virt -bios none -nographic -icount shift=0 -kernel fw_cs.elf >/tmp/rvs.txt 2>&1 & p=$!; sleep 5; kill $p 2>/dev/null; wait $p 2>/dev/null +grep -E 'SYNTH-RV32|E,' /tmp/rvs.txt +rm -rf "$t" +echo "(qemu -icount proxy; control_step synth-rv32 via s11 table trampoline)" diff --git a/benches/engine_control/silicon/wasm-testbed/arch/riscv/rv_cs_tramp.S b/benches/engine_control/silicon/wasm-testbed/arch/riscv/rv_cs_tramp.S new file mode 100644 index 00000000..de90a7fe --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/arch/riscv/rv_cs_tramp.S @@ -0,0 +1,14 @@ +.section .text +.global rv_cs_call +rv_cs_call: # a0=rpm a1=load a2=cool a3=knock -> a0 (synth control_step via s11 table base) + addi sp,sp,-16 + sw ra,0(sp) + sw s11,4(sp) + la s11, gale_tables + lui t0, 0x10 + sub s11, s11, t0 # s11 = &gale_tables - 0x10000 (so [s11+0x10000+idx] hits the tables) + call control_step_decide + lw s11,4(sp) + lw ra,0(sp) + addi sp,sp,16 + ret diff --git a/benches/engine_control/silicon/wasm-testbed/arch/riscv/startup.c b/benches/engine_control/silicon/wasm-testbed/arch/riscv/startup.c new file mode 100644 index 00000000..62cd9187 --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/arch/riscv/startup.c @@ -0,0 +1,120 @@ +/* RISC-V Bare-Metal Startup + * Generated by synth-backend-riscv + * Target: RV32IMAC (16 PMP entries, FPU: false) + */ + +#include + +extern uint32_t _stack_top; +extern uint32_t __global_pointer$; +extern uint32_t __linear_memory_base; +extern uint32_t _data_start, _data_end, _data_load; +extern uint32_t _bss_start, _bss_end; +extern int main(void); + +/* Default trap handler — overridable by user code. */ +__attribute__((weak)) void synth_trap_handler( + uint32_t mcause, uint32_t mepc, uint32_t mtval) { + (void)mcause; (void)mepc; (void)mtval; + /* Default: spin so debuggers can inspect the fault. */ + while (1) { __asm__ volatile("wfi"); } +} + +__attribute__((naked, noreturn, section(".text._reset"))) +void _reset(void) { + __asm__ volatile( + /* Disable interrupts during boot. */ + "csrw mie, zero\n" + "csrw mip, zero\n" + + /* Initialize sp, gp, and the wasm linear-memory base. */ + ".option push\n" + ".option norelax\n" + "la sp, _stack_top\n" + "la gp, __global_pointer$\n" + "la s11, __linear_memory_base\n" + ".option pop\n" + + /* Install the trap vector (direct mode). */ + "la t0, _trap_entry\n" + "csrw mtvec, t0\n" + + /* Copy .data from flash to RAM. */ + "la t0, _data_load\n" + "la t1, _data_start\n" + "la t2, _data_end\n" + "1:\n" + "bgeu t1, t2, 2f\n" + "lw t3, 0(t0)\n" + "sw t3, 0(t1)\n" + "addi t0, t0, 4\n" + "addi t1, t1, 4\n" + "j 1b\n" + "2:\n" + + /* Zero .bss. */ + "la t0, _bss_start\n" + "la t1, _bss_end\n" + "3:\n" + "bgeu t0, t1, 4f\n" + "sw zero, 0(t0)\n" + "addi t0, t0, 4\n" + "j 3b\n" + "4:\n" + + /* Jump to main. If main returns, spin. */ + "call main\n" + "5: wfi\n" + "j 5b\n" + ); +} + +/* Trap entry — saves the caller-saved register set, marshals + * mcause/mepc/mtval into a0/a1/a2, and dispatches to the C handler. + */ +__attribute__((naked, aligned(4), section(".text._trap_entry"))) +void _trap_entry(void) { + __asm__ volatile( + "addi sp, sp, -64\n" + "sw ra, 0(sp)\n" + "sw t0, 4(sp)\n" + "sw t1, 8(sp)\n" + "sw t2, 12(sp)\n" + "sw a0, 16(sp)\n" + "sw a1, 20(sp)\n" + "sw a2, 24(sp)\n" + "sw a3, 28(sp)\n" + "sw a4, 32(sp)\n" + "sw a5, 36(sp)\n" + "sw a6, 40(sp)\n" + "sw a7, 44(sp)\n" + "sw t3, 48(sp)\n" + "sw t4, 52(sp)\n" + "sw t5, 56(sp)\n" + "sw t6, 60(sp)\n" + + "csrr a0, mcause\n" + "csrr a1, mepc\n" + "csrr a2, mtval\n" + "call synth_trap_handler\n" + + "lw ra, 0(sp)\n" + "lw t0, 4(sp)\n" + "lw t1, 8(sp)\n" + "lw t2, 12(sp)\n" + "lw a0, 16(sp)\n" + "lw a1, 20(sp)\n" + "lw a2, 24(sp)\n" + "lw a3, 28(sp)\n" + "lw a4, 32(sp)\n" + "lw a5, 36(sp)\n" + "lw a6, 40(sp)\n" + "lw a7, 44(sp)\n" + "lw t3, 48(sp)\n" + "lw t4, 52(sp)\n" + "lw t5, 56(sp)\n" + "lw t6, 60(sp)\n" + "addi sp, sp, 64\n" + "mret\n" + ); +} diff --git a/benches/engine_control/silicon/wasm-testbed/arm_funccheck.py b/benches/engine_control/silicon/wasm-testbed/arm_funccheck.py new file mode 100644 index 00000000..e844e0e6 --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/arm_funccheck.py @@ -0,0 +1,69 @@ +#!/usr/bin/env python3 +""" +ARM (Cortex-M4 Thumb-2) functional regression lane — the ARM analogue of +arch/riscv/run_rv_funccheck.sh. Executes synth's ARM output for the pure-register +leaves (filter_axis, controller_step) under unicorn across the same wasmtime- +verified edge vectors, so a cross-target codegen change (e.g. const-CSE applied +to the ARM pool) that miscompiles only on certain inputs is caught. control_step +on ARM is covered by arm_harness.py (it needs the table blob + fp base). + +These two leaves have 0 memory ops, so no fp/linmem/tables setup is needed. +ABI NOTE: synth's ARM output passes args in REGISTERS r0..r7 (the RISC-V a0..a7 +style), NOT AAPCS (r0-r3 + stack for arg5+). Verified by disasm: a 7-arg function +pushes {r4-r8,lr} then reads args 5-7 from the saved r4/r5/r6 slots — i.e. it +received them in r4-r6. So a >4-arg synth function called from a stock-AAPCS C +caller would get garbage for args 5+; the wasm-cross-LTO caller/trampoline must +match synth's register convention. We mirror it: all args go in r0.. sequentially +(controller_step's 7 fit r0-r6). Exit 0 = all PASS. +""" +import struct, subprocess, sys, tempfile, os +from unicorn import * +from unicorn.arm_const import * + +CLANG="/opt/homebrew/opt/llvm/bin/clang"; OBJCOPY="/opt/homebrew/opt/llvm/bin/llvm-objcopy" +CODE=0x08000000; RAM=0x20000000; SP=RAM+0x0FF00; STOP=0x08002000 +OPT="/tmp/opt3" # reuse the dissolved loom modules + +def text_bin(loom): + """dissolve already done; synth compile -> cortex-m4f .o -> raw .text bytes.""" + o=tempfile.mktemp(suffix=".o"); b=tempfile.mktemp(suffix=".bin") + r=subprocess.run(["synth","compile",loom,"--target","cortex-m4f","--all-exports", + "--relocatable","-o",o],capture_output=True,text=True) + if r.returncode!=0: raise RuntimeError("synth compile failed: "+r.stderr[:200]) + subprocess.run([OBJCOPY,"-O","binary","--only-section=.text",o,b],check=True) + data=open(b,"rb").read(); os.remove(o); os.remove(b); return data + +REGS=[UC_ARM_REG_R0,UC_ARM_REG_R1,UC_ARM_REG_R2,UC_ARM_REG_R3, + UC_ARM_REG_R4,UC_ARM_REG_R5,UC_ARM_REG_R6,UC_ARM_REG_R7] +def run(code, args): + mu=Uc(UC_ARCH_ARM, UC_MODE_THUMB|UC_MODE_MCLASS) + mu.mem_map(CODE,0x4000); mu.mem_map(RAM,0x20000) + mu.mem_write(CODE,code) + for i,a in enumerate(args): # synth ABI: args in r0..r7 (not AAPCS stack) + mu.reg_write(REGS[i], a & 0xffffffff) + mu.reg_write(UC_ARM_REG_SP, SP) + mu.reg_write(UC_ARM_REG_LR, STOP|1) + mu.emu_start(CODE|1, STOP, count=0) + return mu.reg_read(UC_ARM_REG_R0) & 0xffffffff + +U=lambda v: v & 0xffffffff +TESTS={ + "filter_axis":(f"{OPT}/filter.loom.wasm",[ + ("(0,0,0)",[0,0,0],0), + ("(1000,100,500)",[1000,100,500],1088), + ("(-2000,50,-300)",[U(-2000),50,U(-300)],U(-1917))]), + "controller_step":(f"{OPT}/controller.loom.wasm",[ + ("(0..0)",[0,0,0,0,0,0,0],0), + ("(6400..5)",[6400,0,U(-12800),0,3200,0,5],97419164), + ("(satclamp)",[99999,99999,U(-99999),U(-99999),99999,U(-99999),255],0xFF817F81)]), +} +bad=0 +for fn,(loom,vecs) in TESTS.items(): + code=text_bin(loom) + for name,args,exp in vecs: + got=run(code,args) + ok = got==U(exp) + print(f"{'PASS' if ok else 'FAIL'} {fn}{name} got={got} exp={U(exp)}") + if not ok: bad=1 +print("== ARM FUNCCHECK: %s ==" % ("ALL GREEN" if not bad else "FAILURES (synth ARM miscompile)")) +sys.exit(bad) diff --git a/benches/engine_control/silicon/wasm-testbed/arm_harness.py b/benches/engine_control/silicon/wasm-testbed/arm_harness.py new file mode 100644 index 00000000..8d4450a1 --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/arm_harness.py @@ -0,0 +1,68 @@ +#!/usr/bin/env python3 +""" +ARM-level test harness for synth output: actually executes control_step_decide +(synth's Cortex-M4 Thumb-2 code) under unicorn, with the lookup tables loaded +and fp set to the linear-memory base. Verifies the ARM output's functional +correctness directly (not just the wasm), and pins the suspected coolant-drop +to a concrete got-vs-expected at the instruction level. + +Memory model: + CODE @ 0x08000000 : control_algo.text.bin + RAM @ 0x20000000 : stack (grows down from sp) + linmem + fp(r11) = 0x20000000 (linmem base); synth reads tables at [fp+0x10000]/[fp+0x10190] + blob @ 0x20010000 : [spark int8[20][20] @+0][fuel u16[20][20] @+0x190] +AAPCS: r0=rpm r1=load r2=coolant r3=knock ; return packed (spark<<16|fuel) in r0. +""" +import struct, sys +from unicorn import * +from unicorn.arm_const import * + +CODE_BASE = 0x08000000 +RAM_BASE = 0x20000000 +RAM_SIZE = 0x20000 # 128 KB +FP = RAM_BASE # linmem base +BLOB_ADDR = RAM_BASE + 0x10000 +SP = RAM_BASE + 0x0FF00 +STOP = 0x08001000 # sentinel return address (in mapped code region) + +code = open("control_algo.text.bin","rb").read() +blob = open("tables.blob","rb").read() + +def run(rpm, load, coolant, knock): + mu = Uc(UC_ARCH_ARM, UC_MODE_THUMB | UC_MODE_MCLASS) + mu.mem_map(CODE_BASE, 0x2000) + mu.mem_map(RAM_BASE, RAM_SIZE) + mu.mem_write(CODE_BASE, code) + mu.mem_write(BLOB_ADDR, blob) + mu.reg_write(UC_ARM_REG_R0, rpm & 0xffffffff) + mu.reg_write(UC_ARM_REG_R1, load & 0xffffffff) + mu.reg_write(UC_ARM_REG_R2, coolant & 0xffffffff) + mu.reg_write(UC_ARM_REG_R3, knock & 0xffffffff) + mu.reg_write(UC_ARM_REG_SP, SP) + mu.reg_write(UC_ARM_REG_R11, FP) + mu.reg_write(UC_ARM_REG_LR, STOP | 1) # thumb bit + mu.emu_start(CODE_BASE | 1, STOP, count=0) + r0 = mu.reg_read(UC_ARM_REG_R0) + return r0 & 0xffffffff + +# (rpm, load, coolant, knock) -> expected packed (from native reference) +VEC = [ + (3000, 50, 90, 0, 0x002108FC), # hot: enrich 0 + (3000, 50, 40, 0, 0x00210A55), # mid coolant: enrich 150 -> fuel 2645 (DISCRIMINATOR) + (3000, 50, 0, 0, 0x00210BAE), # cold: enrich 300 + (6000, 80, 40, 3, 0x002208E5), +] +bad = 0 +for rpm, load, cool, knock, exp in VEC: + try: + got = run(rpm, load, cool, knock) + except UcError as e: + print(f"({rpm},{load},{cool},{knock}) -> UC ERROR {e}"); bad += 1; continue + gs, gf = (got>>16)&0xffff, got&0xffff + es, ef = (exp>>16)&0xffff, exp&0xffff + ok = (got == exp) + print(f"[{'OK ' if ok else 'BAD'}] ({rpm},{load},{cool},{knock}) " + f"got=0x{got:08x}(s{gs}/f{gf}) exp=0x{exp:08x}(s{es}/f{ef})") + if not ok: bad += 1 +print("ALL PASS" if bad == 0 else f"{bad} MISMATCH") +sys.exit(1 if bad else 0) diff --git a/benches/engine_control/silicon/wasm-testbed/capture_serial.py b/benches/engine_control/silicon/wasm-testbed/capture_serial.py new file mode 100755 index 00000000..bc287e0d --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/capture_serial.py @@ -0,0 +1,9 @@ +#!/usr/bin/env python3 +"""Reliable G474RE serial capture. cat/stty misses boot output (0 bytes ~50% of +runs); pyserial captures every time. Start this FIRST, then `west flash`. +Port: lex-sort-first /dev/cu.usbmodem* is the ST-LINK VCP (do not hardcode).""" +import glob, serial, sys +port = sorted(glob.glob("/dev/cu.usbmodem*"))[0] +s = serial.Serial(port, 115200, timeout=float(sys.argv[1]) if len(sys.argv) > 1 else 14) +d = s.read(8000) +sys.stdout.write(d.decode(errors="replace") if d else f"0 bytes from {port}\n") diff --git a/benches/engine_control/silicon/wasm-testbed/control_step-microbench/CMakeLists.txt b/benches/engine_control/silicon/wasm-testbed/control_step-microbench/CMakeLists.txt new file mode 100644 index 00000000..6db4a40c --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/control_step-microbench/CMakeLists.txt @@ -0,0 +1,8 @@ +cmake_minimum_required(VERSION 3.20.0) +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(control_step_bench) +target_sources(app PRIVATE src/main.c) +# libcs.a = synth control_step body (synth_cs_body, r11-relative table reads) + cs_tramp.o +# (r11=&wasm_linmem; tables populated at offset 65536/65936) + native ref (control_wasm.c) + tables.c. +# Built by build.sh. Buffer-harness model (fp=linmem base), same as flat_flight-microbench. +target_link_libraries(app PRIVATE ${GALE_CS_LIB}) diff --git a/benches/engine_control/silicon/wasm-testbed/control_step-microbench/RESULT-2026-06-05-g474re.txt b/benches/engine_control/silicon/wasm-testbed/control_step-microbench/RESULT-2026-06-05-g474re.txt new file mode 100644 index 00000000..c90a1cd5 --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/control_step-microbench/RESULT-2026-06-05-g474re.txt @@ -0,0 +1,4 @@ +*** Booting Zephyr OS build v4.4.0-7-g719cc4890346 *** +SELFCHECK synth=2165333 native=2165333 exp=2165333 OK +E,control_step,synth=156,native=67 +=== END === diff --git a/benches/engine_control/silicon/wasm-testbed/control_step-microbench/RESULT-2026-06-13-g474re.txt b/benches/engine_control/silicon/wasm-testbed/control_step-microbench/RESULT-2026-06-13-g474re.txt new file mode 100644 index 00000000..c86ca511 --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/control_step-microbench/RESULT-2026-06-13-g474re.txt @@ -0,0 +1,7 @@ +*** Booting Zephyr OS build v4.4.0-7-g719cc4890346 *** +SELFCHECK synth=2165333 native=2165333 exp=2165333 OK +E,control_step,synth=151,native=67 +=== END === +# synth 0.11.40 + loom 1.1.13, G474RE DWT@170MHz. 151/67 = 2.25x. +# vs prior 156/67 (v0.11.33/34, RESULT-2026-06-05) -> -5 cyc (~3%) from codegen improvements. +# functionally correct (SELFCHECK 2165333). Reproducible: ./build.sh + flash + capture. diff --git a/benches/engine_control/silicon/wasm-testbed/control_step-microbench/build.sh b/benches/engine_control/silicon/wasm-testbed/control_step-microbench/build.sh new file mode 100755 index 00000000..7cadf16b --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/control_step-microbench/build.sh @@ -0,0 +1,22 @@ +#!/usr/bin/env bash +# control_step (engine algo, 4 scalar args + 2 lookup tables) ARM-silicon microbench. +# Tables live in wasm linmem at offset 65536 (spark 400B) + 65936 (fuel 800B); the harness +# copies them into a RAM buffer and the r11=&buffer trampoline addresses them ([r11+offset]). +# Current (loom 1.1.10 + synth 0.11.33): synth=156 / native=67 = 2.33x (G474RE, SELFCHECK 2165333). +set -euo pipefail +SYNTH="${SYNTH:-synth}"; CLANG=/opt/homebrew/opt/llvm/bin/clang; WASMLD=/opt/homebrew/bin/wasm-ld +TC=/Volumes/Home/zephyr-sdk/zephyr-sdk-1.0.1/gnu/arm-zephyr-eabi/bin/arm-zephyr-eabi +WT=$(cd "$(dirname "$0")/.." && pwd); HERE=$(cd "$(dirname "$0")" && pwd); t=$(mktemp -d) +$CLANG --target=wasm32-unknown-unknown -O2 -nostdlib -c "$WT/control_wasm.c" -o "$t/cs.o" +$CLANG --target=wasm32-unknown-unknown -O2 -nostdlib -c "$WT/tables.c" -o "$t/tb.o" +$WASMLD --no-entry --export=control_step_decide --allow-undefined --gc-sections "$t/cs.o" "$t/tb.o" -o "$t/cs.wasm" +loom optimize "$t/cs.wasm" --passes inline --attestation false -o "$t/cs.loom.wasm" >/dev/null +"$SYNTH" compile "$t/cs.loom.wasm" --target cortex-m4f --all-exports --relocatable -o "$t/cs.o2" +"$TC-objcopy" --redefine-sym control_step_decide=synth_cs_body "$t/cs.o2" "$t/cs_body.o" +"$TC-gcc" -mcpu=cortex-m4 -mthumb -c "$HERE/cs_tramp.S" -o "$t/cs_tramp.o" +"$TC-gcc" -mcpu=cortex-m4 -mthumb -O2 -c "$WT/control_wasm.c" -Dcontrol_step_decide=n_control_step -o "$t/cs_native.o" +"$TC-gcc" -mcpu=cortex-m4 -mthumb -O2 -c "$WT/tables.c" -o "$t/cs_tables.o" +"$TC-ar" rcs "$t/libcs.a" "$t/cs_body.o" "$t/cs_tramp.o" "$t/cs_native.o" "$t/cs_tables.o" +export ZEPHYR_BASE=/Volumes/Home/git/pulseengine/zephyr ZEPHYR_SDK_INSTALL_DIR=/Volumes/Home/zephyr-sdk/zephyr-sdk-1.0.1 +west build -b nucleo_g474re -d "$t/build" -p always "$HERE" -- -DGALE_CS_LIB="$t/libcs.a" >/dev/null 2>&1 +echo "built: $t/build/zephyr/zephyr.elf (flash + capture for E,control_step,synth=N,native=M)" diff --git a/benches/engine_control/silicon/wasm-testbed/control_step-microbench/cs_tramp.S b/benches/engine_control/silicon/wasm-testbed/control_step-microbench/cs_tramp.S new file mode 100644 index 00000000..81c7b391 --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/control_step-microbench/cs_tramp.S @@ -0,0 +1,14 @@ + .syntax unified + .thumb + .section .text.cs_tramp,"ax",%progbits + .global control_step_decide + .thumb_func +control_step_decide: + push {r11, lr} + movw r11, :lower16:wasm_linmem + movt r11, :upper16:wasm_linmem + movw r12, :lower16:synth_cs_body + movt r12, :upper16:synth_cs_body + orr r12, r12, #1 + blx r12 + pop {r11, pc} diff --git a/benches/engine_control/silicon/wasm-testbed/control_step-microbench/prj.conf b/benches/engine_control/silicon/wasm-testbed/control_step-microbench/prj.conf new file mode 100644 index 00000000..5b8d9300 --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/control_step-microbench/prj.conf @@ -0,0 +1,5 @@ +CONFIG_PRINTK=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_MAIN_STACK_SIZE=2048 diff --git a/benches/engine_control/silicon/wasm-testbed/control_step-microbench/src/main.c b/benches/engine_control/silicon/wasm-testbed/control_step-microbench/src/main.c new file mode 100644 index 00000000..51fbcd16 --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/control_step-microbench/src/main.c @@ -0,0 +1,27 @@ +#include +#include +#include +#define DEMCR (*(volatile uint32_t*)0xE000EDFCu) +#define DWT_CTRL (*(volatile uint32_t*)0xE0001000u) +#define DWT_CYCCNT (*(volatile uint32_t*)0xE0001004u) +typedef uint32_t (*c4)(uint32_t,uint32_t,int32_t,uint32_t); +extern uint32_t control_step_decide(uint32_t,uint32_t,int32_t,uint32_t); /* tramp->synth */ +extern uint32_t n_control_step(uint32_t,uint32_t,int32_t,uint32_t); /* native */ +/* wasm linmem: tables live at offset 65536 (spark 400B) + 65936 (fuel 800B) */ +uint8_t wasm_linmem[0x10A00] __attribute__((aligned(8))); +extern const int8_t spark_advance_table[20][20]; +extern const uint16_t fuel_duration_table[20][20]; +static inline void dwt(void){DEMCR|=(1u<<24);DWT_CYCCNT=0;DWT_CTRL|=1u;} +static uint32_t m(c4 fn,volatile uint32_t*s){uint32_t b=~0u;for(int i=0;i<200;i++){uint32_t t0=DWT_CYCCNT;uint32_t r=fn(3000,50,40,0);uint32_t t1=DWT_CYCCNT;*s+=r;uint32_t d=t1-t0;if(dloom->synth route we want a pure scalar + * signature (no host pointer deref) so the only memory the synth output + * touches is the embedded lookup tables (wasm data segment). Outputs are + * packed into a u32: spark_advance (i16) in the high half, fuel (u16) low. + * + * Exercises synth codegen paths the `decide` primitive did NOT: + * - integer division by constants (rpm/500, load/5, *300/80, *enrich/1000) + * - reads of a static const data segment (the two lookup tables) + */ +#include + +#define RPM_BINS 20 +#define LOAD_BINS 20 + +extern const int8_t spark_advance_table[RPM_BINS][LOAD_BINS]; +extern const uint16_t fuel_duration_table[RPM_BINS][LOAD_BINS]; + +static inline uint8_t rpm_bin(uint32_t rpm) +{ + uint32_t b = rpm / 500; + if (b >= RPM_BINS) { + b = RPM_BINS - 1; + } + return (uint8_t)b; +} + +static inline uint8_t load_bin(uint16_t load_pct) +{ + uint16_t b = load_pct / 5; + if (b >= LOAD_BINS) { + b = LOAD_BINS - 1; + } + return (uint8_t)b; +} + +static inline uint32_t coolant_enrichment_permille(int16_t coolant_c) +{ + if (coolant_c >= 80) { + return 0; + } + if (coolant_c <= 0) { + return 300; + } + return (uint32_t)((80 - coolant_c) * 300 / 80); +} + +__attribute__((export_name("control_step_decide"))) +uint32_t control_step_decide(uint32_t rpm, uint32_t load_pct, + int32_t coolant_c, uint32_t knock_retard) +{ + uint8_t rb = rpm_bin(rpm); + uint8_t lb = load_bin((uint16_t)load_pct); + + int16_t advance = (int16_t)spark_advance_table[rb][lb]; + advance -= (int16_t)knock_retard; + if (advance < 0) { + advance = 0; + } + + uint32_t base_fuel = (uint32_t)fuel_duration_table[rb][lb]; + uint32_t enrich = coolant_enrichment_permille((int16_t)coolant_c); + uint32_t corrected = base_fuel + (base_fuel * enrich / 1000U); + if (corrected > UINT16_MAX) { + corrected = UINT16_MAX; + } + + return ((uint32_t)(uint16_t)advance << 16) | (uint32_t)(uint16_t)corrected; +} diff --git a/benches/engine_control/silicon/wasm-testbed/controller-microbench/CMakeLists.txt b/benches/engine_control/silicon/wasm-testbed/controller-microbench/CMakeLists.txt new file mode 100644 index 00000000..9101f430 --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/controller-microbench/CMakeLists.txt @@ -0,0 +1,7 @@ +cmake_minimum_required(VERSION 3.20.0) +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(controller_bench) +target_sources(app PRIVATE src/main.c) +# libctl.a = synth controller_step body (renamed synth_ctl_body) + ctl_tramp.o (AAPCS->r0-r7 shuffle). +# Built by build.sh; pass its path via -DGALE_CTL_LIB=... +target_link_libraries(app PRIVATE ${GALE_CTL_LIB}) diff --git a/benches/engine_control/silicon/wasm-testbed/controller-microbench/RESULT-2026-06-04-g474re.txt b/benches/engine_control/silicon/wasm-testbed/controller-microbench/RESULT-2026-06-04-g474re.txt new file mode 100644 index 00000000..a5ee61e8 --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/controller-microbench/RESULT-2026-06-04-g474re.txt @@ -0,0 +1,5 @@ +*** Booting Zephyr OS build v4.4.0-7-g719cc4890346 *** +SELFCHECK synth=0x05e33e81 native=0x05e33e81 MATCH +E,controller_step,synth=169,native=61 +SINK=856795536 ovh=1 +=== END === diff --git a/benches/engine_control/silicon/wasm-testbed/controller-microbench/RESULT-2026-06-13-g474re-v0.11.41.txt b/benches/engine_control/silicon/wasm-testbed/controller-microbench/RESULT-2026-06-13-g474re-v0.11.41.txt new file mode 100644 index 00000000..e94a1a9e --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/controller-microbench/RESULT-2026-06-13-g474re-v0.11.41.txt @@ -0,0 +1,5 @@ +SELFCHECK synth=0x05e33e81 native=0x05e33e81 MATCH +E,controller_step,synth=150,native=61 +=== END === +# synth 0.11.41 + loom 1.1.13, G474RE. 150/61 = 2.46x. Down from 169 (v0.11.30); matches summary. +# body 99 insns: 6 flag-fold round-trips (compare->select), only 3 [sp] spills -> flag-fold-dominated. diff --git a/benches/engine_control/silicon/wasm-testbed/controller-microbench/build.sh b/benches/engine_control/silicon/wasm-testbed/controller-microbench/build.sh new file mode 100755 index 00000000..605d1e1d --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/controller-microbench/build.sh @@ -0,0 +1,18 @@ +#!/usr/bin/env bash +# controller_step (7-arg value fn) ARM-silicon microbench. synth passes args in r0-r7; +# ctl_tramp.S shuffles AAPCS (r0-r3 + stack) into r0-r7. Result: synth=169/native=61=2.77x (G474RE). +set -euo pipefail +SYNTH="${SYNTH:-synth}"; CLANG=/opt/homebrew/opt/llvm/bin/clang; WASMLD=/opt/homebrew/bin/wasm-ld +TC=/Volumes/Home/zephyr-sdk/zephyr-sdk-1.0.1/gnu/arm-zephyr-eabi/bin/arm-zephyr-eabi +WT=$(cd "$(dirname "$0")/.." && pwd); HERE=$(cd "$(dirname "$0")" && pwd) +t=$(mktemp -d) +$CLANG --target=wasm32-unknown-unknown -O2 -nostdlib -c "$WT/controller_wasm.c" -o "$t/c.o" +$WASMLD --no-entry --export=controller_step_decide --allow-undefined --gc-sections "$t/c.o" -o "$t/c.wasm" +loom optimize "$t/c.wasm" --passes inline --attestation false -o "$t/c.loom.wasm" >/dev/null +"$SYNTH" compile "$t/c.loom.wasm" --target cortex-m4f --all-exports --relocatable -o "$t/ctl.o" +"$TC-objcopy" --redefine-sym controller_step_decide=synth_ctl_body "$t/ctl.o" "$t/ctl_body.o" +"$TC-gcc" -mcpu=cortex-m4 -mthumb -c "$HERE/ctl_tramp.S" -o "$t/ctl_tramp.o" +"$TC-ar" rcs "$t/libctl.a" "$t/ctl_body.o" "$t/ctl_tramp.o" +export ZEPHYR_BASE=/Volumes/Home/git/pulseengine/zephyr ZEPHYR_SDK_INSTALL_DIR=/Volumes/Home/zephyr-sdk/zephyr-sdk-1.0.1 +west build -b nucleo_g474re -d "$t/build" -p always "$HERE" -- -DGALE_CTL_LIB="$t/libctl.a" >/dev/null 2>&1 +echo "built: $t/build/zephyr/zephyr.elf (flash + capture for E,controller_step,synth=N,native=M)" diff --git a/benches/engine_control/silicon/wasm-testbed/controller-microbench/ctl_tramp.S b/benches/engine_control/silicon/wasm-testbed/controller-microbench/ctl_tramp.S new file mode 100644 index 00000000..54c79bb5 --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/controller-microbench/ctl_tramp.S @@ -0,0 +1,15 @@ + .syntax unified + .thumb + .section .text.ctl_tramp,"ax",%progbits + .global controller_step_decide + .thumb_func +controller_step_decide: + push {r3, r4, r5, r6, r7, lr} @ 24B, 8-byte aligned; r3(arg4) preserved untouched + ldr r4, [sp, #24] @ arg5 = yaw_mdeg + ldr r5, [sp, #28] @ arg6 = yaw_rate + ldr r6, [sp, #32] @ arg7 = updates + movw r7, :lower16:synth_ctl_body + movt r7, :upper16:synth_ctl_body + orr r7, r7, #1 @ thumb bit (synth#170: no $t) + blx r7 + pop {r3, r4, r5, r6, r7, pc} diff --git a/benches/engine_control/silicon/wasm-testbed/controller-microbench/prj.conf b/benches/engine_control/silicon/wasm-testbed/controller-microbench/prj.conf new file mode 100644 index 00000000..5b8d9300 --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/controller-microbench/prj.conf @@ -0,0 +1,5 @@ +CONFIG_PRINTK=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_MAIN_STACK_SIZE=2048 diff --git a/benches/engine_control/silicon/wasm-testbed/controller-microbench/src/main.c b/benches/engine_control/silicon/wasm-testbed/controller-microbench/src/main.c new file mode 100644 index 00000000..b0542080 --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/controller-microbench/src/main.c @@ -0,0 +1,35 @@ +/* controller_step (7-arg value fn) wasm-cross-LTO vs native on G474RE silicon. + * synth passes args in r0-r7; ctl_tramp.S shuffles AAPCS->r0-r7. DWT min/200, overhead-subtracted. */ +#include +#include +#define DEMCR (*(volatile uint32_t*)0xE000EDFCu) +#define DWT_CTRL (*(volatile uint32_t*)0xE0001000u) +#define DWT_CYCCNT (*(volatile uint32_t*)0xE0001004u) +typedef uint32_t (*c7_t)(int32_t,int32_t,int32_t,int32_t,int32_t,int32_t,uint32_t); +extern uint32_t controller_step_decide(int32_t,int32_t,int32_t,int32_t,int32_t,int32_t,uint32_t); /* tramp->synth */ + +__attribute__((noinline)) +uint32_t n_controller(int32_t rm,int32_t rr,int32_t pm,int32_t pr,int32_t ym,int32_t yr,uint32_t u){ + int32_t a=-(rm>>6)-(rr>>7), e=-(pm>>6)-(pr>>7), r=-(ym>>6)-(yr>>7); + if(a>127)a=127; if(a<-127)a=-127; if(e>127)e=127; if(e<-127)e=-127; if(r>127)r=127; if(r<-127)r=-127; + return ((uint32_t)(uint8_t)(int8_t)a)|((uint32_t)(uint8_t)(int8_t)e<<8)|((uint32_t)(uint8_t)(int8_t)r<<16)|((uint32_t)(u&0xFFu)<<24); +} +static inline void dwt_init(void){ DEMCR|=(1u<<24); DWT_CYCCNT=0; DWT_CTRL|=1u; } +static uint32_t m7(c7_t fn,volatile uint32_t*s){ + uint32_t best=0xFFFFFFFFu; + for(int i=0;i<200;i++){ uint32_t t0=DWT_CYCCNT; uint32_t r=fn(8000,256,-4000,128,2000,-256,5); uint32_t t1=DWT_CYCCNT; *s+=r; uint32_t d=t1-t0; if(d + +__attribute__((export_name("controller_step_decide"))) +uint32_t controller_step_decide(int32_t roll_mdeg, int32_t roll_rate, + int32_t pitch_mdeg, int32_t pitch_rate, + int32_t yaw_mdeg, int32_t yaw_rate, + uint32_t updates) +{ + int32_t aileron = -(roll_mdeg >> 6) - (roll_rate >> 7); + int32_t elevator = -(pitch_mdeg >> 6) - (pitch_rate >> 7); + int32_t rudder = -(yaw_mdeg >> 6) - (yaw_rate >> 7); + + if (aileron > 127) aileron = 127; + if (aileron < -127) aileron = -127; + if (elevator > 127) elevator = 127; + if (elevator < -127) elevator = -127; + if (rudder > 127) rudder = 127; + if (rudder < -127) rudder = -127; + + uint32_t cmd = ((uint32_t)(uint8_t)(int8_t)aileron ) + | ((uint32_t)(uint8_t)(int8_t)elevator << 8) + | ((uint32_t)(uint8_t)(int8_t)rudder << 16) + | ((uint32_t)(updates & 0xFFu) << 24); + return cmd; +} diff --git a/benches/engine_control/silicon/wasm-testbed/filter_wasm.c b/benches/engine_control/silicon/wasm-testbed/filter_wasm.c new file mode 100644 index 00000000..4a99633f --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/filter_wasm.c @@ -0,0 +1,16 @@ +/* + * Value-in/value-out slice of flight_control's filter_step() hot math: + * one axis of the complementary filter. new = (gyro_term*980 + accel*20)/1000 + * where gyro_term = prev + gyro. Pure signed integer: exercises SIGNED + * multiply + SIGNED division by the constant 1000 (sdiv) — a path neither the + * engine algorithm (udiv) nor the controller (shifts only) covered. + */ +#include +#define ALPHA_GYRO_PERMILLE 980 +#define ALPHA_ACCEL_PERMILLE 20 +__attribute__((export_name("filter_axis_decide"))) +int32_t filter_axis_decide(int32_t prev_mdeg, int32_t gyro, int32_t accel) +{ + int32_t gyro_term = prev_mdeg + gyro; + return (gyro_term * ALPHA_GYRO_PERMILLE + accel * ALPHA_ACCEL_PERMILLE) / 1000; +} diff --git a/benches/engine_control/silicon/wasm-testbed/flat_flight-microbench/CMakeLists.txt b/benches/engine_control/silicon/wasm-testbed/flat_flight-microbench/CMakeLists.txt new file mode 100644 index 00000000..e7b0be1f --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/flat_flight-microbench/CMakeLists.txt @@ -0,0 +1,7 @@ +cmake_minimum_required(VERSION 3.20.0) +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(flat_flight_bench) +target_sources(app PRIVATE src/main.c) +# libff.a = synth flat_flight body (renamed synth_flat_flight_body) + ff_tramp.o +# (fp=&wasm_linmem base; 0 statics so this is faithful). Path via -DGALE_FF_LIB or edit here. +target_link_libraries(app PRIVATE ${GALE_FF_LIB}) diff --git a/benches/engine_control/silicon/wasm-testbed/flat_flight-microbench/RESULT-2026-06-04-g474re.txt b/benches/engine_control/silicon/wasm-testbed/flat_flight-microbench/RESULT-2026-06-04-g474re.txt new file mode 100644 index 00000000..405a8f48 --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/flat_flight-microbench/RESULT-2026-06-04-g474re.txt @@ -0,0 +1,5 @@ +*** Booting Zephyr OS build v4.4.0-7-g719cc4890346 *** +SELFCHECK synth=0x07fdf307 native=0x07fdf307 exp=0x07fdf307 OK +E,flat_flight,synth=262,native=103 (ovh=1) +SINK=2093726448 +=== END === diff --git a/benches/engine_control/silicon/wasm-testbed/flat_flight-microbench/RESULT-2026-06-10-g474re-v0.11.35.txt b/benches/engine_control/silicon/wasm-testbed/flat_flight-microbench/RESULT-2026-06-10-g474re-v0.11.35.txt new file mode 100644 index 00000000..7909c653 --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/flat_flight-microbench/RESULT-2026-06-10-g474re-v0.11.35.txt @@ -0,0 +1,6 @@ +*** Booting Zephyr OS build v4.4.0-7-g719cc4890346 *** +SELFCHECK synth=0x07fdf307 native=0x07fdf307 exp=0x07fdf307 OK +E,flat_flight,synth=241,native=103 (ovh=1) +SINK=2093726448 +=== END === +# synth v0.11.35 (#285 spill-cost ranking), loom 1.1.10. Cycle-neutral vs v0.11.34 (241), code 560->526B (-6%). diff --git a/benches/engine_control/silicon/wasm-testbed/flat_flight-microbench/RESULT-2026-06-13-g474re-v0.11.40.txt b/benches/engine_control/silicon/wasm-testbed/flat_flight-microbench/RESULT-2026-06-13-g474re-v0.11.40.txt new file mode 100644 index 00000000..4c95323e --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/flat_flight-microbench/RESULT-2026-06-13-g474re-v0.11.40.txt @@ -0,0 +1,7 @@ +*** Booting Zephyr OS build v4.4.0-7-g719cc4890346 *** +SELFCHECK synth=0x07fdf307 native=0x07fdf307 exp=0x07fdf307 OK +E,flat_flight,synth=241,native=103 (ovh=1) +SINK=2093726448 +=== END === +# synth 0.11.40 + loom 1.1.13, G474RE. 241/103 = 2.34x. Stable vs v0.11.35 (241); down from 262 (v0.11.30). +# functionally correct (SELFCHECK 0x07fdf307). Composed flight algo (filter_step+controller_step). diff --git a/benches/engine_control/silicon/wasm-testbed/flat_flight-microbench/build.sh b/benches/engine_control/silicon/wasm-testbed/flat_flight-microbench/build.sh new file mode 100755 index 00000000..f960e171 --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/flat_flight-microbench/build.sh @@ -0,0 +1,18 @@ +#!/usr/bin/env bash +# flat_flight (composed flight algo) ARM-silicon microbench = Track-A frozen regression target (#209). +# Buffer-harness (fp=&wasm_linmem): flat_flight takes 2 wasm-linmem ptrs + a linmem stack; 0 statics. +# Baseline (loom 1.1.10 + synth 0.11.30): synth=262 / native=103 = 2.54x (G474RE, SELFCHECK 0x07fdf307). +set -euo pipefail +SYNTH="${SYNTH:-synth}"; CLANG=/opt/homebrew/opt/llvm/bin/clang; WASMLD=/opt/homebrew/bin/wasm-ld +TC=/Volumes/Home/zephyr-sdk/zephyr-sdk-1.0.1/gnu/arm-zephyr-eabi/bin/arm-zephyr-eabi +WT=$(cd "$(dirname "$0")/.." && pwd); HERE=$(cd "$(dirname "$0")" && pwd); t=$(mktemp -d) +$CLANG --target=wasm32-unknown-unknown -O2 -nostdlib -I"$WT/arch/riscv" -c "$WT/flat_flight.c" -o "$t/ff.o" +$WASMLD --no-entry --export=flat_flight --allow-undefined --gc-sections "$t/ff.o" -o "$t/ff.wasm" +loom optimize "$t/ff.wasm" --passes inline --attestation false -o "$t/ff.loom.wasm" >/dev/null +"$SYNTH" compile "$t/ff.loom.wasm" --target cortex-m4f --all-exports --relocatable -o "$t/ff.o2" +"$TC-objcopy" --redefine-sym flat_flight=synth_flat_flight_body "$t/ff.o2" "$t/ff_body.o" +"$TC-gcc" -mcpu=cortex-m4 -mthumb -c "$HERE/ff_tramp.S" -o "$t/ff_tramp.o" +"$TC-ar" rcs "$t/libff.a" "$t/ff_body.o" "$t/ff_tramp.o" +export ZEPHYR_BASE=/Volumes/Home/git/pulseengine/zephyr ZEPHYR_SDK_INSTALL_DIR=/Volumes/Home/zephyr-sdk/zephyr-sdk-1.0.1 +west build -b nucleo_g474re -d "$t/build" -p always "$HERE" -- -DGALE_FF_LIB="$t/libff.a" >/dev/null 2>&1 +echo "built: $t/build/zephyr/zephyr.elf (flash + capture for E,flat_flight,synth=N,native=M)" diff --git a/benches/engine_control/silicon/wasm-testbed/flat_flight-microbench/ff_tramp.S b/benches/engine_control/silicon/wasm-testbed/flat_flight-microbench/ff_tramp.S new file mode 100644 index 00000000..ea86ee7a --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/flat_flight-microbench/ff_tramp.S @@ -0,0 +1,14 @@ + .syntax unified + .thumb + .section .text.ff_tramp,"ax",%progbits + .global synth_flat_flight_buf + .thumb_func +synth_flat_flight_buf: @ (uint32_t st_off=r0, uint32_t s_off=r1) + push {r11, lr} + movw r11, :lower16:wasm_linmem + movt r11, :upper16:wasm_linmem + movw r2, :lower16:synth_flat_flight_body + movt r2, :upper16:synth_flat_flight_body + orr r2, r2, #1 @ thumb bit (synth#170) + blx r2 + pop {r11, pc} diff --git a/benches/engine_control/silicon/wasm-testbed/flat_flight-microbench/prj.conf b/benches/engine_control/silicon/wasm-testbed/flat_flight-microbench/prj.conf new file mode 100644 index 00000000..5b8d9300 --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/flat_flight-microbench/prj.conf @@ -0,0 +1,5 @@ +CONFIG_PRINTK=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_MAIN_STACK_SIZE=2048 diff --git a/benches/engine_control/silicon/wasm-testbed/flat_flight-microbench/src/main.c b/benches/engine_control/silicon/wasm-testbed/flat_flight-microbench/src/main.c new file mode 100644 index 00000000..ce9b19cd --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/flat_flight-microbench/src/main.c @@ -0,0 +1,51 @@ +/* flat_flight (composed flight algo) ARM-silicon microbench — the Track-A frozen target. + * synth flat_flight takes 2 wasm linmem ptrs (st,s) + uses a linmem stack; called via + * ff_tramp.S which sets r11=&wasm_linmem (fp=linmem-base model, 0 statics so this suffices). + * native = same logic on real pointers. DWT min/200, overhead-subtracted. */ +#include +#include +struct imu_sample { int16_t gyro_x,gyro_y,gyro_z,accel_x,accel_y,accel_z; uint32_t algo_cycles; uint16_t seq; uint8_t step,_pad; }; +struct flight_state { int32_t pitch_mdeg,roll_mdeg,yaw_mdeg,pitch_rate,roll_rate,yaw_rate; uint32_t updates; }; +#define DEMCR (*(volatile uint32_t*)0xE000EDFCu) +#define DWT_CTRL (*(volatile uint32_t*)0xE0001000u) +#define DWT_CYCCNT (*(volatile uint32_t*)0xE0001004u) + +/* the wasm linear memory (64KB; stack lives at top 65536, structs placed low). r11 base. */ +uint8_t wasm_linmem[65536] __attribute__((aligned(8))); +extern uint32_t synth_flat_flight_buf(uint32_t st_off, uint32_t s_off); /* tramp -> synth body */ + +__attribute__((noinline)) +uint32_t n_flat_flight(struct flight_state *st, const struct imu_sample *s){ + int32_t ap=s->accel_x, ar=s->accel_y; + int32_t gp=st->pitch_mdeg+s->gyro_y, gr=st->roll_mdeg+s->gyro_x, gy=st->yaw_mdeg+s->gyro_z; + st->pitch_mdeg=(gp*980+ap*20)/1000; st->roll_mdeg=(gr*980+ar*20)/1000; st->yaw_mdeg=gy; + st->pitch_rate=s->gyro_y; st->roll_rate=s->gyro_x; st->yaw_rate=s->gyro_z; + int32_t ail=-(st->roll_mdeg>>6)-(st->roll_rate>>7), ele=-(st->pitch_mdeg>>6)-(st->pitch_rate>>7), rud=-(st->yaw_mdeg>>6)-(st->yaw_rate>>7); + if(ail>127)ail=127; if(ail<-127)ail=-127; if(ele>127)ele=127; if(ele<-127)ele=-127; if(rud>127)rud=127; if(rud<-127)rud=-127; + return ((uint32_t)(uint8_t)(int8_t)ail)|((uint32_t)(uint8_t)(int8_t)ele<<8)|((uint32_t)(uint8_t)(int8_t)rud<<16)|((uint32_t)(st->updates&0xFF)<<24); +} +static inline void dwt_init(void){ DEMCR|=(1u<<24); DWT_CYCCNT=0; DWT_CTRL|=1u; } +static void init_st(struct flight_state*st){ st->pitch_mdeg=1000;st->roll_mdeg=-500;st->yaw_mdeg=200;st->pitch_rate=0;st->roll_rate=0;st->yaw_rate=0;st->updates=7; } +static void init_s(struct imu_sample*s){ *s=(struct imu_sample){0}; s->gyro_x=100;s->gyro_y=-50;s->gyro_z=30;s->accel_x=300;s->accel_y=-200; } + +int main(void){ + dwt_init(); + /* place st at offset 0, s at offset 32 in linmem; native uses stack copies */ + struct flight_state *lst=(struct flight_state*)&wasm_linmem[0]; + struct imu_sample *ls =(struct imu_sample*)&wasm_linmem[32]; + struct flight_state nst; struct imu_sample ns; + init_st(lst); init_s(ls); init_st(&nst); init_s(&ns); + uint32_t vs=synth_flat_flight_buf(0,32), vn=n_flat_flight(&nst,&ns); + printk("SELFCHECK synth=0x%08x native=0x%08x exp=0x07fdf307 %s\n", vs, vn, (vs==vn&&vs==0x07fdf307u)?"OK":"BAD"); + uint32_t ovh=0xFFFFFFFFu; + for(int i=0;i<200;i++){ uint32_t a=DWT_CYCCNT,b=DWT_CYCCNT; uint32_t d=b-a; if(daccel_x, accel_roll = s->accel_y; + int32_t gyro_pitch = st->pitch_mdeg + s->gyro_y; + int32_t gyro_roll = st->roll_mdeg + s->gyro_x; + int32_t gyro_yaw = st->yaw_mdeg + s->gyro_z; + st->pitch_mdeg = (gyro_pitch*980 + accel_pitch*20)/1000; + st->roll_mdeg = (gyro_roll *980 + accel_roll *20)/1000; + st->yaw_mdeg = gyro_yaw; + st->pitch_rate = s->gyro_y; st->roll_rate = s->gyro_x; st->yaw_rate = s->gyro_z; + /* --- controller_step inlined --- */ + int32_t ail = -(st->roll_mdeg>>6) - (st->roll_rate>>7); + int32_t ele = -(st->pitch_mdeg>>6) - (st->pitch_rate>>7); + int32_t rud = -(st->yaw_mdeg>>6) - (st->yaw_rate>>7); + if(ail>127)ail=127; if(ail<-127)ail=-127; + if(ele>127)ele=127; if(ele<-127)ele=-127; + if(rud>127)rud=127; if(rud<-127)rud=-127; + return ((uint32_t)(uint8_t)(int8_t)ail)|((uint32_t)(uint8_t)(int8_t)ele<<8) + |((uint32_t)(uint8_t)(int8_t)rud<<16)|((uint32_t)(st->updates&0xFF)<<24); +} diff --git a/benches/engine_control/silicon/wasm-testbed/flight_algo.c b/benches/engine_control/silicon/wasm-testbed/flight_algo.c new file mode 100644 index 00000000..54d5c045 --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/flight_algo.c @@ -0,0 +1,27 @@ +/* Composed flight-control algo: the through-memory caller->callee seam for loom. + * flight_algo() runs filter_step (writes *st) then controller_step (reads *st): + * inlining controller_step here is exactly the memory-reading-callee case loom + * described in loom#155. Exported so loom's inline pass has a real 2-fn seam. */ +#include "control.h" +__attribute__((export_name("flight_algo"))) +uint32_t flight_algo(struct flight_state *st, const struct imu_sample *s) +{ + filter_step(st, s); + return controller_step(st); +} + +/* Test driver: puts the structs in wasm linear memory (statics) and calls + * flight_algo with their addresses, so a scalar-only runtime (wasmtime --invoke) + * can exercise the through-memory path. Not part of the seam under test. */ +static struct flight_state g_st; +static struct imu_sample g_s; +__attribute__((export_name("drive"))) +uint32_t drive(int32_t pitch,int32_t roll,int32_t yaw, + int32_t gx,int32_t gy,int32_t gz,int32_t ax,int32_t ay) +{ + g_st = (struct flight_state){0}; + g_st.pitch_mdeg=pitch; g_st.roll_mdeg=roll; g_st.yaw_mdeg=yaw; g_st.updates=7; + g_s = (struct imu_sample){0}; + g_s.gyro_x=gx; g_s.gyro_y=gy; g_s.gyro_z=gz; g_s.accel_x=ax; g_s.accel_y=ay; + return flight_algo(&g_st, &g_s); +} diff --git a/benches/engine_control/silicon/wasm-testbed/mutex-microbench/CMakeLists.txt b/benches/engine_control/silicon/wasm-testbed/mutex-microbench/CMakeLists.txt new file mode 100644 index 00000000..7bf6f02f --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/mutex-microbench/CMakeLists.txt @@ -0,0 +1,8 @@ +cmake_minimum_required(VERSION 3.20.0) +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(mutex_microbench) +target_sources(app PRIVATE src/main.c) +# Mirror the override macro into main.c's printk label when the wasm variant is built. +if(DEFINED GALE_WASM_LTO_MUTEX_LIB) + target_compile_definitions(app PRIVATE GALE_WASM_LTO_OVERRIDE_MUTEX_UNLOCK=1) +endif() diff --git a/benches/engine_control/silicon/wasm-testbed/mutex-microbench/RESULT-2026-06-13-g474re-v0.11.41.txt b/benches/engine_control/silicon/wasm-testbed/mutex-microbench/RESULT-2026-06-13-g474re-v0.11.41.txt new file mode 100644 index 00000000..89d58d85 --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/mutex-microbench/RESULT-2026-06-13-g474re-v0.11.41.txt @@ -0,0 +1,7 @@ +SELFCHECK k_mutex_unlock rc=0 owner=0 (exp 0 / NULL) +E,k_mutex_unlock,cyc=501 (ovh=1, wasm-cross-LTO) +# synth 0.11.41 (#331 spill-slot-collision fix, built from main commit d6caab0/681f0bf) + loom 1.1.13, G474RE. +# 501/124 native = 4.04x. FIRST successful mutex measurement — prior synth (<=0.11.40) silently +# miscompiled the no-waiter lock_count=0 store (spill-slot collision) -> silicon DEADLOCK. +# SELFCHECK confirms no-waiter unlock leaves owner=NULL, round-trip completes (no hang). +# 31% of the 269-insn dissolved body is [sp] spills -> prime spill-reduction target (synth#209). diff --git a/benches/engine_control/silicon/wasm-testbed/mutex-microbench/RESULT-2026-06-14-g474re-v0.11.43.txt b/benches/engine_control/silicon/wasm-testbed/mutex-microbench/RESULT-2026-06-14-g474re-v0.11.43.txt new file mode 100644 index 00000000..a4e4123e --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/mutex-microbench/RESULT-2026-06-14-g474re-v0.11.43.txt @@ -0,0 +1,7 @@ +SELFCHECK k_mutex_unlock rc=0 owner=0 (exp 0 / NULL) +E,k_mutex_unlock,cyc=472 (ovh=1, wasm-cross-LTO) +# synth 0.11.43 (#345 .bss + PC-relative link-survivability fix; module merged via gale PR#60) + loom 1.1.13, G474RE DWT@170MHz, min/200, uncontended no-waiter unlock. +# 472/124 native = 3.81x. Down from 501 (v0.11.41, RESULT-2026-06-13) -> -29 cyc / -5.8% across 0.11.41->0.11.43 (#313 if/else-result fix + #345). +# Dissolved z_impl_k_mutex_unlock body (v0.11.43): 167 insns, 56 (34%) [sp] spills -> spill reduction (synth#209) remains the dominant lever. +# Reloc shape now link-survivable: MOVW/MOVT_ABS 0, R_ARM_ABS32 11, .data=4 (.bss=65536). Full mutex_api 9/9 PASS on HW (verify_mutex_module_silicon.sh). +# Reference (gale rustc-direct native): k_mutex_unlock = 124 cyc. diff --git a/benches/engine_control/silicon/wasm-testbed/mutex-microbench/prj.conf b/benches/engine_control/silicon/wasm-testbed/mutex-microbench/prj.conf new file mode 100644 index 00000000..5b8d9300 --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/mutex-microbench/prj.conf @@ -0,0 +1,5 @@ +CONFIG_PRINTK=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_MAIN_STACK_SIZE=2048 diff --git a/benches/engine_control/silicon/wasm-testbed/mutex-microbench/remeasure_wasm_lto.sh b/benches/engine_control/silicon/wasm-testbed/mutex-microbench/remeasure_wasm_lto.sh new file mode 100755 index 00000000..150de0e5 --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/mutex-microbench/remeasure_wasm_lto.sh @@ -0,0 +1,65 @@ +#!/usr/bin/env bash +# One-command k_mutex_unlock wasm-cross-LTO re-measurement, staged for synth v0.11.29 +# (the --native-pointer-abi flag from synth#237). Encodes the full dissolution + +# trampoline + microbench + silicon-capture recipe so the turnaround is instant. +# +# Pipeline (per NOTES-wasm-cross-lto-spike.md): +# clang wasm_mutex_shim_poc.c -> wasm-ld + libgale_ffi.a -> loom inline -> +# synth compile --native-pointer-abi --all-exports --relocatable (v0.11.29+: emits +# wasm statics as MOVW/MOVT __synth_wasm_data .data relocs; host k_mutex* stays base=0) +# -> objcopy rename imports->gale_w_*, body->synth_k_mutex_unlock_body +# -> + mtx_tramp.S (mov r11,#0 ; bl synth_body) -> ar libwasmmutex.a +# -> west build mutex-microbench (native + GALE_WASM_LTO_MUTEX_LIB) -> flash -> capture +# Reference (gale rustc-direct, native): k_mutex_unlock = 124 cyc (DWT min/200, uncontended). +set -euo pipefail +SYNTH="${SYNTH:-synth}"; CLANG=/opt/homebrew/opt/llvm/bin/clang; WASMLD=/opt/homebrew/bin/wasm-ld +TC=/Volumes/Home/zephyr-sdk/zephyr-sdk-1.0.1/gnu/arm-zephyr-eabi/bin/arm-zephyr-eabi +GR=/Volumes/Home/git/pulseengine/gale-smart-data +SHIM="$GR/benches/engine_control/silicon/boards/nucleo_g474re/wasm_mutex_shim_poc.c" +LIBFFI=/Volumes/Home/git/pulseengine/gale/ffi/target/wasm32-unknown-unknown/release/libgale_ffi.a +VCP="${VCP:-/dev/cu.usbmodem132203}" # VCP autodetect = lex-first; do NOT pass --port + +"$SYNTH" compile --help 2>&1 | grep -q 'native-pointer-abi' || { echo "synth lacks --native-pointer-abi (need v0.11.29+, synth#237); aborting"; exit 3; } +t=$(mktemp -d); cd "$t" +$CLANG --target=wasm32-unknown-unknown -O2 -nostdlib -c "$SHIM" -o shim.o +( cd /Volumes/Home/git/pulseengine/gale/ffi && cargo rustc --release --target wasm32-unknown-unknown --crate-type=staticlib >/dev/null 2>&1 ) +$WASMLD --no-entry --export=z_impl_k_mutex_unlock --allow-undefined --gc-sections shim.o "$LIBFFI" -o m.wasm +loom optimize m.wasm --passes inline --attestation false -o m.loom.wasm >/dev/null +"$SYNTH" compile m.loom.wasm --target cortex-m4f --native-pointer-abi --all-exports --relocatable -o m.o +"$TC-objcopy" \ + --redefine-sym k_spin_lock=gale_w_spin_lock --redefine-sym k_spin_unlock=gale_w_spin_unlock \ + --redefine-sym z_unpend_first_thread=gale_w_unpend_first_thread --redefine-sym z_ready_thread=gale_w_ready_thread \ + --redefine-sym arch_thread_return_value_set=gale_w_arch_thread_return_value_set --redefine-sym z_reschedule=gale_w_reschedule \ + --redefine-sym z_impl_k_mutex_unlock=synth_k_mutex_unlock_body m.o body.o +cat > tramp.S <<'ASM' + .syntax unified + .thumb + .section .text.gale_mtx_tramp,"ax",%progbits + .global z_impl_k_mutex_unlock + .thumb_func +z_impl_k_mutex_unlock: + push {r11, lr} + mov.w r11, #0 + bl synth_k_mutex_unlock_body + pop {r11, pc} +ASM +"$TC-gcc" -mcpu=cortex-m4 -mthumb -c tramp.S -o tramp.o +"$TC-ar" rcs "$t/libwasmmutex.a" body.o tramp.o +export ZEPHYR_BASE=/Volumes/Home/git/pulseengine/zephyr ZEPHYR_SDK_INSTALL_DIR=/Volumes/Home/zephyr-sdk/zephyr-sdk-1.0.1 +MB="$GR/benches/engine_control/silicon/wasm-testbed/mutex-microbench" +west build -b nucleo_g474re -d "$t/mb" -p always "$MB" -- -DZEPHYR_EXTRA_MODULES="$GR" \ + -DOVERLAY_CONFIG="$GR/zephyr/gale_overlay.conf" -DGALE_WASM_LTO_MUTEX_LIB="$t/libwasmmutex.a" >/dev/null 2>&1 +CAP="$GR/benches/engine_control/silicon" +# Capture loop is intentionally set -e tolerant: serial capture is flaky (0-byte +# reads) and the firmware may fault, so neither openocd/wait nor the match-grep +# must abort the script — we always reach the RESULT print below. +set +e +for try in 1 2 3 4 5; do + python3 "$CAP/capture.py" --port "$VCP" --baud 115200 --sentinel "=== END ===" --timeout 15 --out "$t/cap" >/dev/null 2>&1 & c=$!; sleep 2 + openocd -f interface/stlink.cfg -f target/stm32g4x.cfg -c "program $t/mb/zephyr/zephyr.elf verify reset exit" >/dev/null 2>&1 || true + wait "$c" 2>/dev/null || true + if grep -qaE 'E,k_mutex_unlock|FAULT' "$t/cap"; then break; fi +done +echo "=== RESULT ===" +grep -aE 'SELFCHECK|E,k_mutex_unlock|FAULT' "$t/cap" 2>/dev/null | head || echo "(no output captured — flaky serial; retry)" +echo "(native gale ref: 124 cyc; expect E,k_mutex_unlock,cyc=N once synth#237 BSS coverage lands)" diff --git a/benches/engine_control/silicon/wasm-testbed/mutex-microbench/src/main.c b/benches/engine_control/silicon/wasm-testbed/mutex-microbench/src/main.c new file mode 100644 index 00000000..90cbf632 --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/mutex-microbench/src/main.c @@ -0,0 +1,53 @@ +/* k_mutex_unlock cycle microbench — the 2nd primitive after k_sem_give (907). + * Times the uncontended k_mutex_unlock hot path on real silicon: DWT CYCCNT + * @170 MHz, min over 200 iters, overhead floor (two back-to-back reads) + * subtracted. Which z_impl_k_mutex_unlock is measured is selected at BUILD + * time: native gale (rustc-direct) vs wasm-cross-LTO (GALE_WASM_LTO_MUTEX_LIB). + * Same methodology as silicon-microbench (control_step) + the sem 907 result. */ +#include +#include + +#define DEMCR (*(volatile uint32_t *)0xE000EDFCu) +#define DWT_CTRL (*(volatile uint32_t *)0xE0001000u) +#define DWT_CYCCNT (*(volatile uint32_t *)0xE0001004u) +static inline void dwt_init(void){ DEMCR |= (1u<<24); DWT_CYCCNT = 0; DWT_CTRL |= 1u; } + +static struct k_mutex m; + +int main(void) +{ + dwt_init(); + k_mutex_init(&m); + + /* overhead floor: cost of two adjacent DWT reads */ + uint32_t ovh = 0xFFFFFFFFu; + for (int i = 0; i < 200; i++) { + uint32_t a0 = DWT_CYCCNT; uint32_t a1 = DWT_CYCCNT; + uint32_t d = a1 - a0; if (d < ovh) ovh = d; + } + + /* selfcheck: lock+unlock works (owner round-trips) */ + k_mutex_lock(&m, K_FOREVER); + int rc = k_mutex_unlock(&m); + printk("SELFCHECK k_mutex_unlock rc=%d owner=%p (exp 0 / NULL)\n", + rc, (void *)m.owner); + + /* measure uncontended k_mutex_unlock: lock (outside window) then time unlock */ + uint32_t best = 0xFFFFFFFFu; + for (int i = 0; i < 200; i++) { + k_mutex_lock(&m, K_FOREVER); + uint32_t t0 = DWT_CYCCNT; + k_mutex_unlock(&m); + uint32_t t1 = DWT_CYCCNT; + uint32_t d = t1 - t0; if (d < best) best = d; + } + printk("E,k_mutex_unlock,cyc=%u (ovh=%u, " +#ifdef GALE_WASM_LTO_OVERRIDE_MUTEX_UNLOCK + "wasm-cross-LTO" +#else + "gale-native" +#endif + ")\n", best - ovh, ovh); + printk("=== END ===\n"); + return 0; +} diff --git a/benches/engine_control/silicon/wasm-testbed/mutex-microbench/verify_mutex_module_silicon.sh b/benches/engine_control/silicon/wasm-testbed/mutex-microbench/verify_mutex_module_silicon.sh new file mode 100755 index 00000000..95789ef0 --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/mutex-microbench/verify_mutex_module_silicon.sh @@ -0,0 +1,65 @@ +#!/usr/bin/env bash +# Staged #345 kill-criterion harness: full upstream tests/kernel/mutex/mutex_api on G474RE +# with the wasm-cross-LTO mutex module (CONFIG_GALE_WASM_LTO_MUTEX=y). Run this the moment +# synth#345 (.bss the linmem reservation + PC-relative) lands — one command, instant verdict. +# +# The no-waiter microbench (remeasure_wasm_lto.sh) only exercises the UNLOCKED path; this runs +# the FULL suite, which is what caught the real bugs: +# - WITH --native-pointer-abi pre-#345: test_complex_inversion USAGE FAULT (MOVW_ABS link +# corruption from the 64 KB .data) — see synth#345 / gale PR #60. +# - WITHOUT --native-pointer-abi: test_complex_inversion PASSES but test_mutex_recursive MPU +# FAULT (host-pointer deref wrong without the flag) — workaround ruled out 2026-06-14. +# KILL-CRITERION (PASS): with --native-pointer-abi on the #345-fixed synth, BOTH +# test_complex_inversion AND test_mutex_recursive pass, "PROJECT EXECUTION SUCCESSFUL", no FAULT. +set -u +SYNTH="${SYNTH:-synth}"; CLANG="${CLANG:-/opt/homebrew/opt/llvm/bin/clang}"; WASMLD="${WASMLD:-/opt/homebrew/bin/wasm-ld}" +SDK=/Volumes/Home/zephyr-sdk/zephyr-sdk-1.0.1; TC="$SDK/gnu/arm-zephyr-eabi/bin/arm-zephyr-eabi" +GALE=/Volumes/Home/git/pulseengine/gale +export ZEPHYR_BASE=/Volumes/Home/git/pulseengine/zephyr ZEPHYR_SDK_INSTALL_DIR=$SDK +export PATH="$(dirname "$CLANG"):$TC/..:$PATH" +echo "== verify mutex module (synth $($SYNTH --version|head -1|awk '{print $2}'), --native-pointer-abi) ==" +t=$(mktemp -d); WD=$(mktemp -d) +# 1. FFI wasm staticlib + shim -> dissolve -> synth (WITH --native-pointer-abi) -> renamed .o +( cd "$GALE/ffi" && cargo rustc --release --target wasm32-unknown-unknown --crate-type=staticlib >/dev/null 2>&1 ) +LIBFFI="$GALE/ffi/target/wasm32-unknown-unknown/release/libgale_ffi.a" +$CLANG --target=wasm32-unknown-unknown -O2 -nostdlib -c "$GALE/zephyr/wasm/mutex_unlock_shim.c" -o "$t/shim.o" || exit 2 +$WASMLD --no-entry --export=z_impl_k_mutex_unlock --export=gale_k_mutex_unlock_decide --allow-undefined --gc-sections "$LIBFFI" "$t/shim.o" -o "$t/m.wasm" || exit 2 +loom optimize "$t/m.wasm" --passes inline --attestation false -o "$t/m.loom.wasm" >/dev/null 2>&1 || exit 2 +$SYNTH compile "$t/m.loom.wasm" --target cortex-m4f --native-pointer-abi --all-exports --relocatable -o "$t/m.o" || exit 2 +"$TC-objcopy" --redefine-sym k_spin_lock=gale_w_spin_lock --redefine-sym k_spin_unlock=gale_w_spin_unlock \ + --redefine-sym z_unpend_first_thread=gale_w_unpend_first_thread --redefine-sym z_ready_thread=gale_w_ready_thread \ + --redefine-sym arch_thread_return_value_set=gale_w_arch_thread_return_value_set --redefine-sym z_reschedule=gale_w_reschedule \ + --redefine-sym z_impl_k_mutex_unlock=synth_k_mutex_unlock_body "$t/m.o" "$t/r.o" +"$TC-objcopy" --keep-global-symbol=synth_k_mutex_unlock_body "$t/r.o" "$WD/gale-wasm-mutex-cortex-m4f.o" +echo " module shape: .data=$("$TC-size" -A "$WD/gale-wasm-mutex-cortex-m4f.o" 2>/dev/null|awk '/^\.data/{print $2}')B (target: 0, like sem) MOVW_ABS=$("$TC-objdump" -r "$WD/gale-wasm-mutex-cortex-m4f.o" 2>/dev/null|grep -c MOVW_ABS)" +# 2. build the upstream mutex_api test with the module (override on, branch must have the shim+wiring) +printf "CONFIG_GALE_KERNEL_MUTEX=y\nCONFIG_GALE_WASM_LTO_MUTEX=y\n" > "$t/ov.conf" +west build -b nucleo_g474re -d "$WD/build" "$ZEPHYR_BASE/tests/kernel/mutex/mutex_api" -p always -- \ + -DZEPHYR_EXTRA_MODULES="$GALE" -DOVERLAY_CONFIG="$t/ov.conf" -DGALE_WASM_LTO_MUTEX_OBJ="$WD/gale-wasm-mutex-cortex-m4f.o" >/dev/null 2>&1 \ + || { echo " [BAD] build failed"; exit 3; } +# 3. flash + capture +openocd -f interface/stlink.cfg -f target/stm32g4x.cfg -c "program $WD/build/zephyr/zephyr.elf verify reset exit" >/dev/null 2>&1 +# self-contained capture: VCP autodetect = lex-first /dev/cu.usbmodem* (do NOT hardcode --port); +# reset after opening the port, read until '=== END ===' / PROJECT EXECUTION / timeout. +out=$(python3 - <<'PYCAP' +import serial, glob, time, subprocess, threading +ports=sorted(glob.glob('/dev/cu.usbmodem*')) +ser=serial.Serial(ports[0],115200,timeout=1) +def rst(): + time.sleep(0.5); subprocess.run(["openocd","-f","interface/stlink.cfg","-f","target/stm32g4x.cfg","-c","init;reset;exit"],capture_output=True) +threading.Thread(target=rst,daemon=True).start() +end=time.time()+20; lines=[] +while time.time() wasm-ld -> loom inline -> synth) +# 2. compiles without register-exhaustion skip +# 3. seam folded (no `bl gale_k_*_decide` left) +# 4. mutex ONLY: the synth#331 spill-slot-collision signature is ABSENT — the mutex-ptr +# arg0 home spill slot must be WRITE-ONCE (the bug re-used it for z_unpend_first_thread's +# result, so the no-waiter lock_count store hit a clobbered base -> silicon deadlock). +# This catches a #331 regression in OUR consumption before we ship, complementing the +# frozen synth-side fixture (jess repro/synth-331/). +# Exit 0 = all green. +set -u +CLANG="${CLANG:-/opt/homebrew/opt/llvm/bin/clang}"; WASMLD="${WASMLD:-/opt/homebrew/bin/wasm-ld}" +SYNTH="${SYNTH:-synth}" +OBJDUMP="${OBJDUMP:-/opt/homebrew/opt/llvm/bin/llvm-objdump}" +SIZE="${SIZE:-/opt/homebrew/opt/llvm/bin/llvm-size}" +GALE=/Volumes/Home/git/pulseengine/gale +GR=/Volumes/Home/git/pulseengine/gale-smart-data +SEM_SHIM="$GALE/zephyr/wasm/sem_give_shim.c" +MTX_SHIM="$GR/benches/engine_control/silicon/boards/nucleo_g474re/wasm_mutex_shim_poc.c" +PIPE_SHIM="$GR/benches/engine_control/silicon/boards/nucleo_g474re/wasm_pipe_write_shim_poc.c" +PIPE_RD_SHIM="$GR/benches/engine_control/silicon/boards/nucleo_g474re/wasm_pipe_read_shim_poc.c" +SEM_TAKE_SHIM="$GR/benches/engine_control/silicon/boards/nucleo_g474re/wasm_sem_take_shim_poc.c" +FATAL_SHIM="$GR/benches/engine_control/silicon/boards/nucleo_g474re/wasm_fatal_shim_poc.c" +LIBFFI="$GALE/ffi/target/wasm32-unknown-unknown/release/libgale_ffi.a" +fail=0; t=$(mktemp -d); trap 'rm -rf "$t"' EXIT + +echo "== kernel-primitives codegen lane (synth $($SYNTH --version|head -1|awk '{print $2}'), loom $(loom --version|head -1|awk '{print $2}')) ==" + +# libffi must carry the `pipe` feature (gale_k_pipe_write_decide is #[cfg(feature="pipe")]); +# rebuild if absent or stale (additive feature — sem/mutex decode unchanged). +if [ ! -f "$LIBFFI" ] || ! "$OBJDUMP" -t "$LIBFFI" 2>/dev/null | grep -q gale_k_pipe_write_decide; then + ( cd "$GALE/ffi" && cargo rustc --release --target wasm32-unknown-unknown --features pipe --crate-type=staticlib >/dev/null 2>&1 ) +fi + +build_primitive() { # name shim export extra-synth-flags + local name="$1" shim="$2" exp="$3" flags="$4" + $CLANG --target=wasm32-unknown-unknown -O2 -nostdlib -c "$shim" -o "$t/$name.shim.o" 2>/dev/null || return 1 + $WASMLD --no-entry --export="$exp" --export="gale_k_${name}_decide" --allow-undefined --gc-sections \ + "$LIBFFI" "$t/$name.shim.o" -o "$t/$name.wasm" 2>/dev/null || return 1 + loom optimize "$t/$name.wasm" --passes inline --attestation false -o "$t/$name.loom.wasm" >/dev/null 2>&1 || return 1 + local out; out=$($SYNTH compile "$t/$name.loom.wasm" --target cortex-m4f $flags --all-exports --relocatable -o "$t/$name.o" 2>&1) + if echo "$out" | grep -qiE 'register exhaustion|no functions compiled|skipping function'; then + echo " codegen: $(echo "$out"|grep -iE 'exhaustion|skipping'|head -1|sed 's/^ *//')"; return 2; fi + # seam-fold is checked on the OBJECT's relocations by the caller (synth stdout lists + # imports by name and would false-positive here). + return 0 +} + +# --- k_sem_give --- +echo "k_sem_give (dissolved give path):" +build_primitive sem_give "$SEM_SHIM" z_impl_k_sem_give "" +rc=$? +if [ $rc -eq 0 ]; then + # seam-fold check: no relocation to gale_k_sem_give_decide in the object + if $OBJDUMP -r "$t/sem_give.o" 2>/dev/null | grep -q gale_k_sem_give_decide; then + echo " [BAD] seam not folded (decide reloc present)"; fail=1 + else echo " [OK ] compiles + seam folded"; fi +else echo " [BAD] build/codegen rc=$rc"; fail=1; fi + +# --- k_sem_take (completes the sem primitive: give + take, v0.1.0 release target) --- +echo "k_sem_take (dissolved blocking-acquire path; completes sem primitive — gate-2 sem-shape):" +build_primitive sem_take "$SEM_TAKE_SHIM" z_impl_k_sem_take "" +rc=$? +if [ $rc -eq 0 ]; then + seam=$($OBJDUMP -r "$t/sem_take.o" 2>/dev/null | grep -c gale_k_sem_take_decide) + absr=$($OBJDUMP -r "$t/sem_take.o" 2>/dev/null | grep -cE "R_ARM_MOVW_ABS|R_ARM_MOVT_ABS") + data=$($SIZE -A "$t/sem_take.o" 2>/dev/null | awk '$1==".data"{print $2}'); data=${data:-0} + if [ "$seam" -ne 0 ]; then echo " [BAD] seam not folded (decide reloc present)"; fail=1 + elif [ "$absr" -ne 0 ]; then echo " [BAD] $absr abs MOVW/MOVT relocs — NOT sem-shaped"; fail=1 + elif [ "$data" -gt 16 ]; then echo " [BAD] .data=$data B — linmem blob leaked"; fail=1 + else echo " [OK ] compiles + seam folded + .data=${data}B + 0 abs-relocs (SEM-SHAPED — sem primitive complete: give+take)"; fi +else echo " [BAD] build/codegen rc=$rc"; fail=1; fi + +# --- k_pipe_write (2nd u64-shaped drop-in; NOT --native-pointer-abi; NOT gated on #345) --- +# Gate-2 shape check: pipe's decide returns a packed u64 (gate-1, like sem), so the +# question is whether the more complex 5-action write BODY stays in registers or spills +# to a wasm linmem frame (the synth#345 sret→linmem→64KB .data + MOVW_ABS shape). The +# drop-in criterion is sem-shaped: .data==0, abs-relocs==0, seam folded. +echo "k_pipe_write (dissolved write path; 2nd u64 drop-in — gate-2 sem-shape check):" +build_primitive pipe_write "$PIPE_SHIM" z_impl_k_pipe_write "" +rc=$? +if [ $rc -eq 0 ]; then + seam=$($OBJDUMP -r "$t/pipe_write.o" 2>/dev/null | grep -c gale_k_pipe_write_decide) + absr=$($OBJDUMP -r "$t/pipe_write.o" 2>/dev/null | grep -cE "R_ARM_MOVW_ABS|R_ARM_MOVT_ABS") + data=$($SIZE -A "$t/pipe_write.o" 2>/dev/null | awk '$1==".data"{print $2}'); data=${data:-0} + if [ "$seam" -ne 0 ]; then echo " [BAD] seam not folded (decide reloc present)"; fail=1 + elif [ "$absr" -ne 0 ]; then echo " [BAD] $absr abs MOVW/MOVT relocs — NOT sem-shaped (linmem leak like #345)"; fail=1 + elif [ "$data" -gt 16 ]; then echo " [BAD] .data=$data B — linmem blob leaked (not a clean drop-in)"; fail=1 + else echo " [OK ] compiles + seam folded + .data=${data}B + 0 abs-relocs (SEM-SHAPED — clean drop-in, #345-independent)"; fi +else echo " [BAD] build/codegen rc=$rc"; fail=1; fi + +# --- k_pipe_read (read half — pipe ships only if BOTH directions are clean) --- +echo "k_pipe_read (dissolved read path; pipe's 2nd direction — gate-2 sem-shape check):" +build_primitive pipe_read "$PIPE_RD_SHIM" z_impl_k_pipe_read "" +rc=$? +if [ $rc -eq 0 ]; then + seam=$($OBJDUMP -r "$t/pipe_read.o" 2>/dev/null | grep -c gale_k_pipe_read_decide) + absr=$($OBJDUMP -r "$t/pipe_read.o" 2>/dev/null | grep -cE "R_ARM_MOVW_ABS|R_ARM_MOVT_ABS") + data=$($SIZE -A "$t/pipe_read.o" 2>/dev/null | awk '$1==".data"{print $2}'); data=${data:-0} + if [ "$seam" -ne 0 ]; then echo " [BAD] seam not folded (decide reloc present)"; fail=1 + elif [ "$absr" -ne 0 ]; then echo " [BAD] $absr abs MOVW/MOVT relocs — NOT sem-shaped (linmem leak like #345)"; fail=1 + elif [ "$data" -gt 16 ]; then echo " [BAD] .data=$data B — linmem blob leaked (not a clean drop-in)"; fail=1 + else echo " [OK ] compiles + seam folded + .data=${data}B + 0 abs-relocs (SEM-SHAPED — pipe clean both directions)"; fi +else echo " [BAD] build/codegen rc=$rc"; fail=1; fi + +# --- k_fatal (5th/last u64-shaped clean decide — closes the u64-clean partition) --- +echo "k_fatal (dissolved k_sys_fatal_error_handler policy — gate-2 sem-shape check):" +build_primitive fatal "$FATAL_SHIM" k_sys_fatal_error_handler "" +rc=$? +if [ $rc -eq 0 ]; then + seam=$($OBJDUMP -r "$t/fatal.o" 2>/dev/null | grep -c gale_k_fatal_decide) + absr=$($OBJDUMP -r "$t/fatal.o" 2>/dev/null | grep -cE "R_ARM_MOVW_ABS|R_ARM_MOVT_ABS") + data=$($SIZE -A "$t/fatal.o" 2>/dev/null | awk '$1==".data"{print $2}'); data=${data:-0} + if [ "$seam" -ne 0 ]; then echo " [BAD] seam not folded (decide reloc present)"; fail=1 + elif [ "$absr" -ne 0 ]; then echo " [BAD] $absr abs MOVW/MOVT relocs — NOT sem-shaped"; fail=1 + elif [ "$data" -gt 16 ]; then echo " [BAD] .data=$data B — linmem blob leaked"; fail=1 + else echo " [OK ] compiles + seam folded + .data=${data}B + 0 abs-relocs (SEM-SHAPED — u64-clean partition 5/5 complete)"; fi +else echo " [BAD] build/codegen rc=$rc"; fail=1; fi + +# --- k_mutex_unlock (+ synth#331 signature) --- +echo "k_mutex_unlock (dissolved unlock path; synth#331 spill-slot-collision guard):" +build_primitive mutex_unlock "$MTX_SHIM" z_impl_k_mutex_unlock "--native-pointer-abi" +rc=$? +if [ $rc -eq 0 ]; then + $OBJDUMP -d --triple=thumbv7em-unknown-none-eabi "$t/mutex_unlock.o" 2>/dev/null > "$t/mtx.dis" + # isolate the z_impl_k_mutex_unlock body + awk '/:/{f=1;next} /^[0-9a-f]+ "$t/mtx.body" + # arg0 home slot = the slot stored from r0 in the FIRST few insns (entry param spill) + home=$(grep -oE "str\.w[[:space:]]+r0, \[sp, #0x[0-9a-f]+\]" "$t/mtx.body" | head -1 | grep -oE "#0x[0-9a-f]+") + if [ -z "$home" ]; then echo " [WARN] could not locate arg0 home slot; skipping #331 signature check"; else + # WRITE-ONCE invariant: exactly one str to the home slot in the whole body + nwrite=$(grep -cE "str(\.w)?[[:space:]]+r[0-9]+, \[sp, ${home}\]" "$t/mtx.body") + if [ "$nwrite" -eq 1 ]; then + echo " [OK ] compiles + seam folded + arg0 home ($home) WRITE-ONCE (#331 signature absent)" + else + echo " [BAD] #331 REGRESSION: arg0 home ($home) written $nwrite times — call result aliases it (silent miscompile -> silicon deadlock)"; fail=1 + fi + fi +else echo " [BAD] build/codegen rc=$rc"; fail=1; fi + +echo "== primitives lane: $( [ $fail -eq 0 ] && echo GREEN || echo 'RED — see [BAD]' ) ==" +exit $fail diff --git a/benches/engine_control/silicon/wasm-testbed/repro-loom-seam-sroa/sem.loom.wasm b/benches/engine_control/silicon/wasm-testbed/repro-loom-seam-sroa/sem.loom.wasm new file mode 100644 index 00000000..04328bac Binary files /dev/null and b/benches/engine_control/silicon/wasm-testbed/repro-loom-seam-sroa/sem.loom.wasm differ diff --git a/benches/engine_control/silicon/wasm-testbed/repro-loom-seam-sroa/sem_give_shim.c b/benches/engine_control/silicon/wasm-testbed/repro-loom-seam-sroa/sem_give_shim.c new file mode 100644 index 00000000..2105d4dd --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/repro-loom-seam-sroa/sem_give_shim.c @@ -0,0 +1,94 @@ +/* + * Minimal wasm-side host of z_impl_k_sem_give. + * + * Replicates the hot-path structure of gale-smart-data's gale_sem.c + * but with kernel APIs as externs (which become wasm imports), so the + * shim itself compiles to wasm32-unknown-unknown without pulling in + * Zephyr headers. This puts the C ↔ Rust seam INSIDE the wasm bundle — + * meld/wasm-ld merges it with gale-ffi.wasm, loom inlines through it, + * synth produces ARM with the seam dissolved. + * + * The published silicon-LTO recovery for handoff cycles was 471 (-10.8% + * vs baseline 528) at ADC=n, or 558 (vs baseline 506) at ADC=y. If the + * loom→synth output matches LLVM-LTO's inlined-into-z_impl_k_sem_give + * shape (no `bl gale_k_sem_give_decide`, decision logic merged into + * z_impl_k_sem_give's body), we have evidence that the verified-Rust + * route is at parity with LTO at the codegen level. + */ + +#include + +/* Opaque k_thread — we never deref this in the shim, kernel does. */ +struct k_thread; +/* k_spinlock has a non-zero size in Zephyr; give it one byte so the + * static instance below is a complete type. The kernel's k_spin_lock + * etc. take a pointer; they don't care about our internal size. */ +struct k_spinlock { uint8_t lock_internal; }; + +/* Match gale-smart-data layout — count + limit are the first two u32s + * in a k_sem. We don't touch the rest. */ +/* Faithful mirror of Zephyr v4.4.0 struct k_sem with CONFIG_POLL=n, + * CONFIG_WAITQ_SCALABLE=n: _wait_q_t == sys_dlist_t == {head, tail}. + * The earlier 2-field {count,limit} shape skewed count/limit by 8 bytes + * against the REAL k_sem the bench passes in, and the NULL wait_q below + * made z_unpend_first_thread read the vector table — MPU fault on + * zephyr v4.4.0 final (and semantically-unsound wakes before that). */ +struct k_sem { + void *wq_head; + void *wq_tail; + uint32_t count; + uint32_t limit; +}; + +typedef struct { uint32_t key; } k_spinlock_key_t; + +/* Kernel API externs — wasm imports at link time, native bl at synth-emit. */ +extern k_spinlock_key_t k_spin_lock(struct k_spinlock *); +extern void k_spin_unlock(struct k_spinlock *, k_spinlock_key_t); +extern struct k_thread * z_unpend_first_thread(void *wait_q); +extern void z_ready_thread(struct k_thread *); +extern void arch_thread_return_value_set(struct k_thread *, uint32_t); +extern int z_reschedule(struct k_spinlock *, k_spinlock_key_t); + +/* The verified Rust function — same wasm module after wasm-ld merge, + * so loom can inline. */ +extern uint64_t gale_k_sem_give_decide(uint32_t count, uint32_t limit, + uint32_t has_waiter); + +/* AAPCS-packed decision struct — matches gale-smart-data's layout. */ +union gale_sem_give_decision_u { + uint64_t raw; + struct { + uint8_t action; + uint8_t pad[3]; + uint32_t new_count; + } dec; +}; + +#define GALE_SEM_ACTION_WAKE 1 + +/* The shim spinlock — kept simple, kernel handles real one. */ +static struct k_spinlock shim_lock_raw; + +/* The hot path. THIS IS THE FFI SEAM. */ +void z_impl_k_sem_give(struct k_sem *sem) { + k_spinlock_key_t key = k_spin_lock(&shim_lock_raw); + + /* Extract: try to unpend first waiter (kernel side effect). */ + struct k_thread *thread = z_unpend_first_thread((void *)sem); /* wait_q is k_sem\x27s first member */ + + /* Decide: Rust determines action via 8-byte u64-packed decision. */ + union gale_sem_give_decision_u du; + du.raw = gale_k_sem_give_decide(sem->count, sem->limit, + thread != (struct k_thread *)0 ? 1U : 0U); + + /* Apply: execute the decision. */ + if (du.dec.action == GALE_SEM_ACTION_WAKE) { + arch_thread_return_value_set(thread, 0U); + z_ready_thread(thread); + } else { + sem->count = du.dec.new_count; + } + + z_reschedule(&shim_lock_raw, key); +} diff --git a/benches/engine_control/silicon/wasm-testbed/repro-synth-stack-add-imm/ERROR-v0.11.43.txt b/benches/engine_control/silicon/wasm-testbed/repro-synth-stack-add-imm/ERROR-v0.11.43.txt new file mode 100644 index 00000000..3093e325 --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/repro-synth-stack-add-imm/ERROR-v0.11.43.txt @@ -0,0 +1,3 @@ +warning: skipping function 'gale_k_stack_push_decide': backend 'arm' failed: compilation failed: ARM encoding failed: Synthesis failed: ADD immediate too large for single instruction +warning: skipping function 'z_impl_k_stack_push': backend 'arm' failed: compilation failed: branch-resolve size probe failed: Synthesis failed: ADD immediate too large for single instruction +Error: no functions compiled successfully (2 skipped) — nothing to emit diff --git a/benches/engine_control/silicon/wasm-testbed/repro-synth-stack-add-imm/stack_push.loom.wasm b/benches/engine_control/silicon/wasm-testbed/repro-synth-stack-add-imm/stack_push.loom.wasm new file mode 100644 index 00000000..2f366c60 Binary files /dev/null and b/benches/engine_control/silicon/wasm-testbed/repro-synth-stack-add-imm/stack_push.loom.wasm differ diff --git a/benches/engine_control/silicon/wasm-testbed/repro-synth-stack-add-imm/wasm_stack_push_shim_poc.c b/benches/engine_control/silicon/wasm-testbed/repro-synth-stack-add-imm/wasm_stack_push_shim_poc.c new file mode 100644 index 00000000..6ca58feb --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/repro-synth-stack-add-imm/wasm_stack_push_shim_poc.c @@ -0,0 +1,77 @@ +/* + * Minimal wasm-side host of z_impl_k_stack_push — a 2nd struct-return primitive + * (after mutex) to confirm synth#345 (.bss + PC-relative) generalizes the whole + * struct-return decide family, and to de-risk the gale#63 component epic (which + * will dissolve many struct-return primitives via the kernel-primitives WIT world). + * + * gale_k_stack_push_decide returns GaleStackPushDecision (12-byte #[repr(C)]: + * ret i32 / new_count u32 / action u8) BY VALUE → sret → linmem-frame path, the + * same shape that USAGE-FAULTed mutex pre-#345. With v0.11.43 the expected shape + * is link-survivable: .data bounded (~4), .bss NOBITS, MOVW/MOVT_ABS=0, ABS32 pool + * words — the "mutex shape", NOT the old 64 KB .data blob. Built WITH + * --native-pointer-abi (host k_stack* stays base=0 via the r11=0 trampoline). + * + * Faithful Zephyr v4.4.0 struct k_stack: wait_q first (so &stack == &stack->wait_q). + */ + +#include + +typedef uintptr_t stack_data_t; +struct k_thread; +struct k_spinlock { uint8_t lock_internal; }; +typedef struct { uint32_t key; } k_spinlock_key_t; + +struct k_stack { + void *wq_head; /* _wait_q_t wait_q (head,tail) */ + void *wq_tail; + struct k_spinlock lock; + stack_data_t *base; + stack_data_t *next; + stack_data_t *top; + uint8_t flags; +}; + +extern k_spinlock_key_t k_spin_lock(struct k_spinlock *); +extern void k_spin_unlock(struct k_spinlock *, k_spinlock_key_t); +extern struct k_thread * z_unpend_first_thread(void *wait_q); +extern void z_ready_thread(struct k_thread *); +extern void z_thread_return_value_set_with_data(struct k_thread *, unsigned int, void *); +extern int z_reschedule(struct k_spinlock *, k_spinlock_key_t); + +/* #[repr(C)] GaleStackPushDecision — 12 bytes, returned by value (sret). */ +struct gale_stack_push_decision { int32_t ret; uint32_t new_count; uint8_t action; }; +extern struct gale_stack_push_decision gale_k_stack_push_decide( + uint32_t count, uint32_t capacity, uint32_t has_waiter); + +#define GALE_STACK_PUSH_STORE 0 +#define GALE_STACK_PUSH_WAKE 1 +#define GALE_STACK_PUSH_FULL 2 + +int z_impl_k_stack_push(struct k_stack *stack, stack_data_t data) +{ + k_spinlock_key_t key = k_spin_lock(&stack->lock); + + uint32_t capacity = (uint32_t)(stack->top - stack->base); + uint32_t count = (uint32_t)(stack->next - stack->base); + struct k_thread *waiter = z_unpend_first_thread((void *)stack); /* wait_q is first member */ + + struct gale_stack_push_decision d = + gale_k_stack_push_decide(count, capacity, waiter != (struct k_thread *)0 ? 1U : 0U); + + switch (d.action) { + case GALE_STACK_PUSH_WAKE: + z_thread_return_value_set_with_data(waiter, 0U, (void *)data); + z_ready_thread(waiter); + z_reschedule(&stack->lock, key); + return d.ret; + case GALE_STACK_PUSH_FULL: + k_spin_unlock(&stack->lock, key); + return d.ret; /* -ENOMEM */ + case GALE_STACK_PUSH_STORE: + default: + *(stack->next) = data; + stack->next++; + k_spin_unlock(&stack->lock, key); + return d.ret; + } +} diff --git a/benches/engine_control/silicon/wasm-testbed/resurvey_struct_return_decides.sh b/benches/engine_control/silicon/wasm-testbed/resurvey_struct_return_decides.sh new file mode 100755 index 00000000..7bf1d4e6 --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/resurvey_struct_return_decides.sh @@ -0,0 +1,58 @@ +#!/usr/bin/env bash +# Staged kill-criterion re-survey for the struct-return decide family. Two gates: +# #350 (v0.11.44, FIXED): stack_push/pop + msgq_put/get compile (no ADD-imm skip). +# #354 (v0.11.45, pending): their dissolved objects' .data is BOUNDED (~init bytes +# + .bss for the zero gap), NOT a 64 KB PROGBITS blob — i.e. the per-region +# .data/.bss split (synth-cli build_relocatable_elf) handles a high-offset init +# segment. msgq exhibits it decide-only; stack at full-shim level. +# Run on each synth release; exits non-zero until BOTH gates pass. +set -u +SYNTH="${SYNTH:-synth}"; CLANG=/opt/homebrew/opt/llvm/bin/clang +WASMLD=/opt/homebrew/bin/wasm-ld; OBJDUMP=/opt/homebrew/opt/llvm/bin/llvm-objdump +SIZE=/opt/homebrew/opt/llvm/bin/llvm-size +STACK_SHIM=/Volumes/Home/git/pulseengine/gale-smart-data/benches/engine_control/silicon/boards/nucleo_g474re/wasm_stack_push_shim_poc.c +GALE=/Volumes/Home/git/pulseengine/gale +LIBFFI="$GALE/ffi/target/wasm32-unknown-unknown/release/libgale_ffi.a" +[ -f "$LIBFFI" ] || ( cd "$GALE/ffi" && cargo rustc --release --target wasm32-unknown-unknown --all-features --crate-type=staticlib >/dev/null 2>&1 ) +t=$(mktemp -d); trap 'rm -rf "$t"' EXIT; fail=0 +echo "== struct-return decide compile survey (synth $($SYNTH --version|head -1|awk '{print $2}')) ==" +survey() { + local d="$1" expect="$2" + $WASMLD --no-entry --export="$d" --allow-undefined --gc-sections "$LIBFFI" -o "$t/d.wasm" 2>/dev/null + loom optimize "$t/d.wasm" --passes inline --attestation false -o "$t/d.loom.wasm" >/dev/null 2>&1 + local out; out=$($SYNTH compile "$t/d.loom.wasm" --target cortex-m4f --all-exports --relocatable -o "$t/d.o2" 2>&1) + if echo "$out" | grep -qi "ADD immediate too large"; then + printf " %-30s FAIL: ADD-imm (#350)\n" "$d"; [ "$expect" = "OK" ] && fail=1 + elif echo "$out" | grep -qiE "skipping|no functions"; then + printf " %-30s FAIL: other\n" "$d"; [ "$expect" = "OK" ] && fail=1 + else printf " %-30s OK\n" "$d"; fi +} +# the 4 currently blocked on #350 (expect OK once fixed): +for d in gale_k_stack_push_decide gale_k_stack_pop_decide gale_k_msgq_put_decide gale_k_msgq_get_decide; do survey "$d" OK; done +# controls (must stay OK): +for d in gale_k_sem_give_decide gale_k_mutex_unlock_decide; do survey "$d" OK; done + +# --- #354 gate: .data BOUNDED (not 64KB), --native-pointer-abi --- +echo "== #354 .data-bound check (--native-pointer-abi; bounded => per-region .bss split works) ==" +data_of() { $SIZE -A "$1" 2>/dev/null | awk '$1==".data"{print $2}'; } +# msgq decides exhibit the 64KB .data decide-only: +for d in gale_k_msgq_put_decide gale_k_msgq_get_decide; do + $WASMLD --no-entry --export="$d" --allow-undefined --gc-sections "$LIBFFI" -o "$t/m.wasm" 2>/dev/null + loom optimize "$t/m.wasm" --passes inline --attestation false -o "$t/m.lo.wasm" >/dev/null 2>&1 + $SYNTH compile "$t/m.lo.wasm" --target cortex-m4f --native-pointer-abi --all-exports --relocatable -o "$t/m.o2" 2>/dev/null + dd=$(data_of "$t/m.o2"); dd=${dd:-0} + if [ "$dd" -le 256 ]; then printf " %-30s .data=%-7s OK\n" "$d" "$dd" + else printf " %-30s .data=%-7s FAIL: 64KB blob (#354)\n" "$d" "$dd"; fail=1; fi +done +# stack exhibits it at full-shim level: +if [ -f "$STACK_SHIM" ]; then + $CLANG --target=wasm32-unknown-unknown -O2 -nostdlib -c "$STACK_SHIM" -o "$t/s.o" 2>/dev/null + $WASMLD --no-entry --export=z_impl_k_stack_push --export=gale_k_stack_push_decide --allow-undefined --gc-sections "$LIBFFI" "$t/s.o" -o "$t/s.wasm" 2>/dev/null + loom optimize "$t/s.wasm" --passes inline --attestation false -o "$t/s.lo.wasm" >/dev/null 2>&1 + $SYNTH compile "$t/s.lo.wasm" --target cortex-m4f --native-pointer-abi --all-exports --relocatable -o "$t/s.o2" 2>/dev/null + dd=$(data_of "$t/s.o2"); dd=${dd:-0} + if [ "$dd" -le 256 ]; then printf " %-30s .data=%-7s OK\n" "z_impl_k_stack_push(shim)" "$dd" + else printf " %-30s .data=%-7s FAIL: 64KB blob (#354)\n" "z_impl_k_stack_push(shim)" "$dd"; fail=1; fi +fi +echo "== $( [ $fail -eq 0 ] && echo 'GREEN — #350 + #354 cleared (stack/msgq compile + .data bounded)' || echo 'RED — see FAIL above (#350 compile and/or #354 .data)' ) ==" +exit $fail diff --git a/benches/engine_control/silicon/wasm-testbed/run_testbed.sh b/benches/engine_control/silicon/wasm-testbed/run_testbed.sh new file mode 100755 index 00000000..492a2c15 --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/run_testbed.sh @@ -0,0 +1,77 @@ +#!/usr/bin/env bash +# Self-contained wasm-cross-LTO testbed / regression suite. +# For each algorithm function, from source in this dir: +# 1. clang -> wasm-ld -> loom (dissolve) -> wasm module +# 2. FUNCTIONAL: wasmtime --invoke each vector vs the verified native-reference expected +# 3. CODEGEN: synth compile (cortex-m4f, --relocatable) must succeed (catches the +# v0.11.19-class register-exhaustion / skip regressions) +# +# Run on every new synth/loom release: `./run_testbed.sh`. Exit 0 = all green. +# Verified-correct expected values are ground truth (native gcc == wasmtime == on-silicon, +# established across the 2026-06-02 silicon runs; see ../runs/ and the spike NOTES). +# +# Tools: clang+wasm-ld (llvm), loom, synth, wasmtime on PATH. +set -u +CLANG="${CLANG:-/opt/homebrew/opt/llvm/bin/clang}" +WASMLD="${WASMLD:-/opt/homebrew/bin/wasm-ld}" +TGT=cortex-m4f +fail=0; tmp=$(mktemp -d) + +build() { # name exports-csv src... + local name="$1"; shift; local exports="$1"; shift + local objs="" + for s in "$@"; do local o="$tmp/${s%.c}.o"; "$CLANG" --target=wasm32-unknown-unknown -O2 -nostdlib -c "$s" -o "$o" 2>/dev/null || return 1; objs="$objs $o"; done + local exp_args=""; for e in ${exports//,/ }; do exp_args="$exp_args --export=$e"; done + "$WASMLD" --no-entry $exp_args --allow-undefined --gc-sections $objs -o "$tmp/$name.wasm" 2>/dev/null || return 1 + loom optimize "$tmp/$name.wasm" --passes inline --attestation false -o "$tmp/$name.loom.wasm" >/dev/null 2>&1 || return 1 +} +codegen_ok() { # name -> synth compiles all exports? + local out; out=$(synth compile "$tmp/$1.loom.wasm" --target $TGT --all-exports --relocatable -o "$tmp/$1.o" 2>&1) + if echo "$out" | grep -qiE 'register exhaustion|no functions compiled|skipping function'; then + echo " codegen: $(echo "$out" | grep -iE 'exhaustion|skipping' | head -1 | sed 's/^ *//')"; return 1; fi + return 0 +} +inv() { local fn="$1"; local args="$2"; wasmtime --invoke "$fn" "$tmp/$fn.loom.wasm" $args 2>/dev/null; } +chk() { if [ "$2" = "$3" ]; then echo " [OK ] $1 = $2"; else echo " [BAD] $1: got='$2' exp='$3'"; fail=1; fi; } + +echo "== wasm-cross-LTO testbed (synth $(synth --version|head -1|awk '{print $2}'), loom $(loom --version|head -1|awk '{print $2}')) ==" + +echo "control_step_decide (engine algo: 4 unsigned-const divides + 2 tables):" +if build control_step_decide control_step_decide control_wasm.c tables.c; then + codegen_ok control_step_decide && echo " [OK ] synth compiles" || { echo " [BAD] synth codegen"; fail=1; } + chk "(3000,50,90,0)" "$(inv control_step_decide '3000 50 90 0')" 2164988 + chk "(3000,50,40,0)" "$(inv control_step_decide '3000 50 40 0')" 2165333 + chk "(3000,50,0,0)" "$(inv control_step_decide '3000 50 0 0')" 2165678 + chk "(6000,80,40,3)" "$(inv control_step_decide '6000 80 40 3')" 2230501 +else echo " [BAD] build failed"; fail=1; fi + +echo "controller_step_decide (flight controller: SAR + saturation pack):" +if build controller_step_decide controller_step_decide controller_wasm.c; then + codegen_ok controller_step_decide && echo " [OK ] synth compiles" || { echo " [BAD] synth codegen"; fail=1; } + chk "(6400,0,-12800,0,3200,0,5)" "$(inv controller_step_decide '6400 0 -12800 0 3200 0 5')" 97419164 # 0x05ce7f9c + chk "(0,0,0,0,0,0,0)" "$(inv controller_step_decide '0 0 0 0 0 0 0')" 0 +else echo " [BAD] build failed"; fail=1; fi + +echo "filter_axis_decide (flight filter: signed mul + signed-const divide):" +if build filter_axis_decide filter_axis_decide filter_wasm.c; then + codegen_ok filter_axis_decide && echo " [OK ] synth compiles" || { echo " [BAD] synth codegen"; fail=1; } + chk "(0,0,0)" "$(inv filter_axis_decide '0 0 0')" 0 + chk "(1000,100,500)" "$(inv filter_axis_decide '1000 100 500')" 1088 + chk "(-2000,50,-300)" "$(inv filter_axis_decide '-2000 50 -300')" -1917 +else echo " [BAD] build failed"; fail=1; fi + +rm -rf "$tmp" + +echo "i64-unpack differential (synth#311 guard: wasmtime vs unicorn, packed-u64 return):" +u64out=$(python3 "$(dirname "$0")/u64_funccheck.py" 2>&1) && u64rc=0 || u64rc=1 +echo "$u64out" | sed 's/^/ /' +[ $u64rc -ne 0 ] && { echo " [BAD] i64-unpack lane RED (synth#311 class — silent wrong-code)"; fail=1; } + +echo +echo "kernel-primitives codegen lane (k_sem_give + k_mutex_unlock; synth#331 guard):" +bash "$(dirname "$0")/primitives_codegen_check.sh" 2>&1 | sed 's/^/ /' +prc=${PIPESTATUS[0]} +[ "$prc" -ne 0 ] && { echo " [BAD] kernel-primitives lane RED (codegen/seam-fold or synth#331 collision)"; fail=1; } + +echo "== $( [ $fail -eq 0 ] && echo 'ALL GREEN' || echo 'FAILURES — see [BAD] above' ) ==" +exit $fail diff --git a/benches/engine_control/silicon/wasm-testbed/seam_callee.c b/benches/engine_control/silicon/wasm-testbed/seam_callee.c new file mode 100644 index 00000000..43c5e418 --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/seam_callee.c @@ -0,0 +1,4 @@ +#include +struct S { int32_t a; int32_t b; }; +int32_t rd(struct S *s){ int32_t x = s->a + s->b; if (x>127) x=127; if (x<-127) x=-127; return x; } +void wr(struct S *s, int32_t v){ s->a = v; s->b = v >> 1; } diff --git a/benches/engine_control/silicon/wasm-testbed/seam_top.c b/benches/engine_control/silicon/wasm-testbed/seam_top.c new file mode 100644 index 00000000..e7e7da42 --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/seam_top.c @@ -0,0 +1,5 @@ +#include +struct S { int32_t a; int32_t b; }; +int32_t rd(struct S *s); void wr(struct S *s, int32_t v); +__attribute__((export_name("seam"))) +int32_t seam(struct S *s, int32_t v){ wr(s, v); return rd(s); } /* rd: single call site */ diff --git a/benches/engine_control/silicon/wasm-testbed/silicon-microbench/CMakeLists.txt b/benches/engine_control/silicon/wasm-testbed/silicon-microbench/CMakeLists.txt new file mode 100644 index 00000000..abc41f9f --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/silicon-microbench/CMakeLists.txt @@ -0,0 +1,6 @@ +cmake_minimum_required(VERSION 3.20.0) +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(filter_bench) +target_sources(app PRIVATE src/main.c) +# Link the synth-generated relocatable object (exports filter_axis_decide, self-contained, 0 relocs) +target_link_libraries(app PRIVATE /tmp/wasm-algo-poc/fv_algo.o) diff --git a/benches/engine_control/silicon/wasm-testbed/silicon-microbench/RESULT-2026-06-10-g474re-pr309-deadsave-elim.txt b/benches/engine_control/silicon/wasm-testbed/silicon-microbench/RESULT-2026-06-10-g474re-pr309-deadsave-elim.txt new file mode 100644 index 00000000..a2a00433 --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/silicon-microbench/RESULT-2026-06-10-g474re-pr309-deadsave-elim.txt @@ -0,0 +1,9 @@ +*** Booting Zephyr OS build v4.4.0-7-g719cc4890346 *** +SELFCHECK full s=1088 n=1088 (exp 1088) div s=-1917 n=-1917 (exp -1917) +E,full ,synth=29,native=19 +E,nodiv,synth=21,native=12 +E,div ,synth=22,native=15 +SINK=436128800 ovh=1 +=== END === + +# PR #309 (pre-merge b762ac1, v0.11.36 candidate): realloc default-ON + dead callee-saved-save elim v1. -8 cyc uniform (37/29/30 -> 29/21/22). big-3 byte-identical. Posted PR comment 4671097907. diff --git a/benches/engine_control/silicon/wasm-testbed/silicon-microbench/RESULT-2026-06-10-g474re-v0.11.35-flag-off.txt b/benches/engine_control/silicon/wasm-testbed/silicon-microbench/RESULT-2026-06-10-g474re-v0.11.35-flag-off.txt new file mode 100644 index 00000000..319629d2 --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/silicon-microbench/RESULT-2026-06-10-g474re-v0.11.35-flag-off.txt @@ -0,0 +1,8 @@ +*** Booting Zephyr OS build v4.4.0-7-g719cc4890346 *** +SELFCHECK full s=1088 n=1088 (exp 1088) div s=-1917 n=-1917 (exp -1917) +E,full ,synth=37,native=19 +E,nodiv,synth=29,native=12 +E,div ,synth=30,native=15 +SINK=436128800 ovh=1 +=== END === + diff --git a/benches/engine_control/silicon/wasm-testbed/silicon-microbench/RESULT-2026-06-10-g474re-v0.11.35-realloc-flag-on.txt b/benches/engine_control/silicon/wasm-testbed/silicon-microbench/RESULT-2026-06-10-g474re-v0.11.35-realloc-flag-on.txt new file mode 100644 index 00000000..fa0f8df2 --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/silicon-microbench/RESULT-2026-06-10-g474re-v0.11.35-realloc-flag-on.txt @@ -0,0 +1,9 @@ +*** Booting Zephyr OS build v4.4.0-7-g719cc4890346 *** +SELFCHECK full s=1088 n=1088 (exp 1088) div s=-1917 n=-1917 (exp -1917) +E,full ,synth=37,native=19 +E,nodiv,synth=29,native=12 +E,div ,synth=30,native=15 +SINK=436128800 ovh=1 +=== END === + +# main b657521 SYNTH_RANGE_REALLOC=1: cycles identical to flag-off (37/29/30), regs packed r4-r8->r0/r1. Gate-clearing data posted to synth#209. diff --git a/benches/engine_control/silicon/wasm-testbed/silicon-microbench/build_fv_algo.sh b/benches/engine_control/silicon/wasm-testbed/silicon-microbench/build_fv_algo.sh new file mode 100755 index 00000000..f35aea3d --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/silicon-microbench/build_fv_algo.sh @@ -0,0 +1,14 @@ +#!/usr/bin/env bash +# Rebuild /tmp/wasm-algo-poc/fv_algo.o (the 3-variant filter decomposition object +# linked by CMakeLists.txt). /tmp gets cleaned by macOS — rerun this when it does. +# SYNTH_RANGE_REALLOC=1 may be exported to build the flag-on variant. +set -euo pipefail +SYNTH="${SYNTH:-synth}"; CLANG=/opt/homebrew/opt/llvm/bin/clang; WASMLD=/opt/homebrew/bin/wasm-ld +TC=/Volumes/Home/zephyr-sdk/zephyr-sdk-1.0.1/gnu/arm-zephyr-eabi/bin/arm-zephyr-eabi +HERE=$(cd "$(dirname "$0")" && pwd); mkdir -p /tmp/wasm-algo-poc; cd /tmp/wasm-algo-poc +$CLANG --target=wasm32-unknown-unknown -O2 -nostdlib -c "$HERE/fv_algo.c" -o fv.o +$WASMLD --no-entry --export=full --export=nodiv --export=div --allow-undefined --gc-sections fv.o -o fv.wasm +loom optimize fv.wasm --passes inline --attestation false -o fv.loom.wasm >/dev/null +"$SYNTH" compile fv.loom.wasm --target cortex-m4f --all-exports --relocatable -o fv_algo.raw.o +"$TC-objcopy" --redefine-sym full=v_full --redefine-sym nodiv=v_nodiv --redefine-sym div=v_div fv_algo.raw.o fv_algo.o +echo "wrote /tmp/wasm-algo-poc/fv_algo.o (synth $($SYNTH --version | awk '{print $2}'))" diff --git a/benches/engine_control/silicon/wasm-testbed/silicon-microbench/fv_algo.c b/benches/engine_control/silicon/wasm-testbed/silicon-microbench/fv_algo.c new file mode 100644 index 00000000..5089e232 --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/silicon-microbench/fv_algo.c @@ -0,0 +1,4 @@ +#include +__attribute__((export_name("full"))) int32_t full(int32_t p,int32_t g,int32_t a){ int32_t t=p+g; return (t*980+a*20)/1000; } +__attribute__((export_name("nodiv"))) int32_t nodiv(int32_t p,int32_t g,int32_t a){ int32_t t=p+g; return t*980+a*20; } +__attribute__((export_name("div"))) int32_t divv(int32_t x){ return x/1000; } diff --git a/benches/engine_control/silicon/wasm-testbed/silicon-microbench/prj.conf b/benches/engine_control/silicon/wasm-testbed/silicon-microbench/prj.conf new file mode 100644 index 00000000..5b8d9300 --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/silicon-microbench/prj.conf @@ -0,0 +1,5 @@ +CONFIG_PRINTK=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_MAIN_STACK_SIZE=2048 diff --git a/benches/engine_control/silicon/wasm-testbed/silicon-microbench/src/main.c b/benches/engine_control/silicon/wasm-testbed/silicon-microbench/src/main.c new file mode 100644 index 00000000..931f42ff --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/silicon-microbench/src/main.c @@ -0,0 +1,54 @@ +/* Decompose the wasm-cross-LTO vs native gap on filter_axis, on real silicon. + * Three synth functions (v_full / v_nodiv / v_div) vs native gcc equivalents, + * all called via volatile fn-ptr (thumb bit set; synth#170 = no $t symbol) so + * call overhead is identical. DWT CYCCNT @170 MHz, min over 200 iters. */ +#include +#include + +#define DEMCR (*(volatile uint32_t *)0xE000EDFCu) +#define DWT_CTRL (*(volatile uint32_t *)0xE0001000u) +#define DWT_CYCCNT (*(volatile uint32_t *)0xE0001004u) + +extern char v_full, v_nodiv, v_div; /* synth symbols in fv_algo.o */ +typedef int32_t (*f3_t)(int32_t, int32_t, int32_t); +typedef int32_t (*f1_t)(int32_t); + +__attribute__((noinline)) int32_t n_full(int32_t p,int32_t g,int32_t a){ int32_t t=p+g; return (t*980+a*20)/1000; } +__attribute__((noinline)) int32_t n_nodiv(int32_t p,int32_t g,int32_t a){ int32_t t=p+g; return t*980+a*20; } +__attribute__((noinline)) int32_t n_div(int32_t x){ return x/1000; } + +static inline void dwt_init(void){ DEMCR |= (1u<<24); DWT_CYCCNT = 0; DWT_CTRL |= 1u; } + +static uint32_t m3(f3_t fn,int32_t p,int32_t g,int32_t a,volatile int32_t*s){ + uint32_t best=0xFFFFFFFFu; + for(int i=0;i<200;i++){ uint32_t t0=DWT_CYCCNT; int32_t r=fn(p,g,a); uint32_t t1=DWT_CYCCNT; *s+=r; uint32_t d=t1-t0; if(d + +#define RPM_BINS 20 +#define LOAD_BINS 20 + +/* + * Ignition map: spark advance in degrees BTDC, indexed [rpm_bin][load_bin]. + * More advance at high RPM / low load, less at low RPM / high load + * (classic knock-limit curve). + */ +const int8_t spark_advance_table[RPM_BINS][LOAD_BINS] = { + /* 0 RPM: 0% load ... 95% load */ + { 10,10,10,10,10, 12,12,12,12,12, 14,14,14,14,14, 14,14,14,14,14 }, + /* 500 */ + { 12,12,12,13,13, 14,14,14,15,15, 16,16,16,17,17, 18,18,18,18,18 }, + /* 1000 */ + { 15,15,16,16,17, 17,18,18,19,19, 20,20,20,21,21, 22,22,22,22,22 }, + /* 1500 */ + { 18,18,19,19,20, 20,21,21,22,22, 23,23,23,24,24, 25,25,25,25,25 }, + /* 2000 */ + { 20,21,21,22,23, 23,24,24,25,26, 26,27,27,28,28, 29,29,29,29,28 }, + /* 2500 */ + { 22,23,24,25,26, 26,27,28,28,29, 30,30,31,31,32, 32,32,32,31,30 }, + /* 3000 */ + { 24,25,26,27,28, 29,30,30,31,32, 33,33,34,34,35, 35,35,34,33,32 }, + /* 3500 */ + { 26,27,28,29,30, 31,32,33,34,34, 35,36,36,37,37, 37,36,35,34,33 }, + /* 4000 */ + { 28,29,30,31,32, 33,34,35,36,37, 37,38,38,39,39, 38,37,36,35,34 }, + /* 4500 */ + { 29,30,31,32,33, 34,35,36,37,38, 38,39,39,40,39, 38,37,36,35,34 }, + /* 5000 */ + { 30,31,32,33,34, 35,36,37,38,39, 39,40,40,40,39, 38,37,36,35,34 }, + /* 5500 */ + { 31,32,33,34,35, 36,37,38,39,39, 40,40,40,40,39, 38,37,36,35,34 }, + /* 6000 */ + { 32,33,34,35,36, 37,38,39,39,40, 40,40,40,40,39, 38,37,36,35,34 }, + /* 6500 */ + { 33,34,35,36,37, 38,38,39,40,40, 40,40,40,39,39, 38,37,36,35,34 }, + /* 7000 */ + { 34,35,36,37,38, 38,39,39,40,40, 40,40,40,39,38, 37,36,35,34,33 }, + /* 7500 */ + { 35,36,37,37,38, 39,39,40,40,40, 40,39,39,38,38, 37,36,35,34,33 }, + /* 8000 */ + { 36,36,37,38,38, 39,39,40,40,40, 39,39,38,38,37, 36,35,34,33,32 }, + /* 8500 */ + { 36,37,37,38,38, 39,39,40,40,39, 39,38,38,37,36, 35,34,33,32,31 }, + /* 9000 */ + { 36,37,37,38,38, 39,39,39,39,39, 38,38,37,36,35, 34,33,32,31,30 }, + /* 9500 */ + { 35,36,37,37,38, 38,38,39,38,38, 37,37,36,35,34, 33,32,31,30,29 }, +}; + +/* + * Fuel map: injector pulse width in microseconds, indexed [rpm_bin][load_bin]. + * Higher load = more fuel; high RPM = shorter time budget per pulse. + * Values sized for a ~3 bar fuel rail + 180 cc/min injector. + */ +const uint16_t fuel_duration_table[RPM_BINS][LOAD_BINS] = { + { 1200,1400,1600,1800,2000, 2200,2400,2600,2800,3000, 3200,3400,3600,3800,4000, 4200,4400,4600,4800,5000 }, + { 1150,1340,1530,1720,1910, 2100,2290,2480,2670,2860, 3050,3240,3430,3620,3810, 4000,4190,4380,4570,4760 }, + { 1100,1280,1460,1640,1820, 2000,2180,2360,2540,2720, 2900,3080,3260,3440,3620, 3800,3980,4160,4340,4520 }, + { 1050,1220,1390,1560,1730, 1900,2070,2240,2410,2580, 2750,2920,3090,3260,3430, 3600,3770,3940,4110,4280 }, + { 1000,1160,1320,1480,1640, 1800,1960,2120,2280,2440, 2600,2760,2920,3080,3240, 3400,3560,3720,3880,4040 }, + { 950,1100,1250,1400,1550, 1700,1850,2000,2150,2300, 2450,2600,2750,2900,3050, 3200,3350,3500,3650,3800 }, + { 900,1040,1180,1320,1460, 1600,1740,1880,2020,2160, 2300,2440,2580,2720,2860, 3000,3140,3280,3420,3560 }, + { 860, 990,1120,1250,1380, 1510,1640,1770,1900,2030, 2160,2290,2420,2550,2680, 2810,2940,3070,3200,3330 }, + { 820, 940,1060,1180,1300, 1420,1540,1660,1780,1900, 2020,2140,2260,2380,2500, 2620,2740,2860,2980,3100 }, + { 790, 900,1010,1120,1230, 1340,1450,1560,1670,1780, 1890,2000,2110,2220,2330, 2440,2550,2660,2770,2880 }, + { 760, 860, 960,1060,1160, 1260,1360,1460,1560,1660, 1760,1860,1960,2060,2160, 2260,2360,2460,2560,2660 }, + { 730, 820, 910,1000,1090, 1180,1270,1360,1450,1540, 1630,1720,1810,1900,1990, 2080,2170,2260,2350,2440 }, + { 700, 780, 860, 940,1020, 1100,1180,1260,1340,1420, 1500,1580,1660,1740,1820, 1900,1980,2060,2140,2220 }, + { 675, 750, 825, 900, 975, 1050,1125,1200,1275,1350, 1425,1500,1575,1650,1725, 1800,1875,1950,2025,2100 }, + { 650, 720, 790, 860, 930, 1000,1070,1140,1210,1280, 1350,1420,1490,1560,1630, 1700,1770,1840,1910,1980 }, + { 625, 690, 755, 820, 885, 950,1015,1080,1145,1210, 1275,1340,1405,1470,1535, 1600,1665,1730,1795,1860 }, + { 600, 660, 720, 780, 840, 900, 960,1020,1080,1140, 1200,1260,1320,1380,1440, 1500,1560,1620,1680,1740 }, + { 580, 636, 692, 748, 804, 860, 916, 972,1028,1084, 1140,1196,1252,1308,1364, 1420,1476,1532,1588,1644 }, + { 560, 614, 668, 722, 776, 830, 884, 938, 992,1046, 1100,1154,1208,1262,1316, 1370,1424,1478,1532,1586 }, + { 540, 592, 644, 696, 748, 800, 852, 904, 956,1008, 1060,1112,1164,1216,1268, 1320,1372,1424,1476,1528 }, +}; diff --git a/benches/engine_control/silicon/wasm-testbed/u64_funccheck.py b/benches/engine_control/silicon/wasm-testbed/u64_funccheck.py new file mode 100755 index 00000000..a4b73c5e --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/u64_funccheck.py @@ -0,0 +1,109 @@ +#!/usr/bin/env python3 +"""i64-unpack differential lane (synth#311 regression guard). + +Builds u64repro.c through clang->wasm-ld->loom->synth (cortex-m4f), then +checks the SAME call differentially: + wasmtime (wasm ground truth) check(3,4) == 8, check(0,0) == 1 + unicorn (synth ARM execution) must match + +synth#311: the ARM i64 shift/mask unpack materialized its constants into the +live u64 register pair (r0/r1), silently corrupting packed-u64 returns — +k_sem_give dropped its count update and the engine_control bench hung with no +fault. This lane turns that silent wrong-code into a red testbed line. +""" +import glob, os, struct, subprocess, sys, tempfile + +HERE = os.path.dirname(os.path.abspath(__file__)) +TC = "/Volumes/Home/zephyr-sdk/zephyr-sdk-1.0.1/gnu/arm-zephyr-eabi/bin/arm-zephyr-eabi" +CLANG = "/opt/homebrew/opt/llvm/bin/clang" +WASMLD = "/opt/homebrew/bin/wasm-ld" +SYNTH = os.environ.get("SYNTH", "synth") +VECTORS = [((3, 4), 8), ((0, 0), 1), ((1000, 99), 1100), ((0xFFFF, 1), 0x10001)] +RV = "/Volumes/Home/git/zephyr/zephyr-sdk-0.17.4/riscv64-zephyr-elf/bin/riscv64-zephyr-elf" + +def run(cmd, **kw): + r = subprocess.run(cmd, capture_output=True, text=True, **kw) + if r.returncode != 0: + raise RuntimeError(f"{' '.join(cmd)}\n{r.stderr[-400:]}") + return r.stdout + +def main(): + t = tempfile.mkdtemp() + run([CLANG, "--target=wasm32-unknown-unknown", "-O2", "-nostdlib", + "-c", os.path.join(HERE, "u64repro.c"), "-o", f"{t}/u.o"]) + run([WASMLD, "--no-entry", "--export=check", "--allow-undefined", + "--gc-sections", f"{t}/u.o", "-o", f"{t}/u.wasm"]) + run(["loom", "optimize", f"{t}/u.wasm", "--passes", "inline", + "--attestation", "false", "-o", f"{t}/u.loom.wasm"]) + run([SYNTH, "compile", f"{t}/u.loom.wasm", "--target", "cortex-m4f", + "--all-exports", "--relocatable", "-o", f"{t}/u.arm.o"]) + run([f"{TC}-ld", "-Ttext=0x8000", "--entry=check", f"{t}/u.arm.o", "-o", f"{t}/u.elf"]) + run([f"{TC}-objcopy", "-O", "binary", "--only-section=.text", f"{t}/u.elf", f"{t}/u.bin"]) + entry = next(int(l.split()[0], 16) for l in + run([f"{TC}-nm", f"{t}/u.elf"]).splitlines() if l.endswith(" T check")) + + from unicorn import Uc, UC_ARCH_ARM, UC_MODE_THUMB, UcError + from unicorn.arm_const import (UC_ARM_REG_R0, UC_ARM_REG_R1, UC_ARM_REG_R11, + UC_ARM_REG_SP, UC_ARM_REG_LR) + # RV32 leg (synth#312 guard): same module through -b riscv, executed + # under unicorn RISCV32. Was a hard selector rejection before v0.11.37. + rv32_ok = True + try: + run([SYNTH, "compile", f"{t}/u.loom.wasm", "-b", "riscv", "-t", "rv32imac", + "--all-exports", "--relocatable", "-o", f"{t}/u.rv32.o"]) + run([f"{RV}-ld", "-m", "elf32lriscv", "-Ttext=0x80000000", "--entry=check", + f"{t}/u.rv32.o", "-o", f"{t}/u.rv32.elf"]) + run([f"{RV}-objcopy", "-O", "binary", "--only-section=.text", + f"{t}/u.rv32.elf", f"{t}/u.rv32.bin"]) + rv_entry = next(int(l.split()[0], 16) for l in + run([f"{RV}-nm", f"{t}/u.rv32.elf"]).splitlines() + if l.endswith(" T check")) + except (RuntimeError, StopIteration) as e: + print(f"FAIL rv32 compile/link: {e}") + rv32_ok = False + + ok = True + for (a, b), exp in VECTORS: + wt = int(run(["wasmtime", "run", "--invoke", "check", + f"{t}/u.loom.wasm", str(a), str(b)]).strip() or -1) + mu = Uc(UC_ARCH_ARM, UC_MODE_THUMB) + mu.mem_map(0x0, 0x10000); mu.mem_map(0x20000000, 0x10000) + mu.mem_write(0x8000, open(f"{t}/u.bin", "rb").read()) + mu.reg_write(UC_ARM_REG_R0, a); mu.reg_write(UC_ARM_REG_R1, b) + mu.reg_write(UC_ARM_REG_R11, 0) + mu.reg_write(UC_ARM_REG_SP, 0x20008000) + mu.reg_write(UC_ARM_REG_LR, 0xDEAD0001) + try: + mu.emu_start(entry | 1, 0xDEAD0000, timeout=2_000_000, count=10000) + arm = mu.reg_read(UC_ARM_REG_R0) + except UcError as e: + arm = f"FAULT({e})" + rv = "-" + if rv32_ok: + from unicorn import UC_ARCH_RISCV, UC_MODE_RISCV32 + from unicorn.riscv_const import (UC_RISCV_REG_A0, UC_RISCV_REG_A1, + UC_RISCV_REG_SP, UC_RISCV_REG_RA, + UC_RISCV_REG_S11) + rmu = Uc(UC_ARCH_RISCV, UC_MODE_RISCV32) + rmu.mem_map(0x80000000, 0x10000) + rmu.mem_map(0x80100000, 0x10000) + rmu.mem_map(0x90000000, 0x1000) + rmu.mem_write(0x80000000, open(f"{t}/u.rv32.bin", "rb").read()) + rmu.reg_write(UC_RISCV_REG_A0, a); rmu.reg_write(UC_RISCV_REG_A1, b) + rmu.reg_write(UC_RISCV_REG_SP, 0x80108000) + rmu.reg_write(UC_RISCV_REG_S11, 0) + rmu.reg_write(UC_RISCV_REG_RA, 0x90000000) + try: + rmu.emu_start(rv_entry, 0x90000000, timeout=2_000_000, count=20000) + rv = rmu.reg_read(UC_RISCV_REG_A0) + except UcError as e: + rv = f"FAULT({e})" + good = (wt == exp == arm) and (not rv32_ok or rv == exp) + ok &= good + print(f"{'PASS' if good else 'FAIL'} check({a},{b}): wasm={wt} arm={arm} rv32={rv} exp={exp}") + ok &= rv32_ok + print("== U64 FUNCCHECK:", "ALL GREEN ==" if ok else "RED (synth#311/#312 class) ==") + sys.exit(0 if ok else 1) + +if __name__ == "__main__": + main() diff --git a/benches/engine_control/silicon/wasm-testbed/u64repro.c b/benches/engine_control/silicon/wasm-testbed/u64repro.c new file mode 100644 index 00000000..139e23d1 --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/u64repro.c @@ -0,0 +1,10 @@ +#include +__attribute__((noinline)) uint64_t make(uint32_t a, uint32_t b) { + return (uint64_t)(a + b + 1) << 32 | 1u; +} +__attribute__((export_name("check"))) uint32_t check(uint32_t a, uint32_t b) { + uint64_t r = make(a, b); + uint32_t action = (uint32_t)(r & 0xFFu); /* expect 1 */ + uint32_t val = (uint32_t)(r >> 32); /* expect a+b+1 */ + return action == 1u ? val : 0xDEADu; +} diff --git a/benches/engine_control/silicon/wasm-testbed/wasm_oracle.sh b/benches/engine_control/silicon/wasm-testbed/wasm_oracle.sh new file mode 100755 index 00000000..f24ab987 --- /dev/null +++ b/benches/engine_control/silicon/wasm-testbed/wasm_oracle.sh @@ -0,0 +1,38 @@ +#!/usr/bin/env bash +# Host-side wasm functional oracle for the engine_control algorithm. +# Runs control_step_decide in wasmtime and checks against the native reference. +# Part of the "test environment as wasm" testbed: lets us verify functional +# correctness of any synth/loom input WITHOUT hardware. +# +# NOTE: wasmtime --invoke must be called one-shot per process; capturing it in a +# shell loop subshell came back empty in testing, so we run each vector explicitly. +set -u +WASM="${1:-control.loom.wasm}" +EXPECT=(2164988 2165333 2165678 2230501) # native reference, packed spark<<16|fuel +ARGS=("3000 50 90 0" "3000 50 40 0" "3000 50 0 0" "6000 80 40 3") +fail=0 +for i in 0 1 2 3; do + got=$(wasmtime --invoke control_step_decide "$WASM" ${ARGS[$i]} 2>/dev/null) + exp=${EXPECT[$i]} + spark=$(( (got>>16) & 0xffff )); fuel=$(( got & 0xffff )) + if [ "$got" = "$exp" ]; then mark="OK "; else mark="BAD"; fail=1; fi + printf "[%s] (%s) got=%s exp=%s spark=%d fuel=%d\n" "$mark" "${ARGS[$i]}" "$got" "$exp" "$spark" "$fuel" +done +echo "--- controller_step_decide (flight_control) ---" +CEXP=(0x00000000 0x05ce7f9c 0x07000081 0xff7fc27f) # native reference build of controller_step +CARGS=("0 0 0 0 0 0 0" "6400 0 -12800 0 3200 0 5" "100000 0 0 0 0 0 7" "-100000 256 4096 -256 -8192 128 255") +for i in 0 1 2 3; do + got=$(wasmtime --invoke controller_step_decide controller.loom.wasm ${CARGS[$i]} 2>/dev/null) + gotu=$(printf "0x%08x" $(( got & 0xffffffff ))); exp=${CEXP[$i]} + if [ "$gotu" = "$exp" ]; then m="OK "; else m="BAD"; fail=1; fi + printf "[%s] (%s) got=%s exp=%s\n" "$m" "${CARGS[$i]}" "$gotu" "$exp" +done +echo "--- filter_axis_decide (flight_control) ---" +FEXP=(0 1088 -1917 1); FARGS=("0 0 0" "1000 100 500" "-2000 50 -300" "0 2 0") +for i in 0 1 2 3; do + got=$(wasmtime --invoke filter_axis_decide filter.loom.wasm ${FARGS[$i]} 2>/dev/null) + if [ "$got" = "${FEXP[$i]}" ]; then m="OK "; else m="BAD"; fail=1; fi + printf "[%s] (%s) got=%s exp=%s\n" "$m" "${FARGS[$i]}" "$got" "${FEXP[$i]}" +done +[ $fail -eq 0 ] && echo "ALL PASS" || echo "MISMATCH" +exit $fail diff --git a/benches/engine_control/src/main.c b/benches/engine_control/src/main.c index e5091f92..16bdcb83 100644 --- a/benches/engine_control/src/main.c +++ b/benches/engine_control/src/main.c @@ -40,10 +40,31 @@ #include #include "control.h" +#include "smart_dwt.h" +#include "smart_mcu.h" /* ------------------------------------------------------------- knobs */ -#define RING_CAPACITY_SAMPLES 256 +/* Sized to absorb the biggest single-step ISR burst on real silicon + * without dropping. The long-sweep's largest step is 1000 samples + * (steps 3-7); even with the reader stuck on a full UART buffer for + * the duration of the burst, 2048 fits 1000 with headroom. RAM cost: + * 2048 × sizeof(crank_sample) ≈ 32 KB on STM32G4 (16 KB→48 KB, + * 12% → 37% of the 128 KB SRAM). Previous value (256) caused 56% + * sample drops at high RPM under 115200-baud UART throughput, + * biasing per-RPM medians. + * + * The large ring is gated on real STM32G4 silicon: that is the only + * target with both the 128 KB SRAM to hold it AND the real 115200-baud + * UART back-pressure that caused the drops. The QEMU/Renode CI lanes + * run on lm3s6965 (64 KB SRAM) where 32 KB of `noinit` overflows RAM, + * and they never dropped a sample at 256 (no real UART drain limit), + * so they keep the smaller ring. */ +#if defined(CONFIG_SOC_SERIES_STM32G4X) +# define RING_CAPACITY_SAMPLES 2048 +#else +# define RING_CAPACITY_SAMPLES 256 +#endif struct sweep_step { uint32_t rpm; @@ -124,6 +145,12 @@ static volatile uint32_t g_interrupts = 0U; * could notice the sample count had been reached. */ static volatile uint32_t g_fire_budget = 0U; +/* End-of-sweep handshake. sweep_driver sets this true after its final + * drain; reader_loop polls it (with a short k_sem_take timeout) so + * the bench terminates cleanly even when high-RPM steps drop samples + * and `count` plateaus below TOTAL_SAMPLES. */ +static volatile bool g_sweep_done = false; + /* Side-channel array for handoff_cycles. The ISR measures t_exit AFTER * ring_buf_put (which is the point — handoff cost includes the put + * sem_give). But by then the sample bytes are already in the ring, so @@ -258,14 +285,28 @@ static void emit_event(const struct crank_sample *s) static void reader_loop(void) { - while (count < TOTAL_SAMPLES) { - k_sem_take(&data_ready, K_FOREVER); + /* Exit when sweep_driver has signalled done AND the ring is fully + * drained. Use a 500 ms semaphore timeout so we wake periodically + * to re-check the exit condition even if no samples are arriving + * (which is the normal end-of-sweep state). The previous design + * waited K_FOREVER on the semaphore and exited only when + * `count >= TOTAL_SAMPLES`, which hangs the bench whenever a + * step drops samples (count never catches up). */ + while (!g_sweep_done + || ring_buf_size_get(&sample_ring) >= sizeof(struct crank_sample)) { + if (k_sem_take(&data_ready, K_MSEC(500)) != 0) { + /* Semaphore timeout — loop back and re-check the exit + * condition. If the sweep is still firing, the next + * sample will give the semaphore quickly. If we're at + * end-of-sweep, the loop guard will see g_sweep_done + * and exit. */ + continue; + } struct crank_sample s; while (ring_buf_get(&sample_ring, (uint8_t *)&s, sizeof(s)) == sizeof(s)) { emit_event(&s); count++; - if (count >= TOTAL_SAMPLES) break; } } } @@ -289,10 +330,28 @@ static void print_csv_header(void) printf("overhead_cycles,%u\n", bench_overhead_cycles); printf("# event rows: E,,,,,\n"); printf("# algo / handoff cycles are AFTER subtracting overhead_cycles\n"); + printf("# DWT rows: D,,,,,,,\n"); + printf("# health rows:H,,,,\n"); + + struct dwt_snapshot d; + smart_dwt_snapshot(&d); + smart_dwt_emit("boot", &d); + + struct mcu_health h; + smart_mcu_snapshot(&h); + smart_mcu_emit("boot", &h); } static void print_csv_footer(void) { + struct dwt_snapshot d; + smart_dwt_snapshot(&d); + smart_dwt_emit("end", &d); + + struct mcu_health h; + smart_mcu_snapshot(&h); + smart_mcu_emit("end", &h); + printf("drops,%u\n", g_drops); printf("samples,%u\n", count); printf("=== END ===\n"); @@ -340,12 +399,13 @@ static void sweep_driver(void) /* Drain between steps — the reader emits events over UART * which is the slow path. Without this back-pressure the * ring fills and subsequent ISRs drop samples. We wait for - * the reader to catch up (or give up after a generous - * ceiling so a stuck UART doesn't hang CI forever). */ + * the ring to actually empty (rather than count to hit + * `target`, which can never happen when high-RPM steps drop + * samples). 30s ceiling so a stuck UART doesn't hang CI. */ + (void)start_ints; /* sweep-step diagnostics only — see step printf below */ uint32_t drain_t0 = k_uptime_get_32(); - uint32_t target = start_ints + sweep[i].samples; bool drain_timeout = false; - while (count < target && count < g_interrupts) { + while (ring_buf_size_get(&sample_ring) >= sizeof(struct crank_sample)) { if ((k_uptime_get_32() - drain_t0) > 30000U) { drain_timeout = true; break; @@ -363,17 +423,33 @@ static void sweep_driver(void) (unsigned)count, budget_exceeded ? " [budget_exceeded]" : "", drain_timeout ? " [drain_timeout]" : ""); + + /* Smart-data per-step boundary: DWT + MCU health. Same + * "ISR is quiescent, reader has drained" guarantees as + * the marker printf — no interleaving with E rows. */ + char tag[16]; + snprintf(tag, sizeof(tag), "step_%u", (unsigned)(i + 1)); + struct dwt_snapshot d; + smart_dwt_snapshot(&d); + smart_dwt_emit(tag, &d); + struct mcu_health h; + smart_mcu_snapshot(&h); + smart_mcu_emit(tag, &h); } - /* Final drain. Cap at g_interrupts so we don't hang forever if a - * step hit its budget and produced fewer than planned samples. */ + /* Final drain — wait for the ring to fully empty so the reader can + * emit any in-flight samples before we signal end-of-sweep. */ uint32_t final_t0 = k_uptime_get_32(); - while (count < TOTAL_SAMPLES && count < g_interrupts) { + while (ring_buf_size_get(&sample_ring) >= sizeof(struct crank_sample)) { if ((k_uptime_get_32() - final_t0) > 30000U) { printk("final drain timeout; count=%u\n", (unsigned)count); break; } k_msleep(5); } + /* Signal end-of-sweep. reader_loop polls this with a 500 ms + * semaphore timeout and exits cleanly even when high-RPM steps + * dropped samples (count plateaus below TOTAL_SAMPLES). */ + g_sweep_done = true; } /* -------------------------------------------------------------- main */ @@ -390,6 +466,12 @@ int main(void) "(target %u samples, %u sweep steps)\n", TOTAL_SAMPLES, (unsigned)SWEEP_STEPS); + /* Bring up smart-data sources before any benchmarking work so the + * boot snapshot in print_csv_header reflects a clean state. DWT + * is universally available on ARMv7-M; MCU health may be a stub. */ + smart_dwt_enable(); + (void)smart_mcu_init(); + k_thread_priority_set(k_current_get(), 5); /* Measure framework overhead BEFORE the CSV header so the value diff --git a/benches/engine_control/src/smart_dwt.c b/benches/engine_control/src/smart_dwt.c new file mode 100644 index 00000000..85f410e4 --- /dev/null +++ b/benches/engine_control/src/smart_dwt.c @@ -0,0 +1,88 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * Copyright (c) 2026 PulseEngine + * + * DWT counter snapshot — implementation. + * + * Direct MMIO instead of CMSIS macros to keep this file independent + * of which CMSIS header bundle Zephyr happens to ship for the target + * SoC. The register addresses below are ARMv7-M architecture-defined + * (DDI0403E.e §C1.6, "DWT Memory Map") and identical across Cortex-M3, + * M4, and M7. ARMv8-M (M33/M55) is also compatible at this level. + */ + +#include +#include + +#include "smart_dwt.h" + +#define DCB_DEMCR_ADDR 0xE000EDFCu /* Debug Exception and Monitor Control */ +#define DCB_DEMCR_TRCENA (1u << 24) + +#define DWT_CTRL_ADDR 0xE0001000u +#define DWT_CYCCNT_ADDR 0xE0001004u +#define DWT_CPICNT_ADDR 0xE0001008u +#define DWT_EXCCNT_ADDR 0xE000100Cu +#define DWT_SLEEPCNT_ADDR 0xE0001010u +#define DWT_LSUCNT_ADDR 0xE0001014u +#define DWT_FOLDCNT_ADDR 0xE0001018u + +#define DWT_CTRL_CYCCNTENA (1u << 0) +#define DWT_CTRL_CPIEVTENA (1u << 17) +#define DWT_CTRL_EXCEVTENA (1u << 18) +#define DWT_CTRL_SLEEPEVT (1u << 19) +#define DWT_CTRL_LSUEVTENA (1u << 20) +#define DWT_CTRL_FOLDEVTNA (1u << 21) +/* Hardware-level event-counter enables. The "EVTENA" bits gate the + * external trace output for those events; the counters themselves + * increment whenever the corresponding microarchitectural event + * occurs. We set them anyway so that, if a future bench is hooked + * up to a SWO trace probe, the events are visible there too. */ + +#define MMIO32(addr) (*(volatile uint32_t *)(uintptr_t)(addr)) + +void smart_dwt_enable(void) +{ + MMIO32(DCB_DEMCR_ADDR) |= DCB_DEMCR_TRCENA; + + /* Reset the counters to a known starting point. CYCCNT is a + * 32-bit field; the others are 8-bit fields in their own + * registers but writing 0 is the conventional reset. */ + MMIO32(DWT_CYCCNT_ADDR) = 0u; + MMIO32(DWT_CPICNT_ADDR) = 0u; + MMIO32(DWT_EXCCNT_ADDR) = 0u; + MMIO32(DWT_SLEEPCNT_ADDR) = 0u; + MMIO32(DWT_LSUCNT_ADDR) = 0u; + MMIO32(DWT_FOLDCNT_ADDR) = 0u; + + uint32_t ctrl = MMIO32(DWT_CTRL_ADDR); + ctrl |= DWT_CTRL_CYCCNTENA + | DWT_CTRL_CPIEVTENA + | DWT_CTRL_EXCEVTENA + | DWT_CTRL_SLEEPEVT + | DWT_CTRL_LSUEVTENA + | DWT_CTRL_FOLDEVTNA; + MMIO32(DWT_CTRL_ADDR) = ctrl; +} + +void smart_dwt_snapshot(struct dwt_snapshot *out) +{ + out->cyccnt = MMIO32(DWT_CYCCNT_ADDR); + out->cpicnt = (uint8_t)(MMIO32(DWT_CPICNT_ADDR) & 0xFFu); + out->exccnt = (uint8_t)(MMIO32(DWT_EXCCNT_ADDR) & 0xFFu); + out->sleepcnt = (uint8_t)(MMIO32(DWT_SLEEPCNT_ADDR) & 0xFFu); + out->lsucnt = (uint8_t)(MMIO32(DWT_LSUCNT_ADDR) & 0xFFu); + out->foldcnt = (uint8_t)(MMIO32(DWT_FOLDCNT_ADDR) & 0xFFu); +} + +void smart_dwt_emit(const char *at, const struct dwt_snapshot *s) +{ + printf("D,%s,%u,%u,%u,%u,%u,%u\n", + at, + (unsigned)s->cyccnt, + (unsigned)s->cpicnt, + (unsigned)s->exccnt, + (unsigned)s->sleepcnt, + (unsigned)s->lsucnt, + (unsigned)s->foldcnt); +} diff --git a/benches/engine_control/src/smart_dwt.h b/benches/engine_control/src/smart_dwt.h new file mode 100644 index 00000000..fcb668c9 --- /dev/null +++ b/benches/engine_control/src/smart_dwt.h @@ -0,0 +1,63 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * Copyright (c) 2026 PulseEngine + * + * DWT counter snapshot for the silicon-anchor protocol. + * + * On ARMv7-M the DWT (Data Watchpoint and Trace) unit exposes six + * counters that quantify *why* a measured cycle count is what it + * is — not just "how long did this take" but how much of it was + * stalled on memory, on exceptions, on sleep, etc. A captured + * silicon run that records these alongside the event timestamps + * lets the analyzer discriminate "the runtime cost is real" from + * "the runtime cost is a microarchitectural artefact". + * + * CYCCNT — full 32-bit cycle counter (wraps at 2^32) + * CPICNT — 8-bit CPI overhead counter (extra cycles beyond 1 CPI) + * EXCCNT — 8-bit exception entry/exit overhead counter + * SLEEPCNT — 8-bit sleep cycles counter + * LSUCNT — 8-bit load/store unit additional cycles counter + * FOLDCNT — 8-bit folded-instruction counter + * + * The five 8-bit counters wrap at 256, so the protocol takes a + * snapshot at every RPM-step boundary; the analyzer computes + * wrap-aware deltas. CYCCNT is wide enough to be safe across the + * full sweep on any practical clock. + * + * On targets without a DWT unit (or where DWT is unimplemented in + * the simulator — qemu_cortex_m3 in particular), all reads return + * zero, so the row in the CSV is the literal value 0 across the + * board and analyze.py treats that as "DWT not available" rather + * than as a real measurement. + */ + +#ifndef GALE_BENCH_SMART_DWT_H +#define GALE_BENCH_SMART_DWT_H + +#include + +struct dwt_snapshot { + uint32_t cyccnt; + uint8_t cpicnt; + uint8_t exccnt; + uint8_t sleepcnt; + uint8_t lsucnt; + uint8_t foldcnt; +}; + +/* Enable trace + all six counters. Idempotent. Must be called once + * at boot before any snapshot. On targets without DWT this is a + * no-op (the writes to memory-mapped registers are absorbed by the + * simulator). */ +void smart_dwt_enable(void); + +/* Snapshot the current values. Cheap (six 32-bit MMIO reads). Safe + * to call from thread or ISR context. */ +void smart_dwt_snapshot(struct dwt_snapshot *out); + +/* Emit one CSV row of the form + * D,,,,,,, + * where is the event tag passed in (e.g. "boot", "step_3", "end"). */ +void smart_dwt_emit(const char *at, const struct dwt_snapshot *s); + +#endif /* GALE_BENCH_SMART_DWT_H */ diff --git a/benches/engine_control/src/smart_mcu.h b/benches/engine_control/src/smart_mcu.h new file mode 100644 index 00000000..732f259e --- /dev/null +++ b/benches/engine_control/src/smart_mcu.h @@ -0,0 +1,52 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * Copyright (c) 2026 PulseEngine + * + * MCU self-monitoring snapshot — vendor-neutral interface. + * + * "Smart data" beyond DWT counters: did the chip stay in spec while + * the bench was running? A capture made at +25 °C on cold silicon + * and one made at +85 °C with the regulator drooping are not the + * same measurement. We record the chip's own telemetry so the + * analyzer can flag a thermal- or supply-related anomaly rather + * than mis-attributing it to the gale primitives. + * + * Each backend (smart_mcu_g4.c, smart_mcu_stub.c) implements this + * interface for its target. The stub is selected for any board + * that doesn't have a vendor-specific backend; it returns the + * "not available" marker so the CSV row format stays the same. + * + * H,,,, + * + * `vbat_mV` is reported as 0 on parts without a VBAT divider channel. + * Any field marked unavailable on a given backend is reported as 0 + * with a one-time `# H : not available on this target` + * comment line at boot. + */ + +#ifndef GALE_BENCH_SMART_MCU_H +#define GALE_BENCH_SMART_MCU_H + +#include + +struct mcu_health { + int32_t temp_mC; /* die temperature in milli-degrees C */ + uint32_t vref_mV; /* internal reference voltage, milli-volts */ + uint32_t vbat_mV; /* VBAT pin voltage, mV; 0 if unavailable */ +}; + +/* One-time init: opens the ADC + reads vendor calibration ROM. + * Returns 0 on success; non-zero leaves the backend in + * "snapshot returns zeroed health" mode (still safe to call). + * Always emits a banner comment summarising what's available. */ +int smart_mcu_init(void); + +/* Snapshot the current readings. Reads ADC channels — costs a few + * tens of microseconds. Safe from thread context only. */ +void smart_mcu_snapshot(struct mcu_health *out); + +/* Emit one CSV row: + * H,,,, */ +void smart_mcu_emit(const char *at, const struct mcu_health *h); + +#endif /* GALE_BENCH_SMART_MCU_H */ diff --git a/benches/engine_control/src/smart_mcu_g4.c b/benches/engine_control/src/smart_mcu_g4.c new file mode 100644 index 00000000..b64e52fb --- /dev/null +++ b/benches/engine_control/src/smart_mcu_g4.c @@ -0,0 +1,164 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * Copyright (c) 2026 PulseEngine + * + * STM32G4 MCU self-monitoring — die temperature and internal + * reference voltage via ADC1. + * + * Calibration locations and formulas per STMicroelectronics + * RM0440 (STM32G4 reference manual) §3.7.1 "Boot and start-up + * memory areas" and §21 "ADC". + * + * TS_CAL1 at 0x1FFF75A8 — TS reading at 30 °C, VDDA = 3.0 V + * TS_CAL2 at 0x1FFF75CA — TS reading at 130 °C, VDDA = 3.0 V + * VREFINT_CAL at 0x1FFF75AA — VREFINT reading at 30 °C, 3.0 V + * + * Formulas (RM0440 §21.4.32, §21.4.33): + * + * actual_VREF_mV = 3000 * VREFINT_CAL / raw_VREFINT + * + * temp_C = ((TS_CAL2_TEMP_C - TS_CAL1_TEMP_C) * (raw_TS_at_3V0 - TS_CAL1)) + * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP_C + * + * raw_TS_at_3V0 = raw_TS * actual_VREF_mV / 3000 + * (correct the TS reading back to the calibration condition) + * + * VBAT is not exposed as an ADC channel on this Nucleo configuration + * (no battery input), so we always report 0 for vbat_mV. + */ + +#include +#include +#include +#include +#include + +#include "smart_mcu.h" + +#define ADC_NODE DT_NODELABEL(adc1) +#define ADC_RESOLUTION 12 + +#define ADC_CH_TS 16 +#define ADC_CH_VREFINT 18 + +#define TS_CAL1_ADDR ((const volatile uint16_t *)0x1FFF75A8u) +#define TS_CAL2_ADDR ((const volatile uint16_t *)0x1FFF75CAu) +#define VREFINT_CAL_ADDR ((const volatile uint16_t *)0x1FFF75AAu) +#define TS_CAL1_TEMP_C 30 +#define TS_CAL2_TEMP_C 130 +#define CAL_VREF_MV 3000 + +static const struct device *s_adc; +static int s_init_ok; + +static int read_one(uint8_t channel_id, int16_t *out) +{ + int16_t buf; + struct adc_sequence seq = { + .channels = BIT(channel_id), + .buffer = &buf, + .buffer_size = sizeof(buf), + .resolution = ADC_RESOLUTION, + }; + int ret = adc_read(s_adc, &seq); + if (ret == 0) { + *out = buf; + } + return ret; +} + +static int setup_channel(uint8_t channel_id) +{ + struct adc_channel_cfg cfg = { + .gain = ADC_GAIN_1, + .reference = ADC_REF_INTERNAL, + .acquisition_time = ADC_ACQ_TIME_MAX, + .channel_id = channel_id, + .differential = 0, + }; + return adc_channel_setup(s_adc, &cfg); +} + +int smart_mcu_init(void) +{ + s_adc = DEVICE_DT_GET(ADC_NODE); + if (!device_is_ready(s_adc)) { + printf("# H init: ADC1 device not ready — DT overlay missing?\n"); + return -1; + } + if (setup_channel(ADC_CH_TS) != 0) { + printf("# H init: ADC1 ch%u (TS) setup failed\n", ADC_CH_TS); + return -2; + } + if (setup_channel(ADC_CH_VREFINT) != 0) { + printf("# H init: ADC1 ch%u (VREFINT) setup failed\n", + ADC_CH_VREFINT); + return -3; + } + s_init_ok = 1; + printf("# H ready: temp_mC,vref_mV via ADC1 ch%u + ch%u; " + "VBAT not wired (always 0)\n", + ADC_CH_TS, ADC_CH_VREFINT); + printf("# H cal: TS_CAL1=%u@%dC TS_CAL2=%u@%dC VREFINT_CAL=%u@%dmV\n", + (unsigned)*TS_CAL1_ADDR, TS_CAL1_TEMP_C, + (unsigned)*TS_CAL2_ADDR, TS_CAL2_TEMP_C, + (unsigned)*VREFINT_CAL_ADDR, CAL_VREF_MV); + return 0; +} + +void smart_mcu_snapshot(struct mcu_health *out) +{ + out->vbat_mV = 0; + + if (!s_init_ok) { + out->temp_mC = 0; + out->vref_mV = 0; + return; + } + + int16_t raw_ts = 0, raw_vref = 0; + if (read_one(ADC_CH_VREFINT, &raw_vref) != 0 || raw_vref == 0) { + out->temp_mC = 0; + out->vref_mV = 0; + return; + } + if (read_one(ADC_CH_TS, &raw_ts) != 0) { + out->temp_mC = 0; + out->vref_mV = (uint32_t)CAL_VREF_MV + * (uint32_t)*VREFINT_CAL_ADDR + / (uint32_t)raw_vref; + return; + } + + uint32_t vref_cal = *VREFINT_CAL_ADDR; + uint32_t actual_vref_mV = (uint32_t)CAL_VREF_MV * vref_cal + / (uint32_t)raw_vref; + + /* Correct TS reading to the calibration's 3.0 V condition. + * raw_TS_at_3V0 = raw_TS * actual_VREF / 3.0V */ + int32_t raw_ts_at_3v0 = (int32_t)raw_ts + * (int32_t)actual_vref_mV + / CAL_VREF_MV; + + int32_t ts_cal1 = (int32_t)*TS_CAL1_ADDR; + int32_t ts_cal2 = (int32_t)*TS_CAL2_ADDR; + int32_t span_cal = ts_cal2 - ts_cal1; + if (span_cal == 0) { + /* Defensive: corrupted calibration ROM. */ + out->temp_mC = 0; + } else { + int32_t temp_C_x1000 = + (int32_t)(TS_CAL2_TEMP_C - TS_CAL1_TEMP_C) * 1000 + * (raw_ts_at_3v0 - ts_cal1) / span_cal + + TS_CAL1_TEMP_C * 1000; + out->temp_mC = temp_C_x1000; + } + out->vref_mV = actual_vref_mV; +} + +void smart_mcu_emit(const char *at, const struct mcu_health *h) +{ + printf("H,%s,%d,%u,%u\n", + at, (int)h->temp_mC, (unsigned)h->vref_mV, + (unsigned)h->vbat_mV); +} diff --git a/benches/engine_control/src/smart_mcu_stub.c b/benches/engine_control/src/smart_mcu_stub.c new file mode 100644 index 00000000..47379471 --- /dev/null +++ b/benches/engine_control/src/smart_mcu_stub.c @@ -0,0 +1,38 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * Copyright (c) 2026 PulseEngine + * + * MCU self-monitoring — fallback stub for boards without a + * vendor-specific backend (qemu_cortex_m3, mps2/an385, etc.). + * + * Every reading is reported as 0 / "unavailable". The CSV row + * format stays identical so analyze.py can ingest captures from + * stub and full-backend boards uniformly; the analyzer treats an + * all-zero H row as "no MCU health on this target" rather than + * "the chip is dead". + */ + +#include +#include + +#include "smart_mcu.h" + +int smart_mcu_init(void) +{ + printf("# H temp_mC,vref_mV,vbat_mV: not available on this target " + "(stub backend)\n"); + return -1; +} + +void smart_mcu_snapshot(struct mcu_health *out) +{ + out->temp_mC = 0; + out->vref_mV = 0; + out->vbat_mV = 0; +} + +void smart_mcu_emit(const char *at, const struct mcu_health *h) +{ + printf("H,%s,%d,%u,%u\n", + at, (int)h->temp_mC, (unsigned)h->vref_mV, (unsigned)h->vbat_mV); +} diff --git a/benches/engine_control/tag_events.py b/benches/engine_control/tag_events.py index f81cf4d6..3220c734 100644 --- a/benches/engine_control/tag_events.py +++ b/benches/engine_control/tag_events.py @@ -26,6 +26,12 @@ def main(argv: list[str]) -> int: continue if line.startswith("E,"): print(f"R{run_id},{variant},{line}") + elif line.startswith("D,") or line.startswith("H,"): + # Smart-data rows (DWT counters, MCU health + # snapshots) — same R, prefix as + # event rows so analyze.py can join them against + # the per-run / per-variant samples. + print(f"R{run_id},{variant},{line}") elif (line.startswith("drops,") or line.startswith("samples,")): print(f"M,R{run_id},{variant},{line}") diff --git a/benches/flight_control/CMakeLists.txt b/benches/flight_control/CMakeLists.txt index 59da56ae..36bcd6a2 100644 --- a/benches/flight_control/CMakeLists.txt +++ b/benches/flight_control/CMakeLists.txt @@ -24,10 +24,55 @@ project(gale_flight_control) target_sources(app PRIVATE src/main.c - src/control.c ) target_include_directories(app PRIVATE src) +# -------------------------------------------------------------------------- +# GALE_FC_WASM_LTO (opt-in, default OFF): build the flight algorithm +# (filter_step + controller_step) via the wasm-cross-LTO pipeline +# (clang -> wasm-ld -> loom dissolve -> synth -> Cortex-M object) instead of +# the native src/control.c, so the bench measures the dissolved algorithm +# head-to-head with the native build. Cortex-M4F target (nucleo_g474re); +# needs clang(wasm32), wasm-ld, loom, synth on PATH. A thin r11=0 trampoline +# (wasm/control_wasm_tramp.S) bridges Zephyr's calling convention to synth's +# linear-memory-base addressing. Functionally verified identical to native +# (cmd=0x07FDF307 on the reference vector). See ../engine_control/silicon/. +# -------------------------------------------------------------------------- +option(GALE_FC_WASM_LTO + "Link filter_step/controller_step via wasm-cross-LTO (synth Cortex-M) instead of native C" OFF) + +if(GALE_FC_WASM_LTO) + find_program(GALE_WLTO_CLANG clang REQUIRED) + find_program(GALE_WLTO_WASMLD wasm-ld REQUIRED) + find_program(GALE_WLTO_LOOM loom REQUIRED) + find_program(GALE_WLTO_SYNTH synth REQUIRED) + set(_fc_src ${CMAKE_CURRENT_SOURCE_DIR}/src/control.c) + set(_fc_o ${CMAKE_CURRENT_BINARY_DIR}/control_wasm.o) + add_custom_command( + OUTPUT ${_fc_o} + COMMENT "flight_control: dissolving control.c via wasm-cross-LTO (clang->wasm-ld->loom->synth)" + COMMAND ${GALE_WLTO_CLANG} --target=wasm32-unknown-unknown -O2 -nostdlib + -I${CMAKE_CURRENT_SOURCE_DIR}/src -c ${_fc_src} -o control.wasm.o + COMMAND ${GALE_WLTO_WASMLD} --no-entry --export=filter_step --export=controller_step + --allow-undefined --gc-sections control.wasm.o -o control.wasm + COMMAND ${GALE_WLTO_LOOM} optimize control.wasm --passes inline --attestation false + -o control.loom.wasm + COMMAND ${GALE_WLTO_SYNTH} compile control.loom.wasm --target cortex-m4f + --all-exports --relocatable -o control.synth.o + COMMAND ${CMAKE_OBJCOPY} --redefine-sym filter_step=synth_filter_step + --redefine-sym controller_step=synth_controller_step control.synth.o ${_fc_o} + DEPENDS ${_fc_src} + WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} + VERBATIM) + add_custom_target(gale_fc_control_wasm DEPENDS ${_fc_o}) + set_source_files_properties(${_fc_o} PROPERTIES EXTERNAL_OBJECT TRUE GENERATED TRUE) + target_sources(app PRIVATE wasm/control_wasm_tramp.S ${_fc_o}) + add_dependencies(app gale_fc_control_wasm) + message(STATUS "flight_control: GALE_FC_WASM_LTO ON — control.c via wasm-cross-LTO (cortex-m4f)") +else() + target_sources(app PRIVATE src/control.c) +endif() + # -DENGINE_BENCH_TOTAL_SAMPLES / -DENGINE_BENCH_SWEEP override the # defaults in main.c. Reuses the engine_control naming so existing # CI plumbing (run_qemu_bench.sh, env conventions) translates 1:1. diff --git a/benches/flight_control/runs/2026-06-05-g474re-native-algo141.txt b/benches/flight_control/runs/2026-06-05-g474re-native-algo141.txt new file mode 100644 index 00000000..3702b30b --- /dev/null +++ b/benches/flight_control/runs/2026-06-05-g474re-native-algo141.txt @@ -0,0 +1,20 @@ +*** Booting Zephyr OS build v4.4.0-7-g719cc4890346 *** +flight_control bench starting (target 50 samples, 5 sweep steps) +=== FLIGHT-CONTROL BENCH RESULTS === +build,gale +cycles_per_sec,170000000 +target_samples,50 +# event rows: E,,,,,,,,, +# step 1/5 sensor_hz=500 contention=0 payload=16 ints=30 expected=6 count=0 [drain_timeout] +# step 2/5 sensor_hz=1000 contention=0 payload=32 ints=30 expected=3 count=0 [drain_timeout] +# step 3/5 sensor_hz=1000 contention=1 payload=32 ints=30 expected=3 count=0 [drain_timeout] +E,68,2,2000,141,1336,484,845,3320,-1 +E,78,2,2000,141,1336,484,845,3320,-1 +E,88,2,2000,141,1336,4228,845,3345,-1 +E,89,2,2000,141,1336,484,845,3571,417 +E,107,3,2000,141,133# step 4/5 sensor_hz=2000 contention=0 payload=32 ints=30 expected=1 count=4 +# step 5/5 sensor_hz=2000 contention=2 payload=64 ints=30 expected=1 count=0 [drain_timeout] +6,484,833,2078,-1 +E,119,3,18384,141,1336,484,857,6503,867 +E,133,4,18384,141,1336,484,857,6445,-1 +E,149,4,18384,141,1336,484,833,2262,417 diff --git a/benches/flight_control/runs/2026-06-05-g474re-wasmLTO-algo157.txt b/benches/flight_control/runs/2026-06-05-g474re-wasmLTO-algo157.txt new file mode 100644 index 00000000..c464eb35 --- /dev/null +++ b/benches/flight_control/runs/2026-06-05-g474re-wasmLTO-algo157.txt @@ -0,0 +1,27 @@ +*** Booting Zephyr OS build v4.4.0-7-g719cc4890346 *** +flight_control bench starting (target 50 samples, 5 sweep steps) +=== FLIGHT-CONTROL BENCH RESULTS === +build,gale +cycles_per_sec,170000000 +target_samples,50 +# event rows: E,,,,,,,,, +E,4,0,500,157,1359,486,868,2091,-1 +E,9,0,500,157,1359,486,868,2091,936 +E,14,0,500,157,1359,486,868,2091,-1 +E,19,0,500,157,1359,486,868,2091,936 +E,24,0,500,157,1359,486,868,2091,-1 +E,29,0,500,157,1359,486,868,2041,936 +# step 1/5 sensor_hz=500 contention=0 payload=16 ints=30 expected=6 count=6 +# step 2/5 sensor_hz=1000 contention=0 payload=32 ints=30 expected=3 count=0 [drain_timeout] +# step 3/5 sensor_hz=1000 contention=1 payload=32 ints=30 expected=3 count=0 [drain_timeout] +E,67,2,2000,157,1359,486,880,4272,-1 +E,77,2,2000,157,1359,486,880,3319,-1 +E,87,2,2000,157,1359,486,880,3319,-1 +E,89,2,2000,157,1359,3774,880,3347,502 +E,99,3,2000,157,1359# step 4/5 sensor_hz=2000 contention=0 payload=32 ints=30 expected=1 count=4 +# step 5/5 sensor_hz=2000 contention=2 payload=64 ints=30 expected=1 count=0 [drain_timeout] +,486,868,8674,951 +E,119,3,18384,157,1359,486,892,6497,939 +E,126,4,18384,157,1359,486,892,6478,-1 +E,146,4,18384,157,1359,486,892,6478,-1 +E,149,4,18384,157,1359,486,868,2265,502 diff --git a/benches/flight_control/runs/RESULT-2026-06-13-g474re-v0.11.41.txt b/benches/flight_control/runs/RESULT-2026-06-13-g474re-v0.11.41.txt new file mode 100644 index 00000000..2962d22f --- /dev/null +++ b/benches/flight_control/runs/RESULT-2026-06-13-g474re-v0.11.41.txt @@ -0,0 +1,6 @@ +# flight_control Phase-5 macro bench, GALE_FC_WASM_LTO=ON, G474RE, synth 0.11.41 + loom 1.1.13 +# 5-step sweep, no fault. Event format: E,seq,step,load,algo,handoff,t_lock,t_post,t_round,t_bcast +E,149,4,18384,157,1339,3971,951,4848,327 +E,68,2,2000,157,1339,344,936,4058,-1 +# in-bench algo = 157 cyc (min=median=max, n=9) wasm-cross-LTO; native ref 141 (gcc -O2) = 1.11x. +# Re-confirms the ~11% composed-context overhead on the post-#331 toolchain (was 157 at v0.11.30 too). diff --git a/benches/flight_control/wasm/README.md b/benches/flight_control/wasm/README.md new file mode 100644 index 00000000..91e8556a --- /dev/null +++ b/benches/flight_control/wasm/README.md @@ -0,0 +1,25 @@ +# flight_control wasm-cross-LTO variant + +Builds the flight algorithm (`filter_step` + `controller_step` from `../src/control.c`) +through the wasm-cross-LTO pipeline instead of native C, so the bench measures the +dissolved algorithm head-to-head with the native build (Phase 5). + +```sh +west build -b nucleo_g474re -s benches/flight_control -- -DGALE_FC_WASM_LTO=ON +# needs clang(wasm32) + wasm-ld + loom + synth on PATH +``` + +Pipeline (in CMakeLists.txt, `add_custom_command`): +`clang --target=wasm32 -O2` → `wasm-ld --export=filter_step --export=controller_step` +→ `loom optimize --passes inline` (dissolves the seam) → `synth compile --target cortex-m4f` +→ `objcopy --redefine-sym` (rename exports to `synth_*`) → `control_wasm.o`. + +`control_wasm_tramp.S` provides `filter_step`/`controller_step`: thin wrappers that set +`r11 = 0` (synth's wasm linear-memory base — `[r11+ptr] == [ptr]`, native pointer deref), +call the `synth_*` body, and restore `r11`. synth passes the ≤2 pointer args in r0/r1, so +no stack-arg handling is needed. + +Functionally verified identical to native: on the reference vector +(st pitch=1000 roll=−500 yaw=200 updates=7; imu gyro=100,−50,30 accel=300,−200) +→ `cmd=0x07FDF307`, state pitch=937 roll=−396 yaw=230 — bit-identical to `control.c`, +including when called with a garbage incoming `r11` (the trampoline zeroes it). diff --git a/benches/flight_control/wasm/control_wasm_tramp.S b/benches/flight_control/wasm/control_wasm_tramp.S new file mode 100644 index 00000000..d368733a --- /dev/null +++ b/benches/flight_control/wasm/control_wasm_tramp.S @@ -0,0 +1,25 @@ +/* wasm-cross-LTO trampoline for flight_control: the bench's filter_step / + * controller_step are dissolved (clang->wasm-ld->loom->synth) into + * synth_filter_step / synth_controller_step, which address their pointer + * args via the wasm linear-memory base register r11. Zephyr/the bench call + * with r11 as an ordinary frame pointer, so these thin wrappers set r11=0 + * ([r11+ptr] == [ptr], native deref), call the synth body, and restore. */ + .syntax unified + .thumb + .section .text.gale_fc_tramp,"ax",%progbits + + .global filter_step + .thumb_func +filter_step: + push {r11, lr} + mov.w r11, #0 + bl synth_filter_step + pop {r11, pc} + + .global controller_step + .thumb_func +controller_step: + push {r11, lr} + mov.w r11, #0 + bl synth_controller_step + pop {r11, pc} diff --git a/zephyr/CMakeLists.txt b/zephyr/CMakeLists.txt index deb046b8..6637f697 100644 --- a/zephyr/CMakeLists.txt +++ b/zephyr/CMakeLists.txt @@ -443,6 +443,18 @@ zephyr_library_include_directories( zephyr_library_link_libraries(${GALE_FFI_LIB}) add_dependencies(gale_sem gale_ffi_build) +# wasm-cross-LTO sem variant: -DGALE_WASM_LTO_SEM_LIB= +# excludes the native z_impl_k_sem_give and links the synth-compiled, +# loom-inlined (seam-dissolved) z_impl + fp=0 trampoline instead. +if(DEFINED GALE_WASM_LTO_SEM_LIB) + message(STATUS "Gale: wasm-cross-LTO sem override -> ${GALE_WASM_LTO_SEM_LIB}") + zephyr_library_compile_definitions(GALE_WASM_LTO_OVERRIDE_SEM_GIVE=1) + # out-of-line wrappers for inline-only kernel APIs (k_spin_lock etc.) + # that the synth object calls; built WITH Zephyr headers. + zephyr_library_sources(gale_wasm_wrappers.c) + zephyr_library_link_libraries(${GALE_WASM_LTO_SEM_LIB}) +endif() + endif() # CONFIG_GALE_KERNEL_SEM # ========================================================================== @@ -540,6 +552,20 @@ zephyr_library_include_directories( zephyr_library_link_libraries(${GALE_FFI_LIB}) add_dependencies(gale_mutex gale_ffi_build) +# wasm-cross-LTO mutex variant: -DGALE_WASM_LTO_MUTEX_LIB= +# excludes the native z_impl_k_mutex_unlock and links the synth-compiled, +# loom-inlined (seam-dissolved) z_impl instead. Mirrors GALE_WASM_LTO_SEM_LIB. +if(DEFINED GALE_WASM_LTO_MUTEX_LIB) + message(STATUS "Gale: wasm-cross-LTO mutex override -> ${GALE_WASM_LTO_MUTEX_LIB}") + zephyr_library_compile_definitions(GALE_WASM_LTO_OVERRIDE_MUTEX_UNLOCK=1) + # out-of-line wrappers for inline-only kernel APIs the synth object calls. + # Avoid double-adding if the sem variant already pulled them in. + if(NOT DEFINED GALE_WASM_LTO_SEM_LIB) + zephyr_library_sources(gale_wasm_wrappers.c) + endif() + zephyr_library_link_libraries(${GALE_WASM_LTO_MUTEX_LIB}) +endif() + endif() # CONFIG_GALE_KERNEL_MUTEX # ========================================================================== diff --git a/zephyr/gale_mutex.c b/zephyr/gale_mutex.c index a38104e4..9312ad1c 100644 --- a/zephyr/gale_mutex.c +++ b/zephyr/gale_mutex.c @@ -234,6 +234,14 @@ static inline int z_vrfy_k_mutex_lock(struct k_mutex *mutex, #include #endif /* CONFIG_USERSPACE */ +/* GALE_WASM_LTO_OVERRIDE_MUTEX_UNLOCK: when defined, z_impl_k_mutex_unlock is + * supplied instead by the wasm-cross-LTO object (libwasmmutex.a): this C body + * compiled clang->wasm-ld->loom(inline, seam dissolved)->synth to Cortex-M, + * with gale_k_mutex_unlock_decide folded in. The synth object's kernel-API + * imports are objcopy-renamed to the gale_w_* out-of-line wrappers + * (gale_wasm_wrappers.c). Mirrors GALE_WASM_LTO_OVERRIDE_SEM_GIVE; used only by + * the mutex wasm-LTO bench variant — default builds keep this native one. */ +#ifndef GALE_WASM_LTO_OVERRIDE_MUTEX_UNLOCK int z_impl_k_mutex_unlock(struct k_mutex *mutex) { struct k_thread *new_owner; @@ -311,6 +319,7 @@ int z_impl_k_mutex_unlock(struct k_mutex *mutex) return 0; } +#endif /* GALE_WASM_LTO_OVERRIDE_MUTEX_UNLOCK */ #ifdef CONFIG_USERSPACE static inline int z_vrfy_k_mutex_unlock(struct k_mutex *mutex) diff --git a/zephyr/gale_sem.c b/zephyr/gale_sem.c index 4dc37a36..e714882b 100644 --- a/zephyr/gale_sem.c +++ b/zephyr/gale_sem.c @@ -86,6 +86,14 @@ int z_vrfy_k_sem_init(struct k_sem *sem, unsigned int initial_count, #include #endif /* CONFIG_USERSPACE */ +/* GALE_WASM_LTO_OVERRIDE_SEM_GIVE: when defined, z_impl_k_sem_give is + * supplied instead by the wasm-cross-LTO object (libwasmsem.a): the C + * shim's z_impl_k_sem_give compiled clang->wasm-ld->loom(inline)->synth + * to ARM, with gale_k_sem_give_decide inlined (seam dissolved). A native + * trampoline zeroes the wasm linmem-base reg (fp) so the synth body's + * [fp+ptr] addressing dereferences the real k_sem. Used only by the + * silicon wasm-LTO bench variant; default builds keep the native one. */ +#ifndef GALE_WASM_LTO_OVERRIDE_SEM_GIVE void z_impl_k_sem_give(struct k_sem *sem) { k_spinlock_key_t key = k_spin_lock(&lock); @@ -123,6 +131,7 @@ void z_impl_k_sem_give(struct k_sem *sem) SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_sem, give, sem); } +#endif /* GALE_WASM_LTO_OVERRIDE_SEM_GIVE */ #ifdef CONFIG_USERSPACE static inline void z_vrfy_k_sem_give(struct k_sem *sem) diff --git a/zephyr/gale_wasm_wrappers.c b/zephyr/gale_wasm_wrappers.c new file mode 100644 index 00000000..0c29e2fb --- /dev/null +++ b/zephyr/gale_wasm_wrappers.c @@ -0,0 +1,67 @@ +/* + * Out-of-line wrappers for the wasm-cross-LTO sem variant. + * + * The wasm shim (compiled clang->wasm-ld->loom->synth) calls the Zephyr + * kernel APIs as out-of-line functions. Several of those — k_spin_lock, + * k_spin_unlock, arch_thread_return_value_set — are `static inline` in + * Zephyr headers, so they have no linkable symbol. These thin wrappers + * (built WITH the Zephyr headers) provide out-of-line entry points; the + * synth object's imports are objcopy-renamed to call gale_w_* instead. + * + * The spinlock wrappers ignore the pointer the wasm shim passes (it is a + * wasm-linear-memory address, not a real lock) and use a real kernel-RAM + * spinlock instead — correct and avoids touching the wasm linmem region. + * + * Only compiled when GALE_WASM_LTO_OVERRIDE_SEM_GIVE is defined. + */ +#include +#include +#include +#include + +static struct k_spinlock gale_wasm_lock; + +k_spinlock_key_t gale_w_spin_lock(struct k_spinlock *ignored) +{ + ARG_UNUSED(ignored); + return k_spin_lock(&gale_wasm_lock); +} + +void gale_w_spin_unlock(struct k_spinlock *ignored, k_spinlock_key_t key) +{ + ARG_UNUSED(ignored); + k_spin_unlock(&gale_wasm_lock, key); +} + +int gale_w_reschedule(struct k_spinlock *ignored, k_spinlock_key_t key) +{ + ARG_UNUSED(ignored); + z_reschedule(&gale_wasm_lock, key); /* z_reschedule is void here */ + return 0; /* wasm shim expects an i32 (dropped) */ +} + +struct k_thread *gale_w_unpend_first_thread(_wait_q_t *wait_q) +{ + return z_unpend_first_thread(wait_q); +} + +void gale_w_ready_thread(struct k_thread *thread) +{ + z_ready_thread(thread); +} + +void gale_w_arch_thread_return_value_set(struct k_thread *thread, unsigned int value) +{ + arch_thread_return_value_set(thread, value); +} + +/* Out-of-line _current accessor for the wasm-cross-LTO MUTEX shim + * (wasm_mutex_shim_poc.c): _current is a macro (z_smp_current_get() / + * _kernel.cpus[].current) with no linkable symbol, so the dissolved + * z_impl_k_mutex_unlock imports gale_w_current instead. The mutex shim + * reuses every other gale_w_* wrapper above (spinlock, unpend, ready, + * reschedule, return_value_set) unchanged — only this one is new. */ +struct k_thread *gale_w_current(void) +{ + return _current; +}